1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
10 #include <cpu/amd/gx2def.h>
11 #include <cpu/x86/msr.h>
12 #include <cpu/x86/cache.h>
20 msr.whatever |= ID_CONFIG_SERIAL_SET;
28 msr = rdmsr(MC_GLD_MSR_PM);
38 msr = rdmsr(CPU_DM_CONFIG0);
39 msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
40 msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
41 msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
42 wrmsr(CPU_DM_CONFIG0, msr);
46 msr = rdmsr(CPU_IM_CONFIG);
47 msr.lo |= IM_CONFIG_LOWER_QWT_SET; /* interlock instruction fetches to WS regions with data accesses.
48 * This prevents in instruction fetch from going out to PCI if the
49 * data side is about to make a request.
51 wrmsr(CPU_IM_CONFIG, msr);
52 /* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility.*/
56 wrmsr( CPU_RCONF_A0_BF, msr);
57 wrmsr( CPU_RCONF_C0_DF, msr);
58 wrmsr( CPU_RCONF_E0_FF, msr);
61 /****************************************************************************/
65 /** Bugtool #784 + #792*/
67 /** Fix CPUID instructions for < 3.0 CPUs*/
73 /****************************************************************************/
77 // static char *name = "Geode by NSC";
79 /* we'll do this the stupid way, for now, but that's the string they want. NO ONE KNOWS why you
80 * would do this -- the OS can figure this type of stuff out!
94 /* More CPUID to match AMD better. #792*/
101 /* cpubug 1398: enable MC if we KNOW we have DDR*/
106 msr = rdmsr(MSR_GLCP+0x17);
107 if ((msr.lo & 0xff) < CPU_REV_2_0) {
108 msr = rdmsr(GLCP_SYS_RSTPLL);
109 if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT))
113 /* no bios to check, we just go for it? */
114 msr = rdmsr(MC_GLD_MSR_PM);
115 msr.lo |= 3; /* enable MC clock gating.*/
116 wrmsr(MC_GLD_MSR_PM, msr);
121 printk_err(" NOT DOING eng2900: only shown to be a windows problem\n");
124 ;**************************************************************************
128 ;* Clear Quest IAENG00002900, VSS 118.150
130 ;* BTB issue causes blue screen in windows.
136 ;**************************************************************************
137 CPUbugIAENG2900 PROC NEAR PUBLIC
140 ; Clear bit 43, disables the sysenter/sysexit in CPUID3
146 mov cx, TOKEN_BTB_2900_SWAPSIF_ENABLE
147 NOSTACK bx, GetNVRAMValueBX
148 cmp ax, TVALUE_ENABLE
152 ;Disable enable_actions in DIAGCTL while setting up GLCP
153 mov ecx, MSR_GLCP + 005fh
158 ;Changing DBGCLKCTL register to GeodeLink
159 mov ecx, MSR_GLCP + 0016h
164 mov ecx, MSR_GLCP + 0016h
169 ;The code below sets up the RedCloud to stall for 4 GeodeLink clocks when CPU is snooped.
170 ;Because setting XSTATE to 0 overrides any other XSTATE action, the code will always
171 ;stall for 4 GeodeLink clocks after a snoop request goes away even if it occured a clock or two
172 ;later than a different snoop; the stall signal will never 'glitch high' for
173 ;only one or two CPU clocks with this code.
175 ;Send mb0 port 3 requests to upper GeodeLink diag bits [63:32]
176 mov ecx, MSR_GLIU0 + 2005h
181 ;set5m watches request ready from mb0 to CPU (snoop)
182 mov ecx, MSR_GLCP + 0045h
187 ;SET4M will be high when state is idle (XSTATE=11)
188 mov ecx, MSR_GLCP + 0044h
193 ;SET5n to watch for processor stalled state
194 mov ecx, MSR_GLCP + 004Dh
199 ;Writing action number 13: XSTATE=0 to occur when CPU is snooped unless we're stalled
200 mov ecx, MSR_GLCP + 0075h
205 ;Writing action number 11: inc XSTATE every GeodeLink clock unless we're idle
206 mov ecx, MSR_GLCP + 0073h
212 ;Writing action number 5: STALL_CPU_PIPE when exitting idle state or not in idle state
213 mov ecx, MSR_GLCP + 006Dh
218 ;Writing DIAGCTL Register to enable the stall action and to let set5m watch the upper GeodeLink diag bits.
219 mov ecx, MSR_GLCP + 005fh
232 void bug118253(void){
235 msr = rdmsr(GLPCI_SPARE);
236 msr.lo &= ~GLPCI_SPARE_LOWER_PPC_SET;
237 wrmsr(GLPCI_SPARE, msr);
242 printk_err("This is OPTIONAL BIOS-ENABLED ... ignore for now\n");
247 mov cx, TOKEN_VGTEAR_118339_SWAPSIF_ENABLE
248 NOSTACK bx, GetNVRAMValueBX
249 cmp ax, TVALUE_ENABLE
252 ;Disable enable_actions in DIAGCTL while setting up GLCP
253 mov ecx, MSR_GLCP + 005fh
258 ; SET2M fires if VG pri is odd (3, not 2) and Ystate=0
259 mov ecx, MSR_GLCP + 042h
265 ; SET3M fires if MBUS changed and VG pri is odd
266 mov ecx, MSR_GLCP + 043h
271 ; Put VG request data on lower diag bus
272 mov ecx, MSR_GLIU0 + 2005h
277 ; Increment Y state if SET3M if true
278 mov ecx, MSR_GLCP + 074h
283 ; Set up MBUS action to PRI=3 read of MBIU
284 mov ecx, MSR_GLCP + 020h
289 ; Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI
290 mov ecx, MSR_GLCP + 071h
296 mov ecx, MSR_GLCP + 005fh
301 ; Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled
302 ; As per Todd Roberts in PBz1094 and PBz1095
303 ; Moved from CPUREG to CPUBUG per Tom Sylla
304 mov ecx, 04C000042h ; GLCP SETMCTL Register
306 or edx, 8 ; Bit 35 = MCP_IN
318 /****************************************************************************/
320 /** DisableMemoryReorder*/
323 /** The MC reordered transactions incorrectly and breaks coherency.*/
324 /** Disable reording and take a potential performance hit.*/
325 /** This is safe to do here and not in MC init since there is nothing*/
326 /** to maintain coherency with and the cache is not enabled yet.*/
333 /****************************************************************************/
335 disablememoryreadorder(void) {
337 msr = rdmsr(MC_CF8F_DATA);
339 msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
340 wrmsr(MC_CF8F_DATA, msr);
347 msr = rdmsr(GLCP_CHIP_REVID);
351 printk_err("%s: rev < 0x20! bailing!\n");
354 printk_debug("Doing cpubug fixes for rev 0x%x\n", rev);
360 /* cs 5530 bug; ignore
374 printk_err("unknown rev %x, bailing\n", rev);
379 disablememoryreadorder();
380 printk_debug("Done cpubug fixes \n");