1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
10 #include <cpu/amd/gx2def.h>
11 #include <cpu/x86/msr.h>
12 #include <cpu/x86/cache.h>
20 msr.whatever |= ID_CONFIG_SERIAL_SET;
28 msr = rdmsr(MC_GLD_MSR_PM);
39 msr = rdmsr(CPU_DM_CONFIG0);
40 msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
41 msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
42 msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
43 wrmsr(CPU_DM_CONFIG0, msr);
45 msr = rdmsr(CPU_IM_CONFIG);
46 msr.lo |= IM_CONFIG_LOWER_QWT_SET; /* interlock instruction fetches to WS regions with data accesses.
47 * This prevents in instruction fetch from going out to PCI if the
48 * data side is about to make a request.
50 wrmsr(CPU_IM_CONFIG, msr);
51 /* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility.*/
55 wrmsr( CPU_RCONF_A0_BF, msr);
56 wrmsr( CPU_RCONF_C0_DF, msr);
57 wrmsr( CPU_RCONF_E0_FF, msr);
60 /****************************************************************************/
64 /** Bugtool #784 + #792*/
66 /** Fix CPUID instructions for < 3.0 CPUs*/
72 /****************************************************************************/
77 //static char *name = "Geode by NSC";
79 /* we'll do this the stupid way, for now, but that's the string they want. NO ONE KNOWS why you
80 * would do this -- the OS can figure this type of stuff out!
94 /* More CPUID to match AMD better. #792*/
101 /* cpubug 1398: enable MC if we KNOW we have DDR*/
106 msr = rdmsr(MSR_GLCP+0x17);
107 if ((msr.lo & 0xff) < CPU_REV_2_0) {
108 msr = rdmsr(GLCP_SYS_RSTPLL);
109 if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT))
113 /* no bios to check, we just go for it? */
114 msr = rdmsr(MC_GLD_MSR_PM);
115 msr.lo |= 3; /* enable MC clock gating.*/
116 wrmsr(MC_GLD_MSR_PM, msr);
121 printk_err(" NOT DOING eng2900: only shown to be a windows problem\n");
124 ;**************************************************************************
128 ;* Clear Quest IAENG00002900, VSS 118.150
130 ;* BTB issue causes blue screen in windows.
136 ;**************************************************************************
137 CPUbugIAENG2900 PROC NEAR PUBLIC
140 ; Clear bit 43, disables the sysenter/sysexit in CPUID3
146 mov cx, TOKEN_BTB_2900_SWAPSIF_ENABLE
147 NOSTACK bx, GetNVRAMValueBX
148 cmp ax, TVALUE_ENABLE
152 ;Disable enable_actions in DIAGCTL while setting up GLCP
153 mov ecx, MSR_GLCP + 005fh
158 ;Changing DBGCLKCTL register to GeodeLink
159 mov ecx, MSR_GLCP + 0016h
164 mov ecx, MSR_GLCP + 0016h
169 ;The code below sets up the RedCloud to stall for 4 GeodeLink clocks when CPU is snooped.
170 ;Because setting XSTATE to 0 overrides any other XSTATE action, the code will always
171 ;stall for 4 GeodeLink clocks after a snoop request goes away even if it occured a clock or two
172 ;later than a different snoop; the stall signal will never 'glitch high' for
173 ;only one or two CPU clocks with this code.
175 ;Send mb0 port 3 requests to upper GeodeLink diag bits [63:32]
176 mov ecx, MSR_GLIU0 + 2005h
181 ;set5m watches request ready from mb0 to CPU (snoop)
182 mov ecx, MSR_GLCP + 0045h
187 ;SET4M will be high when state is idle (XSTATE=11)
188 mov ecx, MSR_GLCP + 0044h
193 ;SET5n to watch for processor stalled state
194 mov ecx, MSR_GLCP + 004Dh
199 ;Writing action number 13: XSTATE=0 to occur when CPU is snooped unless we're stalled
200 mov ecx, MSR_GLCP + 0075h
205 ;Writing action number 11: inc XSTATE every GeodeLink clock unless we're idle
206 mov ecx, MSR_GLCP + 0073h
212 ;Writing action number 5: STALL_CPU_PIPE when exitting idle state or not in idle state
213 mov ecx, MSR_GLCP + 006Dh
218 ;Writing DIAGCTL Register to enable the stall action and to let set5m watch the upper GeodeLink diag bits.
219 mov ecx, MSR_GLCP + 005fh
234 /* GLPCI PIO Post Control shouldn't be enabled */
237 msr = rdmsr(GLPCI_SPARE);
238 msr.lo &= ~GLPCI_SPARE_LOWER_PPC_SET;
239 wrmsr(GLPCI_SPARE, msr);
244 /* per AMD, do this always */
248 /* Disable enable_actions in DIAGCTL while setting up GLCP */
249 wrmsr(MSR_GLCP + 0x005f, msr);
251 /* SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */
252 msrnum = MSR_GLCP + 0x042;
253 /* msr.hi = 2d6b8000h */;
258 /* SET3M fires if MBUS changed and VG pri is odd */
259 msrnum = MSR_GLCP + 0x043;
264 /* Put VG request data on lower diag bus */
265 msrnum = MSR_GLIU0 + 0x2005;
270 /* Increment Y state if SET3M if true */
271 msrnum = MSR_GLCP + 0x074;
276 /* Set up MBUS action to PRI=3 read of MBIU */
277 msrnum = MSR_GLCP + 0x020;
282 /* Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI */
283 msrnum = MSR_GLCP + 0x071;
288 /* Writing DIAGCTL */
289 msrnum = MSR_GLCP + 0x005f;
294 /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */
295 /* As per Todd Roberts in PBz1094 and PBz1095 */
296 /* Moved from CPUREG to CPUBUG per Tom Sylla */
297 msrnum = 0x04C000042; /* GLCP SETMCTL Register */;
299 msr.hi |= 8; /* Bit 35 = MCP_IN */
305 /****************************************************************************/
307 /** DisableMemoryReorder*/
310 /** The MC reordered transactions incorrectly and breaks coherency.*/
311 /** Disable reording and take a potential performance hit.*/
312 /** This is safe to do here and not in MC init since there is nothing*/
313 /** to maintain coherency with and the cache is not enabled yet.*/
320 /****************************************************************************/
321 void disablememoryreadorder(void)
324 msr = rdmsr(MC_CF8F_DATA);
326 msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
327 wrmsr(MC_CF8F_DATA, msr);
336 msr = rdmsr(GLCP_CHIP_REVID);
340 printk_err("%s: rev < 0x20! bailing!\n");
343 printk_debug("Doing cpubug fixes for rev 0x%x\n", rev);
349 /* cs 5530 bug; ignore
363 printk_err("unknown rev %x, bailing\n", rev);
368 disablememoryreadorder();
369 printk_debug("Done cpubug fixes \n");