1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
10 #include <cpu/amd/gx2def.h>
11 #include <cpu/x86/msr.h>
12 #include <cpu/x86/cache.h>
20 msr.whatever |= ID_CONFIG_SERIAL_SET;
28 msr = rdmsr(MC_GLD_MSR_PM);
34 /**************************************************************************
38 * Bugtool #465 and #609
40 * There is also fix code in cache and PCI functions. This bug is very is pervasive.
46 **************************************************************************/
53 * forces serialization of all load misses. Setting this bit prevents the
54 * DM pipe from backing up if a read request has to be held up waiting
55 * for PCI writes to complete.
57 msr = rdmsr(CPU_DM_CONFIG0);
58 msr.hi &= ~(7<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
59 msr.hi |= (2<<DM_CONFIG0_UPPER_WSREQ_SHIFT);
60 msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
61 wrmsr(CPU_DM_CONFIG0, msr);
63 /* interlock instruction fetches to WS regions with data accesses.
64 * This prevents an instruction fetch from going out to PCI if the
65 * data side is about to make a request.
67 msr = rdmsr(CPU_IM_CONFIG);
68 msr.lo |= IM_CONFIG_LOWER_QWT_SET;
69 wrmsr(CPU_IM_CONFIG, msr);
71 /* write serialize memory hole to PCI. Need to unWS when something is
72 * shadowed regardless of cachablility.
76 wrmsr( CPU_RCONF_A0_BF, msr);
77 wrmsr( CPU_RCONF_C0_DF, msr);
78 wrmsr( CPU_RCONF_E0_FF, msr);
81 /****************************************************************************
87 * Fix CPUID instructions for < 3.0 CPUs
93 ****************************************************************************/
98 //static char *name = "Geode by NSC";
100 /* we'll do this the stupid way, for now, but that's the string they want. NO ONE KNOWS why you
101 * would do this -- the OS can figure this type of stuff out!
115 /* More CPUID to match AMD better. #792*/
117 msr.hi = 0x0C0C0A13D;
122 /* cpubug 1398: enable MC if we KNOW we have DDR*/
123 /**************************************************************************
127 * ClearQuest #IAENG1398
128 * The MC can not be enabled with SDR memory but can for DDR. Enable for
129 * DDR here if the setup token is "Default"
130 * Add this back to core by default once 2.0 CPUs are not supported.
135 **************************************************************************/
140 msr = rdmsr(MSR_GLCP+0x17);
141 if ((msr.lo & 0xff) <= CPU_REV_2_0) {
142 msr = rdmsr(GLCP_SYS_RSTPLL);
143 if (msr.lo & (1<<RSTPPL_LOWER_SDRMODE_SHIFT))
147 /* no CMOS/NVRAM to check, so enable MC Clock Gating */
148 msr = rdmsr(MC_GLD_MSR_PM);
149 msr.lo |= 3; /* enable MC clock gating.*/
150 wrmsr(MC_GLD_MSR_PM, msr);
153 /***************************************************************************
157 * Clear Quest IAENG00002900, VSS 118.150
159 * BTB issue causes blue screen in windows, but the fix is required
160 * for all operating systems.
166 **************************************************************************/
172 printk(BIOS_DEBUG, "CPU_BUG:%s\n", __func__);
173 /* Clear bit 43, disables the sysenter/sysexit in CPUID3 */
175 msr.hi &= 0xFFFFF7FF;
178 /* change this value to zero if you need to disable this BTB SWAPSiF. */
181 /* Disable enable_actions in DIAGCTL while setting up GLCP */
184 wrmsr(MSR_GLCP + 0x005f, msr);
186 /* Changing DBGCLKCTL register to GeodeLink */
189 wrmsr(MSR_GLCP + 0x0016, msr);
193 wrmsr(MSR_GLCP + 0x0016, msr);
195 /* The code below sets up the CPU to stall for 4 GeodeLink
196 * clocks when CPU is snooped. Because setting XSTATE to 0
197 * overrides any other XSTATE action, the code will always
198 * stall for 4 GeodeLink clocks after a snoop request goes
199 * away even if it occured a clock or two later than a
200 * different snoop; the stall signal will never 'glitch high'
201 * for only one or two CPU clocks with this code.
204 /* Send mb0 port 3 requests to upper GeodeLink diag bits
208 wrmsr(MSR_GLIU0 + 0x2005, msr);
210 /* set5m watches request ready from mb0 to CPU (snoop) */
213 wrmsr(MSR_GLCP + 0x0045, msr);
215 /* SET4M will be high when state is idle (XSTATE=11) */
218 wrmsr(MSR_GLCP + 0x0044, msr);
220 /* SET5n to watch for processor stalled state */
223 wrmsr(MSR_GLCP + 0x004D, msr);
225 /* Writing action number 13: XSTATE=0 to occur when CPU is
226 snooped unless we're stalled */
229 wrmsr(MSR_GLCP + 0x0075, msr);
231 /* Writing action number 11: inc XSTATE every GeodeLink clock
235 wrmsr(MSR_GLCP + 0x0073, msr);
237 /* Writing action number 5: STALL_CPU_PIPE when exitting idle
238 state or not in idle state */
241 wrmsr(MSR_GLCP + 0x006D, msr);
243 /* Writing DIAGCTL Register to enable the stall action and to
244 let set5m watch the upper GeodeLink diag bits. */
247 wrmsr(MSR_GLCP + 0x005f, msr);
253 /* GLPCI PIO Post Control shouldn't be enabled */
256 msr = rdmsr(GLPCI_SPARE);
257 msr.lo &= ~GLPCI_SPARE_LOWER_PPC_SET;
258 wrmsr(GLPCI_SPARE, msr);
263 /* per AMD, do this always */
267 /* Disable enable_actions in DIAGCTL while setting up GLCP */
268 wrmsr(MSR_GLCP + 0x005f, msr);
270 /* SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */
271 msrnum = MSR_GLCP + 0x042;
272 /* msr.hi = 2d6b8000h */;
277 /* SET3M fires if MBUS changed and VG pri is odd */
278 msrnum = MSR_GLCP + 0x043;
283 /* Put VG request data on lower diag bus */
284 msrnum = MSR_GLIU0 + 0x2005;
289 /* Increment Y state if SET3M if true */
290 msrnum = MSR_GLCP + 0x074;
295 /* Set up MBUS action to PRI=3 read of MBIU */
296 msrnum = MSR_GLCP + 0x020;
301 /* Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI */
302 msrnum = MSR_GLCP + 0x071;
307 /* Writing DIAGCTL */
308 msrnum = MSR_GLCP + 0x005f;
313 /* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled */
314 /* As per Todd Roberts in PBz1094 and PBz1095 */
315 /* Moved from CPUREG to CPUBUG per Tom Sylla */
316 msrnum = 0x04C000042; /* GLCP SETMCTL Register */;
318 msr.hi |= 8; /* Bit 35 = MCP_IN */
324 /****************************************************************************/
326 /** DisableMemoryReorder*/
329 /** The MC reordered transactions incorrectly and breaks coherency.*/
330 /** Disable reording and take a potential performance hit.*/
331 /** This is safe to do here and not in MC init since there is nothing*/
332 /** to maintain coherency with and the cache is not enabled yet.*/
339 /****************************************************************************/
340 void disablememoryreadorder(void)
343 msr = rdmsr(MC_CF8F_DATA);
345 msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
346 wrmsr(MC_CF8F_DATA, msr);
355 msr = rdmsr(GLCP_CHIP_REVID);
359 printk(BIOS_ERR, "%s: rev < 0x20! bailing!\n", __func__);
362 printk(BIOS_DEBUG, "Doing cpubug fixes for rev 0x%x\n", rev);
368 /* cs 5530 bug; ignore
382 printk(BIOS_ERR, "unknown rev %x, bailing\n", rev);
387 disablememoryreadorder();
388 printk(BIOS_DEBUG, "Done cpubug fixes \n");