src/cpu/amd/model_fxx/powernow_acpi.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #include <console/console.h>
  22 #include <stdint.h>
  23 #include <cpu/x86/msr.h>
  24 #include <arch/acpigen.h>
  25 #include <cpu/amd/model_fxx_powernow.h>
  26 #include <device/pci.h>
  27 #include <device/pci_ids.h>
  28 #include <cpu/x86/msr.h>
  29 #include <cpu/amd/mtrr.h>
  30 #include <cpu/amd/amdk8_sysconf.h>
  31 #include <arch/cpu.h>
  32
  33 static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid,
  34                                 u8 *pstate_fid, u32 *pstate_power, int coreID,
  35                                 u32 pcontrol_blk, u8 plen, u8 onlyBSP)
  36 {
  37         int lenp, lenpr, i;
  38
  39         if ((onlyBSP) && (coreID != 0)) {
  40             plen = 0;
  41             pcontrol_blk = 0;
  42         }
  43
  44         lenpr = acpigen_write_processor(coreID, pcontrol_blk, plen);
  45         lenpr += acpigen_write_empty_PCT();
  46         lenpr += acpigen_write_name("_PSS");
  47
  48         /* add later to total sum */
  49         lenp = acpigen_write_package(pstate_num);
  50
  51         for (i = 0;i < pstate_num;i++) {
  52                 u32 control, status;
  53
  54                 control =
  55                             (0x3 << 30) | /* IRT */
  56                             (0x2 << 28) | /* RVO */
  57                             (0x1 << 27) | /* ExtType */
  58                             (0x2 << 20) | /* PLL_LOCK_TIME */
  59                             (0x0 << 18) | /* MVS */
  60                             (0x5 << 11) | /* VST */
  61                             (pstate_vid[i] << 6) |
  62                             pstate_fid[i];
  63                 status =
  64                             (pstate_vid[i] << 6) |
  65                             pstate_fid[i];
  66
  67                 lenp += acpigen_write_PSS_package(pstate_feq[i],
  68                                                 pstate_power[i],
  69                                                 0x64,
  70                                                 0x7,
  71                                                 control,
  72                                                 status);
  73         }
  74         /* update the package  size */
  75         acpigen_patch_len(lenp - 1);
  76
  77         lenpr += lenp;
  78         lenpr += acpigen_write_PPC(pstate_num);
  79         /* patch the whole Processor token length */
  80         acpigen_patch_len(lenpr - 2);
  81         return lenpr;
  82 }
  83 /*
  84 * Details about this algorithm , refert to BDKG 10.5.1
  85 * Two parts are included, the another is the DSDT reconstruction process
  86 */
  87
  88 static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
  89 {
  90         int len;
  91         u8 processor_brand[49];
  92         u32 *v;
  93         struct cpuid_result cpuid1;
  94
  95         struct power_limit_encoding {
  96                 u8 socket_type;
  97                 u8 cmp_cap;
  98                 u8 pwr_lmt;
  99                 u32 power_limit;
 100         };
 101         u8 Max_fid, Max_vid, Start_fid, Start_vid, Min_fid, Min_vid;
 102         u16 Max_feq;
 103         u8 Pstate_fid[10];
 104         u16 Pstate_feq[10];
 105         u8 Pstate_vid[10];
 106         u32 Pstate_power[10];
 107         u32 Pstate_volt[10];
 108         u8 PstateStep, PstateStep_coef;
 109         u8 IntPstateSup;
 110         u8 Pstate_num;
 111         u16 Cur_feq;
 112         u8 Cur_fid;
 113         u8 cmp_cap, pwr_lmt;
 114         u32 power_limit = 0;
 115         u8 index;
 116         msr_t msr;
 117         u32 fid_multiplier;
 118         static struct power_limit_encoding TDP[20] = {
 119                 {0x11, 0x0, 0x8, 62},
 120                 {0x11, 0x1, 0x8, 89},
 121                 {0x11, 0x1, 0xa, 103},
 122                 {0x11, 0x1, 0xc, 125},
 123                 {0x11, 0x0, 0x2, 15},
 124                 {0x11, 0x0, 0x4, 35},
 125                 {0x11, 0x1, 0x2, 35},
 126                 {0x11, 0x0, 0x5, 45},
 127                 {0x11, 0x1, 0x7, 76},
 128                 {0x11, 0x1, 0x6, 65},
 129                 {0x11, 0x1, 0x8, 89},
 130                 {0x11, 0x0, 0x1, 8},
 131                 {0x11, 0x1, 0x1, 22},
 132                 {0x12, 0x0, 0x6, 25},
 133                 {0x12, 0x0, 0x1, 8},
 134                 {0x12, 0x0, 0x2, 9},
 135                 {0x12, 0x0, 0x4, 15},
 136                 {0x12, 0x0, 0xc, 35},
 137                 {0x12, 0x1, 0xc, 35},
 138                 {0x12, 0x1, 0x4, 20}
 139         };
 140
 141         /* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */
 142         cpuid1 = cpuid(0x80000002);
 143         v = (u32 *) processor_brand;
 144         v[0] = cpuid1.eax;
 145         v[1] = cpuid1.ebx;
 146         v[2] = cpuid1.ecx;
 147         v[3] = cpuid1.edx;
 148         cpuid1 = cpuid(0x80000003);
 149         v[4] = cpuid1.eax;
 150         v[5] = cpuid1.ebx;
 151         v[6] = cpuid1.ecx;
 152         v[7] = cpuid1.edx;
 153         cpuid1 = cpuid(0x80000004);
 154         v[8] = cpuid1.eax;
 155         v[9] = cpuid1.ebx;
 156         v[10] = cpuid1.ecx;
 157         v[11] = cpuid1.edx;
 158         processor_brand[48] = 0;
 159         printk_info("processor_brand=%s\n", processor_brand);
 160
 161         /*
 162          * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
 163          * socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1
 164          * cmp_cap : 0x0 SingleCore ; 0x1 DualCore
 165          */
 166         printk_info("Pstates Algorithm ...\n");
 167         cmp_cap =
 168             (pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) &
 169              0x3000) >> 12;
 170         cpuid1 = cpuid(0x80000001);
 171         pwr_lmt = ((cpuid1.ebx & 0x1C0) >> 5) | ((cpuid1.ebx & 0x4000) >> 14);
 172         for (index = 0; index <= sizeof(TDP) / sizeof(TDP[0]); index++)
 173                 if (TDP[index].socket_type == CONFIG_CPU_SOCKET_TYPE &&
 174                     TDP[index].cmp_cap == cmp_cap &&
 175                     TDP[index].pwr_lmt == pwr_lmt) {
 176                         power_limit = TDP[index].power_limit;
 177                 }
 178
 179         Pstate_num = 0;
 180
 181         /* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
 182         cpuid1 = cpuid(0x80000007);
 183         if ((cpuid1.edx & 0x6) != 0x6) {
 184                 printk_info("No valid set of P-states\n");
 185                 goto write_pstates;
 186         }
 187
 188         msr = rdmsr(0xc0010042);
 189         Max_fid = (msr.lo & 0x3F0000) >> 16;
 190         Start_fid = (msr.lo & 0x3F00) >> 8;
 191         Max_vid = (msr.hi & 0x3F0000) >> 16;
 192         Start_vid = (msr.hi & 0x3F00) >> 8;
 193         PstateStep = (msr.hi & 0x1000000) >> 24;
 194         IntPstateSup = (msr.hi & 0x20000000) >> 29;
 195
 196         /*
 197          * The P1...P[Min+1] VID need PstateStep to calculate
 198          * P[N] = P[N-1]VID + 2^PstateStep
 199          * PstateStep_coef = 2^PstateStep
 200          */
 201         if (PstateStep == 0)
 202                 PstateStep_coef = 1;
 203         else
 204                 PstateStep_coef = 2;
 205
 206         if (IntPstateSup == 0) {
 207                 printk_info("No intermediate P-states are supported\n");
 208                 goto write_pstates;
 209         }
 210
 211         /* Get the multipier of the fid frequency */
 212         /*
 213          * Fid multiplier is always 100 revF and revG.
 214          */
 215         fid_multiplier = 100;
 216
 217         /*
 218          * Formula1:    CPUFreq = FID * fid_multiplier + 800
 219          * Formula2:       CPUVolt = 1550 - VID * 25 (mv)
 220          * Formula3:       Power = (PwrLmt * P[N]Frequency*(P[N]Voltage^2))/(P[0]Frequency * P[0]Voltage^2))
 221          */
 222
 223         /* Construct P0(P[Max]) state */
 224         Max_feq = Max_fid * fid_multiplier + 800;
 225         if (Max_fid == 0x2A && Max_vid != 0x0) {
 226                 Min_fid = 0x2;
 227                 Pstate_fid[0] = Start_fid + 0xA;        /* Start Frequency + 1GHz */
 228                 Pstate_feq[0] = Pstate_fid[0] * fid_multiplier + 800;
 229                 Min_vid = Start_vid;
 230                 Pstate_vid[0] = Max_vid + 0x2;  /* Maximum Voltage - 50mV */
 231                 Pstate_volt[0] = 1550 - Pstate_vid[0] * 25;
 232                 Pstate_power[0] = power_limit * 1000;   /* mw */
 233                 Pstate_num++;
 234         } else {
 235                 Min_fid = Start_fid;
 236                 Pstate_fid[0] = Max_fid;
 237                 Pstate_feq[0] = Max_feq;
 238                 Min_vid = Start_vid;
 239                 Pstate_vid[0] = Max_vid + 0x2;
 240                 Pstate_volt[0] = 1550 - Pstate_vid[0] * 25;
 241                 Pstate_power[0] = power_limit * 1000;   /* mw */
 242                 Pstate_num++;
 243         }
 244
 245         Cur_feq = Max_feq;
 246         Cur_fid = Max_fid;
 247         /* Construct P1 state */
 248         if (((Max_fid & 0x1) != 0) && ((Max_fid - 0x1) >= (Min_fid + 0x8))) {   /* odd value */
 249                 Pstate_fid[1] = Max_fid - 0x1;
 250                 Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
 251                 Cur_fid = Pstate_fid[1];
 252                 Cur_feq = Pstate_feq[1];
 253                 if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) {        /* odd value */
 254                         Pstate_vid[1] = Pstate_vid[0] + 0x1;
 255                         Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
 256                         Pstate_power[1] =
 257                             (unsigned long long)Pstate_power[0] *
 258                             Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
 259                             (Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
 260                 }
 261                 if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) {        /* even value */
 262                         Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
 263                         Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
 264                         Pstate_power[1] =
 265                             (unsigned long long)Pstate_power[0] *
 266                             Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
 267                             (Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
 268                 }
 269                 Pstate_num++;
 270         }
 271
 272         if (((Max_fid & 0x1) == 0) && ((Max_fid - 0x2) >= (Min_fid + 0x8))) {   /* even value */
 273                 Pstate_fid[1] = Max_fid - 0x2;
 274                 Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
 275                 Cur_fid = Pstate_fid[1];
 276                 Cur_feq = Pstate_feq[1];
 277                 if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) {        /* odd value */
 278                         Pstate_vid[1] = Pstate_vid[0] + 0x1;
 279                         Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
 280                         Pstate_power[1] =
 281                             (unsigned long long)Pstate_power[0] *
 282                             Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
 283                             (Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
 284                 }
 285                 if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) {        /* even value */
 286                         Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
 287                         Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
 288                         Pstate_power[1] =
 289                             (unsigned long long)Pstate_power[0] *
 290                             Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
 291                             (Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
 292                 }
 293
 294                 Pstate_num++;
 295         }
 296
 297         /* Construct P2...P[Min-1] state */
 298         Cur_fid = Cur_fid - 0x2;
 299         Cur_feq = Cur_fid * fid_multiplier + 800;
 300         while (Cur_feq >= ((Min_fid * fid_multiplier) + 800) * 2) {
 301                 Pstate_fid[Pstate_num] = Cur_fid;
 302                 Pstate_feq[Pstate_num] =
 303                     Pstate_fid[Pstate_num] * fid_multiplier + 800;
 304                 Cur_fid = Cur_fid - 0x2;
 305                 Cur_feq = Cur_fid * fid_multiplier + 800;
 306                 if (Pstate_vid[Pstate_num - 1] >= Min_vid) {
 307                         Pstate_vid[Pstate_num] = Pstate_vid[Pstate_num - 1];
 308                         Pstate_volt[Pstate_num] = Pstate_volt[Pstate_num - 1];
 309                         Pstate_power[Pstate_num] = Pstate_power[Pstate_num - 1];
 310                 } else {
 311                         Pstate_vid[Pstate_num] =
 312                             Pstate_vid[Pstate_num - 1] + PstateStep_coef;
 313                         Pstate_volt[Pstate_num] =
 314                             1550 - Pstate_vid[Pstate_num] * 25;
 315                         Pstate_power[Pstate_num] =
 316                             (unsigned long long)Pstate_power[0] *
 317                             Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
 318                             Pstate_volt[Pstate_num] / (Pstate_feq[0] *
 319                                                        Pstate_volt[0] *
 320                                                        Pstate_volt[0]);
 321                 }
 322                 Pstate_num++;
 323         }
 324
 325         /* Constuct P[Min] State */
 326         if (Max_fid == 0x2A && Max_vid != 0x0) {
 327                 Pstate_fid[Pstate_num] = 0x2;
 328                 Pstate_feq[Pstate_num] =
 329                     Pstate_fid[Pstate_num] * fid_multiplier + 800;
 330                 Pstate_vid[Pstate_num] = Min_vid;
 331                 Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
 332                 Pstate_power[Pstate_num] =
 333                     (unsigned long long)Pstate_power[0] *
 334                     Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
 335                     Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] *
 336                                                Pstate_volt[0]);
 337                 Pstate_num++;
 338         } else {
 339                 Pstate_fid[Pstate_num] = Start_fid;
 340                 Pstate_feq[Pstate_num] =
 341                     Pstate_fid[Pstate_num] * fid_multiplier + 800;
 342                 Pstate_vid[Pstate_num] = Min_vid;
 343                 Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
 344                 Pstate_power[Pstate_num] =
 345                     (unsigned long long)Pstate_power[0] *
 346                     Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
 347                     Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] *
 348                                                Pstate_volt[0]);
 349                 Pstate_num++;
 350         }
 351
 352         /* Print Pstate freq,vid,volt,power */
 353
 354         for (index = 0; index < Pstate_num; index++) {
 355                 printk_info("Pstate_freq[%d] = %dMHz\t", index,
 356                             Pstate_feq[index]);
 357                 printk_info("Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
 358                 printk_info("Pstate_volt[%d] = %dmv\t", index,
 359                             Pstate_volt[index]);
 360                 printk_info("Pstate_power[%d] = %dmw\n", index,
 361                             Pstate_power[index]);
 362         }
 363
 364
 365 write_pstates:
 366
 367         len = 0;
 368
 369         for (index = 0; index < (cmp_cap + 1); index++) {
 370                 len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
 371                                 Pstate_fid, Pstate_power, index,
 372                                 pcontrol_blk, plen, onlyBSP);
 373         }
 374
 375         return len;
 376 }
 377
 378 int amd_model_fxx_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 379 {
 380         int lens;
 381         char pscope[] = "\\_PR";
 382
 383         lens = acpigen_write_scope(pscope);
 384         lens += pstates_algorithm(pcontrol_blk, plen, onlyBSP);
 385         //minus opcode
 386         acpigen_patch_len(lens - 1);
 387         return lens;
 388 }