1 /* Needed so the AMD K8 runs correctly. */
2 /* this should be done by Eric
3 * 2004.11 yhlu add d0 e0 support
4 * 2004.12 yhlu add dual core support
5 * 2005.02 yhlu add e0 memory hole support
8 * 2005.08 yhlu add microcode support
10 #include <console/console.h>
11 #include <cpu/x86/msr.h>
12 #include <cpu/amd/mtrr.h>
13 #include <device/device.h>
14 #include <device/pci.h>
16 #include <cpu/x86/msr.h>
17 #include <cpu/x86/pae.h>
18 #include <pc80/mc146818rtc.h>
19 #include <cpu/x86/lapic.h>
21 #include "../../../northbridge/amd/amdk8/amdk8.h"
23 #include <cpu/amd/model_fxx_rev.h>
25 #include <cpu/x86/cache.h>
26 #include <cpu/x86/mtrr.h>
27 #include <cpu/x86/mem.h>
29 #include <cpu/amd/dualcore.h>
31 #include <cpu/amd/model_fxx_msr.h>
33 int is_e0_later_in_bsp(int nodeid)
38 if(nodeid==0) { // we don't need to do that for node 0 in core0/node0
39 return !is_cpu_pre_e0();
41 // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
43 dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid,2));
45 val_old = pci_read_config32(dev, 0x80);
48 pci_write_config32(dev, 0x80, val);
49 val = pci_read_config32(dev, 0x80);
50 e0_later = !!(val & (1<<3));
51 if(e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
52 pci_write_config32(dev, 0x80, val_old); // restore it
58 #define MCI_STATUS 0x401
60 static inline msr_t rdmsr_amd(unsigned index)
63 __asm__ __volatile__ (
65 : "=a" (result.lo), "=d" (result.hi)
66 : "c" (index), "D" (0x9c5a203a)
71 static inline void wrmsr_amd(unsigned index, msr_t msr)
73 __asm__ __volatile__ (
76 : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a)
82 #define ZERO_CHUNK_KB 0x800UL /* 2M */
83 #define TOLM_KB 0x400000UL
90 struct mtrr mtrrs[MTRR_COUNT];
91 msr_t top_mem, top_mem2;
95 static void save_mtrr_state(struct mtrr_state *state)
98 for(i = 0; i < MTRR_COUNT; i++) {
99 state->mtrrs[i].base = rdmsr(MTRRphysBase_MSR(i));
100 state->mtrrs[i].mask = rdmsr(MTRRphysMask_MSR(i));
102 state->top_mem = rdmsr(TOP_MEM);
103 state->top_mem2 = rdmsr(TOP_MEM2);
104 state->def_type = rdmsr(MTRRdefType_MSR);
107 static void restore_mtrr_state(struct mtrr_state *state)
112 for(i = 0; i < MTRR_COUNT; i++) {
113 wrmsr(MTRRphysBase_MSR(i), state->mtrrs[i].base);
114 wrmsr(MTRRphysMask_MSR(i), state->mtrrs[i].mask);
116 wrmsr(TOP_MEM, state->top_mem);
117 wrmsr(TOP_MEM2, state->top_mem2);
118 wrmsr(MTRRdefType_MSR, state->def_type);
125 static void print_mtrr_state(struct mtrr_state *state)
128 for(i = 0; i < MTRR_COUNT; i++) {
129 printk_debug("var mtrr %d: %08x%08x mask: %08x%08x\n",
131 state->mtrrs[i].base.hi, state->mtrrs[i].base.lo,
132 state->mtrrs[i].mask.hi, state->mtrrs[i].mask.lo);
134 printk_debug("top_mem: %08x%08x\n",
135 state->top_mem.hi, state->top_mem.lo);
136 printk_debug("top_mem2: %08x%08x\n",
137 state->top_mem2.hi, state->top_mem2.lo);
138 printk_debug("def_type: %08x%08x\n",
139 state->def_type.hi, state->def_type.lo);
143 static void set_init_ecc_mtrrs(void)
149 /* First clear all of the msrs to be safe */
150 for(i = 0; i < MTRR_COUNT; i++) {
152 zero.lo = zero.hi = 0;
153 wrmsr(MTRRphysBase_MSR(i), zero);
154 wrmsr(MTRRphysMask_MSR(i), zero);
157 /* Write back cache the first 1MB */
159 msr.lo = 0x00000000 | MTRR_TYPE_WRBACK;
160 wrmsr(MTRRphysBase_MSR(0), msr);
162 msr.lo = ~((CONFIG_LB_MEM_TOPK << 10) - 1) | 0x800;
163 wrmsr(MTRRphysMask_MSR(0), msr);
165 /* Set the default type to write combining */
167 msr.lo = 0xc00 | MTRR_TYPE_WRCOMB;
168 wrmsr(MTRRdefType_MSR, msr);
170 /* Set TOP_MEM to 4G */
178 static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_state)
180 unsigned long limitk;
184 /* Report every 64M */
185 if ((basek % (64*1024)) == 0) {
187 /* Restore the normal state */
189 restore_mtrr_state(mtrr_state);
192 /* Print a status message */
193 printk_debug("%c", (basek >= TOLM_KB)?'+':'-');
195 /* Return to the initialization state */
196 set_init_ecc_mtrrs();
201 limitk = (basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1);
203 /* couldn't happen, memory must on 2M boundary */
208 size = (limitk - basek) << 10;
209 addr = map_2M_page(basek >> 11);
210 if (addr == MAPPING_ERROR) {
211 printk_err("Cannot map page: %x\n", basek >> 11);
215 /* clear memory 2M (limitk - basek) */
216 addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
217 clear_memory(addr, size);
220 static void init_ecc_memory(unsigned node_id)
222 unsigned long startk, begink, endk;
223 unsigned long hole_startk = 0;
225 struct mtrr_state mtrr_state;
227 device_t f1_dev, f2_dev, f3_dev;
228 int enable_scrubbing;
231 f1_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 1));
233 die("Cannot find cpu function 1\n");
235 f2_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 2));
237 die("Cannot find cpu function 2\n");
239 f3_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 3));
241 die("Cannot find cpu function 3\n");
244 /* See if we scrubbing should be enabled */
245 enable_scrubbing = 1;
246 get_option(&enable_scrubbing, "hw_scrubber");
248 /* Enable cache scrubbing at the lowest possible rate */
249 if (enable_scrubbing) {
250 pci_write_config32(f3_dev, SCRUB_CONTROL,
251 (SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_NONE << 0));
253 pci_write_config32(f3_dev, SCRUB_CONTROL,
254 (SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0));
255 printk_debug("Scrubbing Disabled\n");
259 /* If ecc support is not enabled don't touch memory */
260 dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
261 if (!(dcl & DCL_DimmEccEn)) {
262 printk_debug("ECC Disabled\n");
266 startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
267 endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
269 #if K8_HW_MEM_HOLE_SIZEK != 0
270 if (!is_cpu_pre_e0())
274 val = pci_read_config32(f1_dev, 0xf0);
276 hole_startk = ((val & (0xff<<24)) >> 10);
282 /* Don't start too early */
284 if (begink < CONFIG_LB_MEM_TOPK) {
285 begink = CONFIG_LB_MEM_TOPK;
288 printk_debug("Clearing memory %uK - %uK: ", begink, endk);
290 /* Save the normal state */
291 save_mtrr_state(&mtrr_state);
293 /* Switch to the init ecc state */
294 set_init_ecc_mtrrs();
297 /* Walk through 2M chunks and zero them */
298 #if K8_HW_MEM_HOLE_SIZEK != 0
299 /* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */
300 if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) {
301 for(basek = begink; basek < hole_startk;
302 basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
304 clear_2M_ram(basek, &mtrr_state);
306 for(basek = 4*1024*1024; basek < endk;
307 basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
309 clear_2M_ram(basek, &mtrr_state);
314 for(basek = begink; basek < endk;
315 basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
317 clear_2M_ram(basek, &mtrr_state);
321 /* Restore the normal state */
323 restore_mtrr_state(&mtrr_state);
326 /* Set the scrub base address registers */
327 pci_write_config32(f3_dev, SCRUB_ADDR_LOW, startk << 10);
328 pci_write_config32(f3_dev, SCRUB_ADDR_HIGH, startk >> 22);
330 /* Enable the scrubber? */
331 if (enable_scrubbing) {
332 /* Enable scrubbing at the lowest possible rate */
333 pci_write_config32(f3_dev, SCRUB_CONTROL,
334 (SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_84ms << 0));
337 printk_debug(" done\n");
340 static inline void k8_errata(void)
343 if (is_cpu_pre_c0()) {
345 msr = rdmsr(HWCR_MSR);
347 wrmsr(HWCR_MSR, msr);
350 msr = rdmsr_amd(BU_CFG_MSR);
351 msr.hi |= (1 << (45 - 32));
352 wrmsr_amd(BU_CFG_MSR, msr);
355 msr = rdmsr_amd(DC_CFG_MSR);
357 wrmsr_amd(DC_CFG_MSR, msr);
360 /* I can't touch this msr on early buggy cpus */
361 if (!is_cpu_pre_b3()) {
364 msr = rdmsr(NB_CFG_MSR);
367 if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
368 /* D0 later don't need it */
369 /* Erratum 86 Disable data masking on C0 and
370 * later processor revs.
371 * FIXME this is only needed if ECC is enabled.
373 msr.hi |= 1 << (36 - 32);
375 wrmsr(NB_CFG_MSR, msr);
379 if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
380 msr = rdmsr_amd(DC_CFG_MSR);
382 wrmsr_amd(DC_CFG_MSR, msr);
386 if (is_cpu_pre_d0()) {
387 msr = rdmsr_amd(IC_CFG_MSR);
389 wrmsr_amd(IC_CFG_MSR, msr);
392 /* Erratum 91 prefetch miss is handled in the kernel */
394 /* Erratum 106 ... */
395 msr = rdmsr_amd(LS_CFG_MSR);
397 wrmsr_amd(LS_CFG_MSR, msr);
399 /* Erratum 107 ... */
400 msr = rdmsr_amd(BU_CFG_MSR);
401 msr.hi |= 1 << (43 - 32);
402 wrmsr_amd(BU_CFG_MSR, msr);
406 msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES);
408 wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr);
411 if (!is_cpu_pre_e0())
413 /* Erratum 110 ... */
414 msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
416 wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
420 msr = rdmsr(HWCR_MSR);
422 wrmsr(HWCR_MSR, msr);
427 extern void model_fxx_update_microcode(unsigned cpu_deviceid);
429 void model_fxx_init(device_t dev)
433 struct node_core_id id;
434 #if CONFIG_LOGICAL_CPUS == 1
438 /* Turn on caching if we haven't already */
443 /* Update the microcode */
444 model_fxx_update_microcode(dev->device);
448 /* zero the machine check error status registers */
452 wrmsr(MCI_STATUS + (i*4),msr);
459 /* Enable the local cpu apics */
462 #if CONFIG_LOGICAL_CPUS == 1
463 siblings = cpuid_ecx(0x80000008) & 0xff;
466 msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
468 wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
470 msr = rdmsr_amd(LOGICAL_CPUS_NUM_MSR);
471 msr.lo = (siblings+1)<<16;
472 wrmsr_amd(LOGICAL_CPUS_NUM_MSR, msr);
474 msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
475 msr.hi |= 1<<(33-32);
476 wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
481 id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set
483 /* Is this a bad location? In particular can another node prefecth
484 * data from this node before we have initialized it?
486 if (id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core 0
488 #if CONFIG_LOGICAL_CPUS==1
489 /* Start up my cpu siblings */
490 // if(id.coreid==0) amd_sibling_init(dev); // Don't need core1 is already be put in the CPU BUS in bus_cpu_scan
495 static struct device_operations cpu_dev_ops = {
496 .init = model_fxx_init,
498 static struct cpu_device_id cpu_table[] = {
499 { X86_VENDOR_AMD, 0xf50 }, /* B3 */
500 { X86_VENDOR_AMD, 0xf51 }, /* SH7-B3 */
501 { X86_VENDOR_AMD, 0xf58 }, /* SH7-C0 */
502 { X86_VENDOR_AMD, 0xf48 },
504 { X86_VENDOR_AMD, 0xf5A }, /* SH7-CG */
505 { X86_VENDOR_AMD, 0xf4A },
506 { X86_VENDOR_AMD, 0xf7A },
507 { X86_VENDOR_AMD, 0xfc0 }, /* DH7-CG */
508 { X86_VENDOR_AMD, 0xfe0 },
509 { X86_VENDOR_AMD, 0xff0 },
510 { X86_VENDOR_AMD, 0xf82 }, /* CH7-CG */
511 { X86_VENDOR_AMD, 0xfb2 },
513 { X86_VENDOR_AMD, 0x10f50 }, /* SH7-D0 */
514 { X86_VENDOR_AMD, 0x10f40 },
515 { X86_VENDOR_AMD, 0x10f70 },
516 { X86_VENDOR_AMD, 0x10fc0 }, /* DH7-D0 */
517 { X86_VENDOR_AMD, 0x10ff0 },
518 { X86_VENDOR_AMD, 0x10f80 }, /* CH7-D0 */
519 { X86_VENDOR_AMD, 0x10fb0 },
521 { X86_VENDOR_AMD, 0x20f50 }, /* SH8-E0*/
522 { X86_VENDOR_AMD, 0x20f40 },
523 { X86_VENDOR_AMD, 0x20f70 },
524 { X86_VENDOR_AMD, 0x20fc0 }, /* DH8-E0 */ /* DH-E3 */
525 { X86_VENDOR_AMD, 0x20ff0 },
526 { X86_VENDOR_AMD, 0x20f10 }, /* JH8-E1 */
527 { X86_VENDOR_AMD, 0x20f30 },
528 { X86_VENDOR_AMD, 0x20f51 }, /* SH-E4 */
529 { X86_VENDOR_AMD, 0x20f71 },
530 { X86_VENDOR_AMD, 0x20f42 }, /* SH-E5 */
531 { X86_VENDOR_AMD, 0x20ff2 }, /* DH-E6 */
532 { X86_VENDOR_AMD, 0x20fc2 },
533 { X86_VENDOR_AMD, 0x20f12 }, /* JH-E6 */
534 { X86_VENDOR_AMD, 0x20f32 },
538 static struct cpu_driver model_fxx __cpu_driver = {
540 .id_table = cpu_table,