src/cpu/amd/model_10xxx/update_microcode.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20
  21 #ifndef __ROMCC__
  22 #include <console/console.h>
  23 #include <device/device.h>
  24 #include <device/pci.h>
  25 #include <string.h>
  26
  27 #include <cpu/amd/microcode.h>
  28 #endif
  29
  30 static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
  31
  32 #ifdef __ROMCC__
  33
  34 /* From the Revision Guide :
  35  * Equivalent Processor Table for AMD Family 10h Processors
  36  *
  37  * Installed Processor   Equivalent Processor   Patch Level
  38  * Revision ID           Revision ID
  39  * 00100F00h             1000h                  01000020h
  40  * 00100F01h             1000h                  01000020h
  41  * 00100F02h             1000h                  01000020h
  42  * 00100F20h             1020h                  01000084h
  43  * 00100F21h             1020h                  01000084h
  44  * 00100F2Ah             1020h                  01000084h
  45  * 00100F22h             1022h                  01000083h
  46  * 00100F23h             1022h                  01000083h
  47  */
  48
  49 #include AMD_UCODE_PATCH_FILE
  50
  51 #endif
  52         /*  Dummy terminator  */
  53         0x0, 0x0, 0x0, 0x0,
  54         0x0, 0x0, 0x0, 0x0,
  55         0x0, 0x0, 0x0, 0x0,
  56         0x0, 0x0, 0x0, 0x0,
  57 };
  58
  59 static u32 get_equivalent_processor_rev_id(u32 orig_id) {
  60         static unsigned id_mapping_table[] = {
  61                 0x100f00, 0x1000,
  62                 0x100f01, 0x1000,
  63                 0x100f02, 0x1000,
  64                 0x100f20, 0x1020,
  65                 0x100f21, 0x1020,
  66                 0x100f2A, 0x1020,
  67                 0x100f22, 0x1022,
  68                 0x100f23, 0x1022,
  69         };
  70
  71         u32 new_id;
  72         int i;
  73
  74         new_id = 0;
  75
  76         for (i = 0; i < sizeof(id_mapping_table); i += 2 ) {
  77                 if(id_mapping_table[i]==orig_id) {
  78                         new_id = id_mapping_table[i + 1];
  79                         break;
  80                 }
  81         }
  82
  83         return new_id;
  84
  85 }
  86
  87 void update_microcode(u32 cpu_deviceid)
  88 {
  89         u32 equivalent_processor_rev_id;
  90
  91         /* Update the microcode */
  92         equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid );
  93         if (equivalent_processor_rev_id != 0) {
  94                 amd_update_microcode((void *) microcode_updates, equivalent_processor_rev_id);
  95         } else {
  96                 printk_debug("microcode: rev id not found. Skipping microcode patch!\n");
  97         }
  98
  99 }