src/cpu/amd/model_10xxx/update_microcode.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20
  21 #ifndef __ROMCC__
  22 #include <console/console.h>
  23 #include <device/device.h>
  24 #include <device/pci.h>
  25 #include <string.h>
  26
  27 #include <cpu/amd/microcode.h>
  28 #endif
  29
  30 static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
  31
  32 #ifdef __ROMCC__
  33
  34         // Barcelona rev Ax
  35 //              #include "mc_patch_01000020.h"
  36
  37         // Barcelona rev B0, B1, BA
  38 //              #include "mc_patch_01000066.h"
  39
  40         // Barcelona rev B2, B3
  41                 #include "mc_patch_01000065.h"
  42
  43 #endif
  44         /*  Dummy terminator  */
  45         0x0, 0x0, 0x0, 0x0,
  46         0x0, 0x0, 0x0, 0x0,
  47         0x0, 0x0, 0x0, 0x0,
  48         0x0, 0x0, 0x0, 0x0,
  49 };
  50
  51 static u32 get_equivalent_processor_rev_id(u32 orig_id) {
  52         static unsigned id_mapping_table[] = {
  53                 0x100f00, 0x1000,
  54                 0x100f01, 0x1000,
  55                 0x100f02, 0x1000,
  56                 0x100f20, 0x1020,
  57                 0x100f21, 0x1020,
  58                 0x100f2A, 0x1020,
  59                 0x100f22, 0x1022,
  60                 0x100f23, 0x1022,
  61         };
  62
  63         u32 new_id;
  64         int i;
  65
  66         new_id = 0;
  67
  68         for (i = 0; i < sizeof(id_mapping_table); i += 2 ) {
  69                 if(id_mapping_table[i]==orig_id) {
  70                         new_id = id_mapping_table[i + 1];
  71                         break;
  72                 }
  73         }
  74
  75         return new_id;
  76
  77 }
  78
  79 void update_microcode(u32 cpu_deviceid)
  80 {
  81         u32 equivalent_processor_rev_id;
  82
  83         /* Update the microcode */
  84         equivalent_processor_rev_id = get_equivalent_processor_rev_id(cpu_deviceid );
  85         if (equivalent_processor_rev_id != 0) {
  86                 amd_update_microcode((void *) microcode_updates, equivalent_processor_rev_id);
  87         } else {
  88                 printk_debug("microcode: rev id not found. Skipping microcode patch!\n");
  89         }
  90
  91 }