2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <cpu/x86/msr.h>
22 #include <cpu/amd/mtrr.h>
23 #include <device/device.h>
24 #include <device/pci.h>
26 #include <cpu/x86/msr.h>
27 #include <cpu/x86/pae.h>
28 #include <pc80/mc146818rtc.h>
29 #include <cpu/x86/lapic.h>
31 #include "../../../northbridge/amd/amdfam10/amdfam10.h"
33 #include <cpu/amd/model_10xxx_rev.h>
35 #include <cpu/x86/cache.h>
36 #include <cpu/x86/mtrr.h>
37 #include <cpu/x86/mem.h>
38 #include <cpu/amd/quadcore.h>
39 #include <cpu/amd/model_10xxx_msr.h>
41 extern device_t get_node_pci(u32 nodeid, u32 fn);
45 #define MCI_STATUS 0x401
48 static inline msr_t rdmsr_amd(u32 index)
51 __asm__ __volatile__ (
53 : "=a" (result.lo), "=d" (result.hi)
54 : "c" (index), "D" (0x9c5a203a)
60 static inline void wrmsr_amd(u32 index, msr_t msr)
62 __asm__ __volatile__ (
65 : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a)
70 void model_10xxx_init(device_t dev)
74 struct node_core_id id;
75 #if CONFIG_LOGICAL_CPUS == 1
79 id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
80 printk_debug("nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
82 /* Turn on caching if we haven't already */
89 /* zero the machine check error status registers */
92 for(i=0; i < 5; i++) {
93 wrmsr(MCI_STATUS + (i * 4),msr);
99 /* Enable the local cpu apics */
102 /* FIXME: Update CPUID name strings here */
104 #if CONFIG_LOGICAL_CPUS == 1
105 siblings = cpuid_ecx(0x80000008) & 0xff;
108 msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
110 wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
112 msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
113 msr.hi |= 1 << (33-32);
114 wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
116 printk_debug("siblings = %02d, ", siblings);
119 /* DisableCf8ExtCfg */
120 msr = rdmsr(NB_CFG_MSR);
121 msr.hi &= ~(1 << (46-32));
122 wrmsr(NB_CFG_MSR, msr);
124 /* Write protect SMM space with SMMLOCK. */
125 msr = rdmsr(HWCR_MSR);
127 wrmsr(HWCR_MSR, msr);
131 static struct device_operations cpu_dev_ops = {
132 .init = model_10xxx_init,
134 static struct cpu_device_id cpu_table[] = {
136 { X86_VENDOR_AMD, 0x100f00 }, /* SH-F0 L1 */
137 { X86_VENDOR_AMD, 0x100f10 }, /* M2 */
138 { X86_VENDOR_AMD, 0x100f20 }, /* S1g1 */
139 { X86_VENDOR_AMD, 0x100f21 },
140 { X86_VENDOR_AMD, 0x100f2A },
141 { X86_VENDOR_AMD, 0x100f22 },
142 { X86_VENDOR_AMD, 0x100f23 },
145 static struct cpu_driver model_10xxx __cpu_driver = {
147 .id_table = cpu_table,