2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #if FAM10_SET_FIDVID == 1
21 #include "../../../northbridge/amd/amdht/AsPsDefs.h"
23 #define FAM10_SET_FIDVID_DEBUG 1
25 // if we are tight of CAR stack, disable it
26 #define FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
28 static inline void print_debug_fv(const char *str, u32 val)
30 #if FAM10_SET_FIDVID_DEBUG == 1
31 printk_debug("%s%x\n", str, val);
35 static inline void print_debug_fv_8(const char *str, u8 val)
37 #if FAM10_SET_FIDVID_DEBUG == 1
38 printk_debug("%s%02x\n", str, val);
42 static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
44 #if FAM10_SET_FIDVID_DEBUG == 1
45 printk_debug("%s%x%x\n", str, val, val2);
55 static void enable_fid_change(u8 fid)
64 for(i = 0; i < nodes; i++) {
66 dword = pci_read_config32(dev, 0xd4);
68 dword |= (u32) fid & 0x1F;
69 dword |= 1 << 5; // enable
70 pci_write_config32(dev, 0xd4, dword);
71 printk_debug("FID Change Node:%02x, F3xD4: %08x \n", i, dword);
76 static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
79 u8 highVoltageVid, lowVoltageVid, bValue;
81 u16 vSlamTimes[7]={1000,2000,3000,4000,6000,10000,20000}; /* Reg settings scaled by 100 */
85 /* This function calculates the VsSlamTime using the range of possible
86 * voltages instead of a hardcoded 200us.
87 * Note:This function is called from setFidVidRegs and setUserPs after
88 * programming a custom Pstate.
91 /* Calculate Slam Time
92 * Vslam = 0.4us/mV * Vp0 - (lowest out of Vpmin or Valt)
93 * In our case, we will scale the values by 100 to avoid
99 /* Determine if this is a PVI or SVI system */
100 dtemp = pci_read_config32(dev, 0xA0);
102 if( dtemp & PVI_MODE )
107 /* Get P0's voltage */
108 msr = rdmsr(0xC0010064);
109 highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
111 /* If SVI, we only care about CPU VID.
112 * If PVI, determine the higher voltage b/t NB and CPU
115 bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
116 if( highVoltageVid > bValue )
117 highVoltageVid = bValue;
120 /* Get Pmin's index */
121 msr = rdmsr(0xC0010061);
122 bValue = (u8) ((msr.lo >> PS_CUR_LIM_SHFT) & BIT_MASK_3);
125 msr = rdmsr(0xC0010064 + bValue);
126 lowVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
128 /* If SVI, we only care about CPU VID.
129 * If PVI, determine the higher voltage b/t NB and CPU
132 bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
133 if( lowVoltageVid > bValue )
134 lowVoltageVid = bValue;
138 dtemp = pci_read_config32(dev, 0xDC);
139 bValue = (u8) (dtemp & BIT_MASK_7);
141 /* Use the VID with the lowest voltage (higher VID) */
142 if( lowVoltageVid < bValue )
143 lowVoltageVid = bValue;
145 /* If Vids are 7Dh - 7Fh, force 7Ch to keep calculations linear */
146 if (lowVoltageVid > 0x7C) {
147 lowVoltageVid = 0x7C;
148 if(highVoltageVid > 0x7C)
149 highVoltageVid = 0x7C;
152 bValue = (u8) (lowVoltageVid - highVoltageVid);
154 /* Each Vid increment is 12.5 mV. The minimum slam time is:
155 * vidCodeDelta * 12.5mV * 0.4us/mV
156 * Scale by 100 to avoid decimals.
158 minimumSlamTime = bValue * (125 * 4);
160 /* Now round up to nearest register setting.
161 * Note that if we don't find a value, we
162 * will fall through to a value of 7
164 for(bValue=0; bValue < 7; bValue++) {
165 if(minimumSlamTime <= vSlamTimes[bValue])
169 /* Apply the value */
170 dtemp = pci_read_config32(dev, 0xD8);
171 dtemp &= VSSLAM_MASK;
173 pci_write_config32(dev, 0xd8, dtemp);
177 static void prep_fid_change(void)
184 /* This needs to be run before any Pstate changes are requested */
188 for(i = 0; i < nodes; i++) {
189 printk_debug("Prep FID/VID Node:%02x \n", i);
192 dword = pci_read_config32(dev, 0xd8);
193 dword &= VSRAMP_MASK;
194 dword |= VSRAMP_VALUE;
195 pci_write_config32(dev, 0xd8, dword);
197 /* Figure out the value for VsSlamTime and program it */
198 recalculateVsSlamTimeSettingOnCorePre(dev);
200 /* Program fields in Clock Power/Control register0 (F3xD4) */
201 /* set F3xD4 Clock Power/Timing Control 0 Register
202 * NbClkDidApplyAll=1b
204 * PowerStepUp= "platform dependent"
205 * PowerStepDown= "platform dependent"
207 * ClkRampHystSel=HW default
209 /* check platform type */
210 if (!(get_platform_type() & AMD_PTYPE_SVR)) {
211 /* For non-server platform
212 * PowerStepUp=01000b - 50nS
213 * PowerStepDown=01000b - 50ns
215 dword = pci_read_config32(dev, 0xd4);
217 dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 |
218 LNK_PLL_LOCK; /* per BKDG */
219 pci_write_config32(dev, 0xd4, dword);
221 dword = pci_read_config32(dev, 0xd4);
223 /* get number of cores for PowerStepUp & PowerStepDown in server
224 1 core - 400nS - 0000b
225 2 cores - 200nS - 0010b
226 3 cores - 133nS -> 100nS - 0011b
227 4 cores - 100nS - 0011b
229 switch(get_core_num_in_bsp(i))
232 dword |= PW_STP_UP400 | PW_STP_DN400;
236 dword |= PW_STP_UP200 | PW_STP_DN200;
239 dword |= PW_STP_UP100 | PW_STP_DN100;
242 dword |= PW_STP_UP100 | PW_STP_DN100;
245 dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK;
246 pci_write_config32(dev, 0xd4, dword);
250 dword = pci_read_config32(dev, 0xA0);
251 if(dword & PVI_MODE) { /* PVI */
252 /* set slamVidMode to 0 for PVI */
253 dword &= VID_SLAM_OFF | PLLLOCK_OFF;
254 dword |= PLLLOCK_DFT_L;
255 pci_write_config32(dev, 0xA0, dword);
257 /* set slamVidMode to 1 for SVI */
258 dword &= PLLLOCK_OFF;
259 dword |= PLLLOCK_DFT_L | VID_SLAM_ON;
260 pci_write_config32(dev, 0xA0, dword);
264 /* Program F3xD8[PwrPlanes] according F3xA0[DulaVdd] */
265 dword = pci_read_config32(dev, 0xD8);
267 if( dtemp & DUAL_VDD_BIT)
270 dword &= PWR_PLN_OFF;
271 pci_write_config32(dev, 0xD8, dword);
274 /* Note the following settings are additional from the ported
275 * function setFidVidRegs()
277 dword = pci_read_config32(dev, 0xDc);
278 dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */
279 pci_write_config32(dev, 0xdc, dword);
281 /* Rev B settings - FIXME: support other revs. */
283 pci_write_config32(dev, 0x84, dword);
286 pci_write_config32(dev, 0x80, dword);
288 dword = pci_read_config32(dev, 0x80);
289 printk_debug(" F3x80: %08x \n", dword);
290 dword = pci_read_config32(dev, 0x84);
291 printk_debug(" F3x84: %08x \n", dword);
292 dword = pci_read_config32(dev, 0xD4);
293 printk_debug(" F3xD4: %08x \n", dword);
294 dword = pci_read_config32(dev, 0xD8);
295 printk_debug(" F3xD8: %08x \n", dword);
296 dword = pci_read_config32(dev, 0xDC);
297 printk_debug(" F3xDC: %08x \n", dword);
304 static void UpdateSinglePlaneNbVid(void)
310 /* copy higher voltage (lower VID) of NBVID & CPUVID to both */
311 for (i = 0; i < 5; i++) {
312 msr = rdmsr(PS_REG_BASE + i);
313 nbVid = (msr.lo & PS_CPU_VID_M_ON) >> PS_CPU_VID_SHFT;
314 cpuVid = (msr.lo & PS_NB_VID_M_ON) >> PS_NB_VID_SHFT;
316 if( nbVid != cpuVid ) {
320 msr.lo = msr.lo & PS_BOTH_VID_OFF;
321 msr.lo = msr.lo | (u32)((nbVid) << PS_NB_VID_SHFT);
322 msr.lo = msr.lo | (u32)((nbVid) << PS_CPU_VID_SHFT);
323 wrmsr(PS_REG_BASE + i, msr);
330 static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid)
335 /* This function sets NbVid before the warm reset.
336 * Get StartupPstate from MSRC001_0071.
337 * Read Pstate register pionted by [StartupPstate].
338 * and copy its content to P0 and P1 registers.
339 * Copy newNbVid to P0[NbVid].
340 * transition to P1 on all cores,
341 * then transition to P0 on core 0.
342 * Wait for MSRC001_0063[CurPstate] = 000b on core 0.
345 msr = rdmsr(0xc0010071);
346 startup_pstate = (msr.hi >> (32-32)) & 0x07;
348 /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for this node in P0.
349 * Then transition to P1 for corex and P0 for core0.
350 * These setting will be cleared by the warm reset
352 msr = rdmsr(0xC0010064 + startup_pstate);
353 wrmsr(0xC0010065, msr);
354 wrmsr(0xC0010064, msr);
356 msr.lo &= ~0xFE000000; // clear nbvid
357 msr.lo |= newNbVid << 25;
358 wrmsr(0xC0010064, msr);
360 UpdateSinglePlaneNbVid();
362 // Transition to P1 for all APs and P0 for core0.
363 msr = rdmsr(0xC0010062);
364 msr.lo = (msr.lo & ~0x07) | 1;
365 wrmsr(0xC0010062, msr);
367 // Wait for P1 to set.
369 msr = rdmsr(0xC0010063);
370 } while (msr.lo != 1);
373 msr.lo = msr.lo & ~0x07;
374 wrmsr(0xC0010062, msr);
375 // Wait for P0 to set.
377 msr = rdmsr(0xC0010063);
378 } while (msr.lo != 0);
383 static void coreDelay (void)
390 This seems like a hack to me...
391 It would be nice to have a central delay function. */
393 cycles = 8000 << 3; /* x8 (number of 1.25ns ticks) */
395 msr = 0x10; /* TSC */
396 _RDMSR(msr, &lo, &hi);
399 _RDMSR(msr, &lo, &hi);
400 } while (lo - saved < cycles );
404 static void transitionVid(u32 targetVid, u8 dev, u8 isNb)
406 u32 currentVid, dtemp;
409 u16 timeTable[8]={10, 20, 30, 40, 60, 100, 200, 500};
412 /* This function steps or slam the Nb VID to the target VID.
413 * It uses VSRampTime for [SlamVidMode]=0 ([PviMode]=1)
414 * or VSSlamTime for [SlamVidMode]=1 ([PviMode]=0)to time period.
417 /* get the current VID */
418 msr = rdmsr(0xC0010071);
420 currentVid = (msr.lo >> NB_VID_POS) & BIT_MASK_7;
422 currentVid = (msr.lo >> CPU_VID_POS) & BIT_MASK_7;
424 /* Read MSRC001_0070 COFVID Control Register */
425 msr = rdmsr(0xC0010070);
428 dtemp = pci_read_config32(dev, 0xA0);
429 if (dtemp & PVI_MODE) { /* PVI, step VID */
430 if (currentVid < targetVid) {
431 while (currentVid < targetVid) {
434 msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS);
436 msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS);
437 wrmsr(0xC0010070, msr);
439 /* read F3xD8[VSRampTime] */
440 dtemp = pci_read_config32(dev, 0xD8);
441 vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7);
442 vsTime = (int) timeTable[vsTimecode];
448 } else if (currentVid > targetVid) {
449 while (currentVid > targetVid) {
452 msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS);
454 msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS);
455 wrmsr(0xC0010070, msr);
457 /* read F3xD8[VSRampTime] */
458 dtemp = pci_read_config32(dev, 0xD8);
459 vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7);
460 vsTime = (int) timeTable[vsTimecode];
467 } else { /* SVI, slam VID */
469 msr.lo = (msr.lo & NB_VID_MASK_OFF) | (targetVid << NB_VID_POS);
471 msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (targetVid << CPU_VID_POS);
472 wrmsr(0xC0010070, msr);
474 /* read F3xD8[VSRampTime] */
475 dtemp = pci_read_config32(dev, 0xD8);
476 vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7);
477 vsTime = (int) timeTable[vsTimecode];
486 static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid)
491 u8 nb_cof_vid_update;
498 printk_debug("FIDVID on AP: %02x\n", apicid);
500 /* Steps 1-6 of BIOS NB COF and VID Configuration
501 * for SVI and Single-Plane PVI Systems.
504 /* If any node has nb_cof_vid_update set all nodes need an update. */
506 nb_cof_vid_update = 0;
507 for (i = 0; i < nodes; i++) {
508 if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) {
509 nb_cof_vid_update = 1;
514 dev = NODE_PCI(nodeid,3);
515 pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
516 reg1fc = pci_read_config32(dev, 0x1FC);
518 if (nb_cof_vid_update) {
520 vid_max = (reg1fc >> 7) & 0x7F;
521 fid_max = (reg1fc >> 2) & 0x1F;
523 /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */
524 fixPsNbVidBeforeWR(vid_max, coreid);
526 vid_max = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F);
527 fid_max = ((reg1fc >> 2) & 0x1F) + ((reg1fc >> 14) & 0x7);
528 transitionVid(vid_max, dev, IS_NB);
531 /* fid setup is handled by the BSP at the end. */
533 } else { /* ! nb_cof_vid_update */
536 UpdateSinglePlaneNbVid();
539 send = (nb_cof_vid_update << 16) | (fid_max << 8);
540 send |= (apicid << 24); // ap apicid
542 // Send signal to BSP about this AP max fid
543 // This also indicates this AP is ready for warm reset (if required).
544 lapic_write(LAPIC_MSG_REG, send | 1);
547 static u32 calc_common_fid(u32 fid_packed, u32 fid_packed_new)
552 fidmax = (fid_packed >> 8) & 0xFF;
554 fidmax_new = (fid_packed_new >> 8) & 0xFF;
556 if(fidmax > fidmax_new) {
560 fid_packed &= 0xFF << 16;
561 fid_packed |= (fidmax << 8);
562 fid_packed |= fid_packed_new & (0xFF << 16); // set nb_cof_vid_update
568 static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp )
573 struct fidvid_st *fvp = gp;
576 print_debug_fv("Wait for AP stage 1: ap_apicid = ", ap_apicid);
580 if(lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0) continue;
581 if((readback & 0x3f) == 1) {
583 break; //target ap is in stage 1
588 print_initcpu8("fidvid_bsp_stage1: time out while reading from ap ", ap_apicid);
592 print_debug_fv("\treadback = ", readback);
594 fvp->common_fid = calc_common_fid(fvp->common_fid, readback);
596 print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid);
601 static void updateSviPsNbVidAfterWR(u32 newNbVid)
606 /* This function copies newNbVid to NbVid bits in P-state Registers[4:0]
610 for( i = 0; i < 5; i++) {
611 msr = rdmsr(0xC0010064 + i);
612 if ((msr.hi >> 31) & 1) { /* PstateEn? */
613 msr.lo &= ~(0x7F << 25);
614 msr.lo |= (newNbVid & 0x7F) << 25;
615 wrmsr(0xC0010064 + i, msr);
621 static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll)
627 /* This function copies newNbVid to NbVid bits in P-state
628 * Registers[4:0] if its NbDid bit=0 and PstateEn bit =1 in case of
629 * NbVidUpdatedAll =0 or copies copies newNbVid to NbVid bits in
630 * P-state Registers[4:0] if its and PstateEn bit =1 in case of
631 * NbVidUpdatedAll=1. Then transition to StartPstate.
634 /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
635 for( i = 0; i < 5; i++) {
636 msr = rdmsr(0xC0010064 + i);
637 /* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */
638 if ((((msr.lo >> 22) & 1) == 0) || NbVidUpdatedAll) {
639 msr.lo &= ~(0x7F << 25);
640 msr.lo |= (newNbVid & 0x7F) << 25;
641 wrmsr (0xC0010064 + i, msr);
645 UpdateSinglePlaneNbVid();
647 /* For each core in the system, transition all cores to StartupPstate */
648 msr = rdmsr(0xC0010071);
649 StartupPstate = msr.hi & 0x07;
650 msr = rdmsr(0xC0010062);
651 msr.lo = StartupPstate;
652 wrmsr(0xC0010062, msr);
654 /* Wait for StartupPstate to set.*/
656 msr = rdmsr(0xC0010063);
657 } while (msr.lo != StartupPstate);
661 static void set_p0(void)
665 // Transition P0 for calling core.
666 msr = rdmsr(0xC0010062);
667 msr.lo = (msr.lo & ~0x07);
668 wrmsr(0xC0010062, msr);
670 /* Wait for P0 to set. */
672 msr = rdmsr(0xC0010063);
673 } while (msr.lo != 0);
677 static void finalPstateChange (void) {
678 /* Enble P0 on all cores for best performance.
679 * Linux can slow them down later if need be.
680 * It is safe since they will be in C1 halt
681 * most of the time anyway.
687 static void init_fidvid_stage2(u32 apicid, u32 nodeid)
694 u8 nb_cof_vid_update;
700 /* After warm reset finish the fid/vid setup for all cores. */
702 /* If any node has nb_cof_vid_update set all nodes need an update. */
704 nb_cof_vid_update = 0;
705 for (i = 0; i < nodes; i++) {
706 if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) {
707 nb_cof_vid_update = 1;
712 dev = NODE_PCI(nodeid,3);
713 pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
714 reg1fc = pci_read_config32(dev, 0x1FC);
715 nbvid = (reg1fc >> 7) & 0x7F;
716 NbVidUpdateAll = (reg1fc >> 1) & 1;
718 if (nb_cof_vid_update) {
720 nbvid = (reg1fc >> 7) & 0x7F;
721 /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
722 fixPsNbVidAfterWR(nbvid, NbVidUpdateAll);
724 nbvid = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F);
725 updateSviPsNbVidAfterWR(nbvid);
727 } else { /* !nb_cof_vid_update */
729 UpdateSinglePlaneNbVid();
731 dtemp = pci_read_config32(dev, 0xA0);
732 dtemp &= PLLLOCK_OFF;
733 dtemp |= PLLLOCK_DFT_L;
734 pci_write_config32(dev, 0xA0, dtemp);
738 /* Set TSC to tick at the P0 ndfid rate */
745 #if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
746 struct ap_apicid_st {
748 // it could use 256 bytes for 64 node quad core system
749 u8 apicid[NODE_NUMS * 4];
752 static void store_ap_apicid(unsigned ap_apicid, void *gp)
754 struct ap_apicid_st *p = gp;
756 p->apicid[p->num++] = ap_apicid;
762 static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
764 #if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
765 struct ap_apicid_st ap_apicidx;
772 u8 nb_cof_vid_update;
776 printk_debug("FIDVID on BSP, APIC_id: %02x\n", bsp_apicid);
777 /* FIXME: The first half of this function is nearly the same as
778 * init_fidvid_bsp() and the code could be combined.
781 /* Steps 1-6 of BIOS NB COF and VID Configuration
782 * for SVI and Single-Plane PVI Systems.
785 /* If any node has nb_cof_vid_update set all nodes need an update. */
786 nb_cof_vid_update = 0;
787 for (i = 0; i < nodes; i++) {
788 if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) {
789 nb_cof_vid_update = 1;
794 dev = NODE_PCI(0, 3);
795 pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
796 reg1fc = pci_read_config32(dev, 0x1FC);
798 if (nb_cof_vid_update) {
800 vid_max = (reg1fc >> 7) & 0x7F;
801 fid_max = (reg1fc >> 2) & 0x1F;
803 /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */
804 fixPsNbVidBeforeWR(vid_max, 0);
806 vid_max = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F);
807 fid_max = ((reg1fc >> 2) & 0x1F) + ((reg1fc >> 14) & 0x7);
808 transitionVid(vid_max, dev, IS_NB);
811 /* fid setup is handled by the BSP at the end. */
813 } else { /* ! nb_cof_vid_update */
816 UpdateSinglePlaneNbVid();
819 fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8) ;
820 print_debug_fv("BSP fid = ", fv.common_fid);
822 #if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 && FAM10_SET_FIDVID_CORE0_ONLY == 0
823 /* For all APs (We know the APIC ID of all APs even when the APIC ID
824 is lifted) remote read from AP LAPIC_MSG_REG about max fid.
825 Then calculate the common max fid that can be used for all
829 for_each_ap(bsp_apicid, FAM10_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx);
831 for(i = 0; i < ap_apicidx.num; i++) {
832 init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
835 for_each_ap(bsp_apicid, FAM10_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
838 print_debug_fv("common_fid = ", fv.common_fid);
840 if (fv.common_fid & (1 << 16)) { /* check nb_cof_vid_update */
842 // Enable the common fid and other settings.
843 enable_fid_change((fv.common_fid >> 8) & 0x1F);
845 // nbfid change need warm reset, so reset at first
849 return 0; // No FID/VID changes. Don't reset