2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <northbridge/amd/amdht/AsPsDefs.h>
23 static inline void print_debug_fv(const char *str, u32 val)
25 #if CONFIG_SET_FIDVID_DEBUG
26 printk(BIOS_DEBUG, "%s%x\n", str, val);
30 static inline void print_debug_fv_8(const char *str, u8 val)
32 #if CONFIG_SET_FIDVID_DEBUG
33 printk(BIOS_DEBUG, "%s%02x\n", str, val);
37 static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
39 #if CONFIG_SET_FIDVID_DEBUG
40 printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
48 static void enable_fid_change(u8 fid)
57 for (i = 0; i < nodes; i++) {
59 dword = pci_read_config32(dev, 0xd4);
61 dword |= (u32) fid & 0x1F;
62 dword |= 1 << 5; // enable
63 pci_write_config32(dev, 0xd4, dword);
64 printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i,
69 static void setVSRamp(device_t dev) {
70 /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime]
71 * If this field accepts 8 values between 10 and 500 us why
72 * does page 324 say "BIOS should set this field to 001b."
74 * Shouldn't it depend on the voltage regulators, mainboard
78 dword = pci_read_config32(dev, 0xd8);
80 dword |= VSRAMP_VALUE;
81 pci_write_config32(dev, 0xd8, dword);
84 static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
87 u8 highVoltageVid, lowVoltageVid, bValue;
89 u16 vSlamTimes[7] = { 1000, 2000, 3000, 4000, 6000, 10000, 20000 }; /* Reg settings scaled by 100 */
93 /* This function calculates the VsSlamTime using the range of possible
94 * voltages instead of a hardcoded 200us.
95 * Note:This function is called from setFidVidRegs and setUserPs after
96 * programming a custom Pstate.
99 /* Calculate Slam Time
100 * Vslam = 0.4us/mV * Vp0 - (lowest out of Vpmin or Valt)
101 * In our case, we will scale the values by 100 to avoid
105 /* Determine if this is a PVI or SVI system */
106 dtemp = pci_read_config32(dev, 0xA0);
108 if (dtemp & PVI_MODE)
113 /* Get P0's voltage */
114 msr = rdmsr(0xC0010064);
115 highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
117 /* If SVI, we only care about CPU VID.
118 * If PVI, determine the higher voltage b/t NB and CPU
121 bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
122 if (highVoltageVid > bValue)
123 highVoltageVid = bValue;
126 /* Get Pmin's index */
127 msr = rdmsr(0xC0010061);
128 bValue = (u8) ((msr.lo >> PS_CUR_LIM_SHFT) & BIT_MASK_3);
131 msr = rdmsr(0xC0010064 + bValue);
132 lowVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
134 /* If SVI, we only care about CPU VID.
135 * If PVI, determine the higher voltage b/t NB and CPU
138 bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
139 if (lowVoltageVid > bValue)
140 lowVoltageVid = bValue;
144 dtemp = pci_read_config32(dev, 0xDC);
145 bValue = (u8) (dtemp & BIT_MASK_7);
147 /* Use the VID with the lowest voltage (higher VID) */
148 if (lowVoltageVid < bValue)
149 lowVoltageVid = bValue;
151 /* If Vids are 7Dh - 7Fh, force 7Ch to keep calculations linear */
152 if (lowVoltageVid > 0x7C) {
153 lowVoltageVid = 0x7C;
154 if (highVoltageVid > 0x7C)
155 highVoltageVid = 0x7C;
158 bValue = (u8) (lowVoltageVid - highVoltageVid);
160 /* Each Vid increment is 12.5 mV. The minimum slam time is:
161 * vidCodeDelta * 12.5mV * 0.4us/mV
162 * Scale by 100 to avoid decimals.
164 minimumSlamTime = bValue * (125 * 4);
166 /* Now round up to nearest register setting.
167 * Note that if we don't find a value, we
168 * will fall through to a value of 7
170 for (bValue = 0; bValue < 7; bValue++) {
171 if (minimumSlamTime <= vSlamTimes[bValue])
175 /* Apply the value */
176 dtemp = pci_read_config32(dev, 0xD8);
177 dtemp &= VSSLAM_MASK;
179 pci_write_config32(dev, 0xd8, dtemp);
182 static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) {
185 if (AMD_CpuFindCapability(node, 0, &offset)) {
186 link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 );
188 /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package
189 S1g3 in link Gen3 mode, but I don't know how to tell
190 package S1g3 from S1g4 */
191 if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX)
193 return 5 ; /* divide clk by 128*/
195 return 4 ; /* divide clk by 16 */
200 static u32 power_up_down(int node, u8 procPkg) {
202 /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */
203 u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2)
204 || (procPkg == AMD_PKGTYPE_S1gX)
205 || (procPkg == AMD_PKGTYPE_ASB2));
207 if (singleLinkFlag) {
209 * PowerStepUp=01000b - 50nS
210 * PowerStepDown=01000b - 50ns
212 dword |= PW_STP_UP50 | PW_STP_DN50;
214 u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1;
217 for(j=0 ; (j<4) && (!isocEn) ; j++ ) {
219 if (AMD_CpuFindCapability(node, j, &offset)) {
220 isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1;
224 if (dispRefModeEn || isocEn) {
225 dword |= PW_STP_UP50 | PW_STP_DN50 ;
227 /* get number of cores for PowerStepUp & PowerStepDown in server
228 1 core - 400nS - 0000b
229 2 cores - 200nS - 0010b
230 3 cores - 133nS -> 100nS - 0011b
231 4 cores - 100nS - 0011b
233 switch (get_core_num_in_bsp(node)) {
235 dword |= PW_STP_UP400 | PW_STP_DN400;
239 dword |= PW_STP_UP200 | PW_STP_DN200;
242 dword |= PW_STP_UP100 | PW_STP_DN100;
245 dword |= PW_STP_UP100 | PW_STP_DN100;
253 static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
254 device_t dev = NODE_PCI(node, 3);
256 /* Program fields in Clock Power/Control register0 (F3xD4) */
258 /* set F3xD4 Clock Power/Timing Control 0 Register
259 * NbClkDidApplyAll=1b
260 * NbClkDid=100b or 101b
261 * PowerStepUp= "platform dependent"
262 * PowerStepDown= "platform dependent"
264 * ClkRampHystCtl=HW default
265 * ClkRampHystSel=1111b
267 u32 dword= pci_read_config32(dev, 0xd4);
269 dword |= NB_CLKDID_ALL | LNK_PLL_LOCK | CLK_RAMP_HYST_SEL_VAL;
270 dword |= (nb_clk_did(node,cpuRev,procPkg) << NB_CLKDID_SHIFT);
272 dword |= power_up_down(node, procPkg);
274 pci_write_config32(dev, 0xd4, dword);
278 static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
280 u32 dword = pci_read_config32(dev, 0xA0);
282 /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xA0[VSSlamVidMod] */
283 /* PllLockTime and PsiVidEn set in ruleset in defaults.h */
284 if (dword & PVI_MODE) { /* PVI */
285 /* set slamVidMode to 0 for PVI */
286 dword &= VID_SLAM_OFF ;
288 /* set slamVidMode to 1 for SVI */
289 dword |= VID_SLAM_ON;
293 /* Program F3xD8[PwrPlanes] according F3xA0[DulaVdd] */
294 dword = pci_read_config32(dev, 0xD8);
296 if (dtemp & DUAL_VDD_BIT)
299 dword &= PWR_PLN_OFF;
300 pci_write_config32(dev, 0xD8, dword);
304 /* set the rest of A0 since we're at it... */
306 if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) {
307 dword |= NB_PSTATE_FORCE_ON;
308 } // else should we clear it ?
311 if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) {
312 dword |= BP_INS_TRI_EN_ON ;
315 /* TODO: look into C1E state and F3xA0[IdleExitEn]*/
316 #if CONFIG_SVI_HIGH_FREQ
317 if (cpuRev & AMD_FAM10_C3) {
318 dword |= SVI_HIGH_FREQ_ON;
321 pci_write_config32(dev, 0xA0, dword);
324 static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
325 /* Note the following settings are additional from the ported
326 * function setFidVidRegs()
328 /* adjust FIFO between nb and core clocks to max allowed
329 values (min latency) */
330 u32 nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK;
332 if ((cpuRev & (AMD_DR_Bx|AMD_DA_Cx) )
333 || ( (cpuRev & AMD_RB_C3) && (nbPstate!=0))) {
339 u32 dword = pci_read_config32(dev, 0xDc);
340 dword &= ~ NB_SYN_PTR_ADJ_MASK;
341 dword |= nbSynPtrAdj << NB_SYN_PTR_ADJ_POS;
342 /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */
343 pci_write_config32(dev, 0xdc, dword);
346 static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) {
347 /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */
350 if (cpuRev & (AMD_DR_Bx)) {
351 // will coreboot ever enable cache scrubbing ?
352 // if it does, will it be enough to check the current state
353 // or should we configure for what we'll set up later ?
354 dword = pci_read_config32(dev, 0x58);
355 u32 scrubbingCache = dword &
356 ( (0x1F << 16) // DCacheScrub
357 | (0x1F << 8) ); // L2Scrub
358 if (scrubbingCache) {
363 } else { // rev C or later
364 // same doubt as cache scrubbing: ok to check current state ?
365 dword = pci_read_config32(dev, 0xDC);
366 u32 cacheFlushOnHalt = dword & (7 << 16);
367 if (!cacheFlushOnHalt) {
371 dword = (c1 << 24) | (0xE641E6);
372 pci_write_config32(dev, 0x84, dword);
375 /* FIXME: BKDG Table 100 says if the link is at a Gen1
376 frequency and the chipset does not support a 10us minimum LDTSTOP
377 assertion time, then { If ASB2 && SVI then smaf001 = F6h else
378 smaf001=87h. } else ... I hardly know what it means or how to check
379 it from here, so I bluntly assume it is false and code here the else,
383 if (cpuRev & AMD_DR_Bx ) {
386 #if CONFIG_SVI_HIGH_FREQ
387 if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) {
392 u32 fidvidChange = 0;
393 if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX))
394 || (cpuRev & AMD_RB_C3) ) {
397 dword = (0xE6 << 24) | (fidvidChange << 16)
398 | (smaf001 << 8) | 0x81;
399 pci_write_config32(dev, 0x80, dword);
402 static void prep_fid_change(void)
409 /* This needs to be run before any Pstate changes are requested */
413 for (i = 0; i < nodes; i++) {
414 printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
415 dev = NODE_PCI(i, 3);
416 u32 cpuRev = mctGetLogicalCPUID(0xFF) ;
417 u8 procPkg = mctGetProcessorPackageType();
420 /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */
421 /* Figure out the value for VsSlamTime and program it */
422 recalculateVsSlamTimeSettingOnCorePre(dev);
424 config_clk_power_ctrl_reg0(i,cpuRev,procPkg);
426 config_power_ctrl_misc_reg(dev,cpuRev,procPkg);
427 config_nb_syn_ptr_adj(dev,cpuRev);
429 config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg);
431 dword = pci_read_config32(dev, 0x80);
432 printk(BIOS_DEBUG, " F3x80: %08x \n", dword);
433 dword = pci_read_config32(dev, 0x84);
434 printk(BIOS_DEBUG, " F3x84: %08x \n", dword);
435 dword = pci_read_config32(dev, 0xD4);
436 printk(BIOS_DEBUG, " F3xD4: %08x \n", dword);
437 dword = pci_read_config32(dev, 0xD8);
438 printk(BIOS_DEBUG, " F3xD8: %08x \n", dword);
439 dword = pci_read_config32(dev, 0xDC);
440 printk(BIOS_DEBUG, " F3xDC: %08x \n", dword);
447 static void UpdateSinglePlaneNbVid(void)
453 /* copy higher voltage (lower VID) of NBVID & CPUVID to both */
454 for (i = 0; i < 5; i++) {
455 msr = rdmsr(PS_REG_BASE + i);
456 nbVid = (msr.lo & PS_CPU_VID_M_ON) >> PS_CPU_VID_SHFT;
457 cpuVid = (msr.lo & PS_NB_VID_M_ON) >> PS_NB_VID_SHFT;
459 if (nbVid != cpuVid) {
463 msr.lo = msr.lo & PS_BOTH_VID_OFF;
464 msr.lo = msr.lo | (u32) ((nbVid) << PS_NB_VID_SHFT);
465 msr.lo = msr.lo | (u32) ((nbVid) << PS_CPU_VID_SHFT);
466 wrmsr(PS_REG_BASE + i, msr);
471 static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid)
476 /* This function sets NbVid before the warm reset.
477 * Get StartupPstate from MSRC001_0071.
478 * Read Pstate register pionted by [StartupPstate].
479 * and copy its content to P0 and P1 registers.
480 * Copy newNbVid to P0[NbVid].
481 * transition to P1 on all cores,
482 * then transition to P0 on core 0.
483 * Wait for MSRC001_0063[CurPstate] = 000b on core 0.
486 msr = rdmsr(0xc0010071);
487 startup_pstate = (msr.hi >> (32 - 32)) & 0x07;
489 /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for this node in P0.
490 * Then transition to P1 for corex and P0 for core0.
491 * These setting will be cleared by the warm reset
493 msr = rdmsr(0xC0010064 + startup_pstate);
494 wrmsr(0xC0010065, msr);
495 wrmsr(0xC0010064, msr);
497 msr.lo &= ~0xFE000000; // clear nbvid
498 msr.lo |= newNbVid << 25;
499 wrmsr(0xC0010064, msr);
501 UpdateSinglePlaneNbVid();
503 // Transition to P1 for all APs and P0 for core0.
504 msr = rdmsr(0xC0010062);
505 msr.lo = (msr.lo & ~0x07) | 1;
506 wrmsr(0xC0010062, msr);
508 // Wait for P1 to set.
510 msr = rdmsr(0xC0010063);
511 } while (msr.lo != 1);
514 msr.lo = msr.lo & ~0x07;
515 wrmsr(0xC0010062, msr);
516 // Wait for P0 to set.
518 msr = rdmsr(0xC0010063);
519 } while (msr.lo != 0);
523 static void coreDelay(void)
530 This seems like a hack to me...
531 It would be nice to have a central delay function. */
533 cycles = 8000 << 3; /* x8 (number of 1.25ns ticks) */
535 msr = 0x10; /* TSC */
536 _RDMSR(msr, &lo, &hi);
539 _RDMSR(msr, &lo, &hi);
540 } while (lo - saved < cycles);
543 static void transitionVid(u32 targetVid, u8 dev, u8 isNb)
545 u32 currentVid, dtemp;
548 u16 timeTable[8] = { 10, 20, 30, 40, 60, 100, 200, 500 };
551 /* This function steps or slam the Nb VID to the target VID.
552 * It uses VSRampTime for [SlamVidMode]=0 ([PviMode]=1)
553 * or VSSlamTime for [SlamVidMode]=1 ([PviMode]=0)to time period.
556 /* get the current VID */
557 msr = rdmsr(0xC0010071);
559 currentVid = (msr.lo >> NB_VID_POS) & BIT_MASK_7;
561 currentVid = (msr.lo >> CPU_VID_POS) & BIT_MASK_7;
563 /* Read MSRC001_0070 COFVID Control Register */
564 msr = rdmsr(0xC0010070);
567 dtemp = pci_read_config32(dev, 0xA0);
568 if (dtemp & PVI_MODE) { /* PVI, step VID */
569 if (currentVid < targetVid) {
570 while (currentVid < targetVid) {
573 msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS);
575 msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS);
576 wrmsr(0xC0010070, msr);
578 /* read F3xD8[VSRampTime] */
579 dtemp = pci_read_config32(dev, 0xD8);
580 vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7);
581 vsTime = (int)timeTable[vsTimecode];
585 } while (vsTime > 0);
587 } else if (currentVid > targetVid) {
588 while (currentVid > targetVid) {
591 msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS);
593 msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS);
594 wrmsr(0xC0010070, msr);
596 /* read F3xD8[VSRampTime] */
597 dtemp = pci_read_config32(dev, 0xD8);
598 vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7);
599 vsTime = (int)timeTable[vsTimecode];
603 } while (vsTime > 0);
606 } else { /* SVI, slam VID */
608 msr.lo = (msr.lo & NB_VID_MASK_OFF) | (targetVid << NB_VID_POS);
610 msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (targetVid << CPU_VID_POS);
611 wrmsr(0xC0010070, msr);
613 /* read F3xD8[VSRampTime] */
614 dtemp = pci_read_config32(dev, 0xD8);
615 vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7);
616 vsTime = (int)timeTable[vsTimecode];
620 } while (vsTime > 0);
624 static u32 needs_NB_COF_VID_update(void)
626 u8 nb_cof_vid_update;
630 /* If any node has nb_cof_vid_update set all nodes need an update. */
632 nb_cof_vid_update = 0;
633 for (i = 0; i < nodes; i++) {
634 if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) {
635 nb_cof_vid_update = 1;
639 return nb_cof_vid_update;
642 static u32 init_fidvid_core(u32 nodeid, u32 coreid)
647 u8 nb_cof_vid_update = needs_NB_COF_VID_update();
651 /* Steps 1-6 of BIOS NB COF and VID Configuration
652 * for SVI and Single-Plane PVI Systems.
655 dev = NODE_PCI(nodeid, 3);
656 pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
657 reg1fc = pci_read_config32(dev, 0x1FC);
659 if (nb_cof_vid_update) {
661 vid_max = (reg1fc >> 7) & 0x7F;
662 fid_max = (reg1fc >> 2) & 0x1F;
664 /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */
665 fixPsNbVidBeforeWR(vid_max, coreid);
667 vid_max = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F);
668 fid_max = ((reg1fc >> 2) & 0x1F) + ((reg1fc >> 14) & 0x7);
669 transitionVid(vid_max, dev, IS_NB);
672 /* fid setup is handled by the BSP at the end. */
674 } else { /* ! nb_cof_vid_update */
677 UpdateSinglePlaneNbVid();
680 return ((nb_cof_vid_update << 16) | (fid_max << 8));
684 static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid)
688 printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid);
690 send = init_fidvid_core(nodeid,coreid);
691 send |= (apicid << 24); // ap apicid
693 // Send signal to BSP about this AP max fid
694 // This also indicates this AP is ready for warm reset (if required).
695 lapic_write(LAPIC_MSG_REG, send | F10_APSTATE_RESET);
698 static u32 calc_common_fid(u32 fid_packed, u32 fid_packed_new)
703 fidmax = (fid_packed >> 8) & 0xFF;
705 fidmax_new = (fid_packed_new >> 8) & 0xFF;
707 if (fidmax > fidmax_new) {
711 fid_packed &= 0xFF << 16;
712 fid_packed |= (fidmax << 8);
713 fid_packed |= fid_packed_new & (0xFF << 16); // set nb_cof_vid_update
718 static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp)
723 struct fidvid_st *fvp = gp;
726 print_debug_fv("Wait for AP stage 1: ap_apicid = ", ap_apicid);
730 if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0)
732 if ((readback & 0x3f) == 1) {
734 break; /* target ap is in stage 1 */
739 printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n",
740 __func__, ap_apicid);
744 print_debug_fv("\treadback = ", readback);
746 fvp->common_fid = calc_common_fid(fvp->common_fid, readback);
748 print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid);
752 static void updateSviPsNbVidAfterWR(u32 newNbVid)
757 /* This function copies newNbVid to NbVid bits in P-state Registers[4:0]
761 for (i = 0; i < 5; i++) {
762 msr = rdmsr(0xC0010064 + i);
763 if ((msr.hi >> 31) & 1) { /* PstateEn? */
764 msr.lo &= ~(0x7F << 25);
765 msr.lo |= (newNbVid & 0x7F) << 25;
766 wrmsr(0xC0010064 + i, msr);
772 static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll)
778 /* This function copies newNbVid to NbVid bits in P-state
779 * Registers[4:0] if its NbDid bit=0 and PstateEn bit =1 in case of
780 * NbVidUpdatedAll =0 or copies copies newNbVid to NbVid bits in
781 * P-state Registers[4:0] if its and PstateEn bit =1 in case of
782 * NbVidUpdatedAll=1. Then transition to StartPstate.
785 /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
786 for (i = 0; i < 5; i++) {
787 msr = rdmsr(0xC0010064 + i);
788 /* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */
789 if ((((msr.lo >> 22) & 1) == 0) || NbVidUpdatedAll) {
790 msr.lo &= ~(0x7F << 25);
791 msr.lo |= (newNbVid & 0x7F) << 25;
792 wrmsr(0xC0010064 + i, msr);
796 UpdateSinglePlaneNbVid();
798 /* For each core in the system, transition all cores to StartupPstate */
799 msr = rdmsr(0xC0010071);
800 StartupPstate = msr.hi & 0x07;
801 msr = rdmsr(0xC0010062);
802 msr.lo = StartupPstate;
803 wrmsr(0xC0010062, msr);
805 /* Wait for StartupPstate to set. */
807 msr = rdmsr(0xC0010063);
808 } while (msr.lo != StartupPstate);
811 static void set_p0(void)
815 // Transition P0 for calling core.
816 msr = rdmsr(0xC0010062);
817 msr.lo = (msr.lo & ~0x07);
818 wrmsr(0xC0010062, msr);
820 /* Wait for P0 to set. */
822 msr = rdmsr(0xC0010063);
823 } while (msr.lo != 0);
826 static void finalPstateChange(void)
828 /* Enble P0 on all cores for best performance.
829 * Linux can slow them down later if need be.
830 * It is safe since they will be in C1 halt
831 * most of the time anyway.
836 static void init_fidvid_stage2(u32 apicid, u32 nodeid)
843 u8 nb_cof_vid_update = needs_NB_COF_VID_update();
847 /* After warm reset finish the fid/vid setup for all cores. */
849 /* If any node has nb_cof_vid_update set all nodes need an update. */
851 dev = NODE_PCI(nodeid, 3);
852 pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
853 reg1fc = pci_read_config32(dev, 0x1FC);
854 nbvid = (reg1fc >> 7) & 0x7F;
855 NbVidUpdateAll = (reg1fc >> 1) & 1;
857 if (nb_cof_vid_update) {
859 nbvid = (reg1fc >> 7) & 0x7F;
860 /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
861 fixPsNbVidAfterWR(nbvid, NbVidUpdateAll);
863 nbvid = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F);
864 updateSviPsNbVidAfterWR(nbvid);
866 } else { /* !nb_cof_vid_update */
868 UpdateSinglePlaneNbVid();
870 dtemp = pci_read_config32(dev, 0xA0);
871 dtemp &= PLLLOCK_OFF;
872 dtemp |= PLLLOCK_DFT_L;
873 pci_write_config32(dev, 0xA0, dtemp);
877 /* Set TSC to tick at the P0 ndfid rate */
884 #if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
885 struct ap_apicid_st {
887 // it could use 256 bytes for 64 node quad core system
888 u8 apicid[NODE_NUMS * 4];
891 static void store_ap_apicid(unsigned ap_apicid, void *gp)
893 struct ap_apicid_st *p = gp;
895 p->apicid[p->num++] = ap_apicid;
901 static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
903 #if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST
904 struct ap_apicid_st ap_apicidx;
909 printk(BIOS_DEBUG, "FIDVID on BSP, APIC_id: %02x\n", bsp_apicid);
911 /* Steps 1-6 of BIOS NB COF and VID Configuration
912 * for SVI and Single-Plane PVI Systems.
915 fv.common_fid = init_fidvid_core(0,0);
917 print_debug_fv("BSP fid = ", fv.common_fid);
919 #if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST && !CONFIG_SET_FIDVID_CORE0_ONLY
920 /* For all APs (We know the APIC ID of all APs even when the APIC ID
921 is lifted) remote read from AP LAPIC_MSG_REG about max fid.
922 Then calculate the common max fid that can be used for all
926 for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx);
928 for (i = 0; i < ap_apicidx.num; i++) {
929 init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
932 for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
935 print_debug_fv("common_fid = ", fv.common_fid);
937 if (fv.common_fid & (1 << 16)) { /* check nb_cof_vid_update */
939 // Enable the common fid and other settings.
940 enable_fid_change((fv.common_fid >> 8) & 0x1F);
942 // nbfid change need warm reset, so reset at first
946 return 0; // No FID/VID changes. Don't reset