2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <northbridge/amd/amdht/AsPsDefs.h>
23 #define SET_FIDVID_DEBUG 1
25 // if we are tight of CAR stack, disable it
26 #define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
28 static inline void print_debug_fv(const char *str, u32 val)
30 #if SET_FIDVID_DEBUG == 1
31 printk(BIOS_DEBUG, "%s%x\n", str, val);
35 static inline void print_debug_fv_8(const char *str, u8 val)
37 #if SET_FIDVID_DEBUG == 1
38 printk(BIOS_DEBUG, "%s%02x\n", str, val);
42 static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
44 #if SET_FIDVID_DEBUG == 1
45 printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
53 static void enable_fid_change(u8 fid)
62 for (i = 0; i < nodes; i++) {
64 dword = pci_read_config32(dev, 0xd4);
66 dword |= (u32) fid & 0x1F;
67 dword |= 1 << 5; // enable
68 pci_write_config32(dev, 0xd4, dword);
69 printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i,
74 static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
77 u8 highVoltageVid, lowVoltageVid, bValue;
79 u16 vSlamTimes[7] = { 1000, 2000, 3000, 4000, 6000, 10000, 20000 }; /* Reg settings scaled by 100 */
83 /* This function calculates the VsSlamTime using the range of possible
84 * voltages instead of a hardcoded 200us.
85 * Note:This function is called from setFidVidRegs and setUserPs after
86 * programming a custom Pstate.
89 /* Calculate Slam Time
90 * Vslam = 0.4us/mV * Vp0 - (lowest out of Vpmin or Valt)
91 * In our case, we will scale the values by 100 to avoid
95 /* Determine if this is a PVI or SVI system */
96 dtemp = pci_read_config32(dev, 0xA0);
103 /* Get P0's voltage */
104 msr = rdmsr(0xC0010064);
105 highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
107 /* If SVI, we only care about CPU VID.
108 * If PVI, determine the higher voltage b/t NB and CPU
111 bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
112 if (highVoltageVid > bValue)
113 highVoltageVid = bValue;
116 /* Get Pmin's index */
117 msr = rdmsr(0xC0010061);
118 bValue = (u8) ((msr.lo >> PS_CUR_LIM_SHFT) & BIT_MASK_3);
121 msr = rdmsr(0xC0010064 + bValue);
122 lowVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
124 /* If SVI, we only care about CPU VID.
125 * If PVI, determine the higher voltage b/t NB and CPU
128 bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F);
129 if (lowVoltageVid > bValue)
130 lowVoltageVid = bValue;
134 dtemp = pci_read_config32(dev, 0xDC);
135 bValue = (u8) (dtemp & BIT_MASK_7);
137 /* Use the VID with the lowest voltage (higher VID) */
138 if (lowVoltageVid < bValue)
139 lowVoltageVid = bValue;
141 /* If Vids are 7Dh - 7Fh, force 7Ch to keep calculations linear */
142 if (lowVoltageVid > 0x7C) {
143 lowVoltageVid = 0x7C;
144 if (highVoltageVid > 0x7C)
145 highVoltageVid = 0x7C;
148 bValue = (u8) (lowVoltageVid - highVoltageVid);
150 /* Each Vid increment is 12.5 mV. The minimum slam time is:
151 * vidCodeDelta * 12.5mV * 0.4us/mV
152 * Scale by 100 to avoid decimals.
154 minimumSlamTime = bValue * (125 * 4);
156 /* Now round up to nearest register setting.
157 * Note that if we don't find a value, we
158 * will fall through to a value of 7
160 for (bValue = 0; bValue < 7; bValue++) {
161 if (minimumSlamTime <= vSlamTimes[bValue])
165 /* Apply the value */
166 dtemp = pci_read_config32(dev, 0xD8);
167 dtemp &= VSSLAM_MASK;
169 pci_write_config32(dev, 0xd8, dtemp);
172 static void prep_fid_change(void)
179 /* This needs to be run before any Pstate changes are requested */
183 for (i = 0; i < nodes; i++) {
184 printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
185 dev = NODE_PCI(i, 3);
187 dword = pci_read_config32(dev, 0xd8);
188 dword &= VSRAMP_MASK;
189 dword |= VSRAMP_VALUE;
190 pci_write_config32(dev, 0xd8, dword);
192 /* Figure out the value for VsSlamTime and program it */
193 recalculateVsSlamTimeSettingOnCorePre(dev);
195 /* Program fields in Clock Power/Control register0 (F3xD4) */
196 /* set F3xD4 Clock Power/Timing Control 0 Register
197 * NbClkDidApplyAll=1b
199 * PowerStepUp= "platform dependent"
200 * PowerStepDown= "platform dependent"
202 * ClkRampHystSel=HW default
204 /* check platform type */
205 if (!(get_platform_type() & AMD_PTYPE_SVR)) {
206 /* For non-server platform
207 * PowerStepUp=01000b - 50nS
208 * PowerStepDown=01000b - 50ns
210 dword = pci_read_config32(dev, 0xd4);
212 dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 | LNK_PLL_LOCK; /* per BKDG */
213 pci_write_config32(dev, 0xd4, dword);
215 dword = pci_read_config32(dev, 0xd4);
217 /* get number of cores for PowerStepUp & PowerStepDown in server
218 1 core - 400nS - 0000b
219 2 cores - 200nS - 0010b
220 3 cores - 133nS -> 100nS - 0011b
221 4 cores - 100nS - 0011b
223 switch (get_core_num_in_bsp(i)) {
225 dword |= PW_STP_UP400 | PW_STP_DN400;
229 dword |= PW_STP_UP200 | PW_STP_DN200;
232 dword |= PW_STP_UP100 | PW_STP_DN100;
235 dword |= PW_STP_UP100 | PW_STP_DN100;
238 dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK;
239 pci_write_config32(dev, 0xd4, dword);
243 dword = pci_read_config32(dev, 0xA0);
244 if (dword & PVI_MODE) { /* PVI */
245 /* set slamVidMode to 0 for PVI */
246 dword &= VID_SLAM_OFF | PLLLOCK_OFF;
247 dword |= PLLLOCK_DFT_L;
248 pci_write_config32(dev, 0xA0, dword);
250 /* set slamVidMode to 1 for SVI */
251 dword &= PLLLOCK_OFF;
252 dword |= PLLLOCK_DFT_L | VID_SLAM_ON;
253 pci_write_config32(dev, 0xA0, dword);
257 /* Program F3xD8[PwrPlanes] according F3xA0[DulaVdd] */
258 dword = pci_read_config32(dev, 0xD8);
260 if (dtemp & DUAL_VDD_BIT)
263 dword &= PWR_PLN_OFF;
264 pci_write_config32(dev, 0xD8, dword);
267 /* Note the following settings are additional from the ported
268 * function setFidVidRegs()
270 dword = pci_read_config32(dev, 0xDc);
271 dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */
272 pci_write_config32(dev, 0xdc, dword);
274 /* Rev B settings - FIXME: support other revs. */
276 pci_write_config32(dev, 0x84, dword);
279 pci_write_config32(dev, 0x80, dword);
281 dword = pci_read_config32(dev, 0x80);
282 printk(BIOS_DEBUG, " F3x80: %08x \n", dword);
283 dword = pci_read_config32(dev, 0x84);
284 printk(BIOS_DEBUG, " F3x84: %08x \n", dword);
285 dword = pci_read_config32(dev, 0xD4);
286 printk(BIOS_DEBUG, " F3xD4: %08x \n", dword);
287 dword = pci_read_config32(dev, 0xD8);
288 printk(BIOS_DEBUG, " F3xD8: %08x \n", dword);
289 dword = pci_read_config32(dev, 0xDC);
290 printk(BIOS_DEBUG, " F3xDC: %08x \n", dword);
297 static void UpdateSinglePlaneNbVid(void)
303 /* copy higher voltage (lower VID) of NBVID & CPUVID to both */
304 for (i = 0; i < 5; i++) {
305 msr = rdmsr(PS_REG_BASE + i);
306 nbVid = (msr.lo & PS_CPU_VID_M_ON) >> PS_CPU_VID_SHFT;
307 cpuVid = (msr.lo & PS_NB_VID_M_ON) >> PS_NB_VID_SHFT;
309 if (nbVid != cpuVid) {
313 msr.lo = msr.lo & PS_BOTH_VID_OFF;
314 msr.lo = msr.lo | (u32) ((nbVid) << PS_NB_VID_SHFT);
315 msr.lo = msr.lo | (u32) ((nbVid) << PS_CPU_VID_SHFT);
316 wrmsr(PS_REG_BASE + i, msr);
321 static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid)
326 /* This function sets NbVid before the warm reset.
327 * Get StartupPstate from MSRC001_0071.
328 * Read Pstate register pionted by [StartupPstate].
329 * and copy its content to P0 and P1 registers.
330 * Copy newNbVid to P0[NbVid].
331 * transition to P1 on all cores,
332 * then transition to P0 on core 0.
333 * Wait for MSRC001_0063[CurPstate] = 000b on core 0.
336 msr = rdmsr(0xc0010071);
337 startup_pstate = (msr.hi >> (32 - 32)) & 0x07;
339 /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for this node in P0.
340 * Then transition to P1 for corex and P0 for core0.
341 * These setting will be cleared by the warm reset
343 msr = rdmsr(0xC0010064 + startup_pstate);
344 wrmsr(0xC0010065, msr);
345 wrmsr(0xC0010064, msr);
347 msr.lo &= ~0xFE000000; // clear nbvid
348 msr.lo |= newNbVid << 25;
349 wrmsr(0xC0010064, msr);
351 UpdateSinglePlaneNbVid();
353 // Transition to P1 for all APs and P0 for core0.
354 msr = rdmsr(0xC0010062);
355 msr.lo = (msr.lo & ~0x07) | 1;
356 wrmsr(0xC0010062, msr);
358 // Wait for P1 to set.
360 msr = rdmsr(0xC0010063);
361 } while (msr.lo != 1);
364 msr.lo = msr.lo & ~0x07;
365 wrmsr(0xC0010062, msr);
366 // Wait for P0 to set.
368 msr = rdmsr(0xC0010063);
369 } while (msr.lo != 0);
373 static void coreDelay(void)
380 This seems like a hack to me...
381 It would be nice to have a central delay function. */
383 cycles = 8000 << 3; /* x8 (number of 1.25ns ticks) */
385 msr = 0x10; /* TSC */
386 _RDMSR(msr, &lo, &hi);
389 _RDMSR(msr, &lo, &hi);
390 } while (lo - saved < cycles);
393 static void transitionVid(u32 targetVid, u8 dev, u8 isNb)
395 u32 currentVid, dtemp;
398 u16 timeTable[8] = { 10, 20, 30, 40, 60, 100, 200, 500 };
401 /* This function steps or slam the Nb VID to the target VID.
402 * It uses VSRampTime for [SlamVidMode]=0 ([PviMode]=1)
403 * or VSSlamTime for [SlamVidMode]=1 ([PviMode]=0)to time period.
406 /* get the current VID */
407 msr = rdmsr(0xC0010071);
409 currentVid = (msr.lo >> NB_VID_POS) & BIT_MASK_7;
411 currentVid = (msr.lo >> CPU_VID_POS) & BIT_MASK_7;
413 /* Read MSRC001_0070 COFVID Control Register */
414 msr = rdmsr(0xC0010070);
417 dtemp = pci_read_config32(dev, 0xA0);
418 if (dtemp & PVI_MODE) { /* PVI, step VID */
419 if (currentVid < targetVid) {
420 while (currentVid < targetVid) {
423 msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS);
425 msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS);
426 wrmsr(0xC0010070, msr);
428 /* read F3xD8[VSRampTime] */
429 dtemp = pci_read_config32(dev, 0xD8);
430 vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7);
431 vsTime = (int)timeTable[vsTimecode];
435 } while (vsTime > 0);
437 } else if (currentVid > targetVid) {
438 while (currentVid > targetVid) {
441 msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS);
443 msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS);
444 wrmsr(0xC0010070, msr);
446 /* read F3xD8[VSRampTime] */
447 dtemp = pci_read_config32(dev, 0xD8);
448 vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7);
449 vsTime = (int)timeTable[vsTimecode];
453 } while (vsTime > 0);
456 } else { /* SVI, slam VID */
458 msr.lo = (msr.lo & NB_VID_MASK_OFF) | (targetVid << NB_VID_POS);
460 msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (targetVid << CPU_VID_POS);
461 wrmsr(0xC0010070, msr);
463 /* read F3xD8[VSRampTime] */
464 dtemp = pci_read_config32(dev, 0xD8);
465 vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7);
466 vsTime = (int)timeTable[vsTimecode];
470 } while (vsTime > 0);
475 static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid)
480 u8 nb_cof_vid_update;
487 printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid);
489 /* Steps 1-6 of BIOS NB COF and VID Configuration
490 * for SVI and Single-Plane PVI Systems.
493 /* If any node has nb_cof_vid_update set all nodes need an update. */
495 nb_cof_vid_update = 0;
496 for (i = 0; i < nodes; i++) {
497 if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) {
498 nb_cof_vid_update = 1;
503 dev = NODE_PCI(nodeid, 3);
504 pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
505 reg1fc = pci_read_config32(dev, 0x1FC);
507 if (nb_cof_vid_update) {
509 vid_max = (reg1fc >> 7) & 0x7F;
510 fid_max = (reg1fc >> 2) & 0x1F;
512 /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */
513 fixPsNbVidBeforeWR(vid_max, coreid);
515 vid_max = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F);
516 fid_max = ((reg1fc >> 2) & 0x1F) + ((reg1fc >> 14) & 0x7);
517 transitionVid(vid_max, dev, IS_NB);
520 /* fid setup is handled by the BSP at the end. */
522 } else { /* ! nb_cof_vid_update */
525 UpdateSinglePlaneNbVid();
528 send = (nb_cof_vid_update << 16) | (fid_max << 8);
529 send |= (apicid << 24); // ap apicid
531 // Send signal to BSP about this AP max fid
532 // This also indicates this AP is ready for warm reset (if required).
533 lapic_write(LAPIC_MSG_REG, send | F10_APSTATE_RESET);
536 static u32 calc_common_fid(u32 fid_packed, u32 fid_packed_new)
541 fidmax = (fid_packed >> 8) & 0xFF;
543 fidmax_new = (fid_packed_new >> 8) & 0xFF;
545 if (fidmax > fidmax_new) {
549 fid_packed &= 0xFF << 16;
550 fid_packed |= (fidmax << 8);
551 fid_packed |= fid_packed_new & (0xFF << 16); // set nb_cof_vid_update
556 static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp)
561 struct fidvid_st *fvp = gp;
564 print_debug_fv("Wait for AP stage 1: ap_apicid = ", ap_apicid);
568 if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0)
570 if ((readback & 0x3f) == 1) {
572 break; /* target ap is in stage 1 */
577 printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n",
578 __func__, ap_apicid);
582 print_debug_fv("\treadback = ", readback);
584 fvp->common_fid = calc_common_fid(fvp->common_fid, readback);
586 print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid);
590 static void updateSviPsNbVidAfterWR(u32 newNbVid)
595 /* This function copies newNbVid to NbVid bits in P-state Registers[4:0]
599 for (i = 0; i < 5; i++) {
600 msr = rdmsr(0xC0010064 + i);
601 if ((msr.hi >> 31) & 1) { /* PstateEn? */
602 msr.lo &= ~(0x7F << 25);
603 msr.lo |= (newNbVid & 0x7F) << 25;
604 wrmsr(0xC0010064 + i, msr);
610 static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll)
616 /* This function copies newNbVid to NbVid bits in P-state
617 * Registers[4:0] if its NbDid bit=0 and PstateEn bit =1 in case of
618 * NbVidUpdatedAll =0 or copies copies newNbVid to NbVid bits in
619 * P-state Registers[4:0] if its and PstateEn bit =1 in case of
620 * NbVidUpdatedAll=1. Then transition to StartPstate.
623 /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
624 for (i = 0; i < 5; i++) {
625 msr = rdmsr(0xC0010064 + i);
626 /* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */
627 if ((((msr.lo >> 22) & 1) == 0) || NbVidUpdatedAll) {
628 msr.lo &= ~(0x7F << 25);
629 msr.lo |= (newNbVid & 0x7F) << 25;
630 wrmsr(0xC0010064 + i, msr);
634 UpdateSinglePlaneNbVid();
636 /* For each core in the system, transition all cores to StartupPstate */
637 msr = rdmsr(0xC0010071);
638 StartupPstate = msr.hi & 0x07;
639 msr = rdmsr(0xC0010062);
640 msr.lo = StartupPstate;
641 wrmsr(0xC0010062, msr);
643 /* Wait for StartupPstate to set. */
645 msr = rdmsr(0xC0010063);
646 } while (msr.lo != StartupPstate);
649 static void set_p0(void)
653 // Transition P0 for calling core.
654 msr = rdmsr(0xC0010062);
655 msr.lo = (msr.lo & ~0x07);
656 wrmsr(0xC0010062, msr);
658 /* Wait for P0 to set. */
660 msr = rdmsr(0xC0010063);
661 } while (msr.lo != 0);
664 static void finalPstateChange(void)
666 /* Enble P0 on all cores for best performance.
667 * Linux can slow them down later if need be.
668 * It is safe since they will be in C1 halt
669 * most of the time anyway.
674 static void init_fidvid_stage2(u32 apicid, u32 nodeid)
681 u8 nb_cof_vid_update;
687 /* After warm reset finish the fid/vid setup for all cores. */
689 /* If any node has nb_cof_vid_update set all nodes need an update. */
691 nb_cof_vid_update = 0;
692 for (i = 0; i < nodes; i++) {
693 if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) {
694 nb_cof_vid_update = 1;
699 dev = NODE_PCI(nodeid, 3);
700 pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
701 reg1fc = pci_read_config32(dev, 0x1FC);
702 nbvid = (reg1fc >> 7) & 0x7F;
703 NbVidUpdateAll = (reg1fc >> 1) & 1;
705 if (nb_cof_vid_update) {
707 nbvid = (reg1fc >> 7) & 0x7F;
708 /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
709 fixPsNbVidAfterWR(nbvid, NbVidUpdateAll);
711 nbvid = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F);
712 updateSviPsNbVidAfterWR(nbvid);
714 } else { /* !nb_cof_vid_update */
716 UpdateSinglePlaneNbVid();
718 dtemp = pci_read_config32(dev, 0xA0);
719 dtemp &= PLLLOCK_OFF;
720 dtemp |= PLLLOCK_DFT_L;
721 pci_write_config32(dev, 0xA0, dtemp);
725 /* Set TSC to tick at the P0 ndfid rate */
732 #if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
733 struct ap_apicid_st {
735 // it could use 256 bytes for 64 node quad core system
736 u8 apicid[NODE_NUMS * 4];
739 static void store_ap_apicid(unsigned ap_apicid, void *gp)
741 struct ap_apicid_st *p = gp;
743 p->apicid[p->num++] = ap_apicid;
749 static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
751 #if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
752 struct ap_apicid_st ap_apicidx;
759 u8 nb_cof_vid_update;
763 printk(BIOS_DEBUG, "FIDVID on BSP, APIC_id: %02x\n", bsp_apicid);
764 /* FIXME: The first half of this function is nearly the same as
765 * init_fidvid_bsp() and the code could be combined.
768 /* Steps 1-6 of BIOS NB COF and VID Configuration
769 * for SVI and Single-Plane PVI Systems.
772 /* If any node has nb_cof_vid_update set all nodes need an update. */
773 nb_cof_vid_update = 0;
774 for (i = 0; i < nodes; i++) {
775 if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) {
776 nb_cof_vid_update = 1;
781 dev = NODE_PCI(0, 3);
782 pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1;
783 reg1fc = pci_read_config32(dev, 0x1FC);
785 if (nb_cof_vid_update) {
787 vid_max = (reg1fc >> 7) & 0x7F;
788 fid_max = (reg1fc >> 2) & 0x1F;
790 /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */
791 fixPsNbVidBeforeWR(vid_max, 0);
793 vid_max = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F);
794 fid_max = ((reg1fc >> 2) & 0x1F) + ((reg1fc >> 14) & 0x7);
795 transitionVid(vid_max, dev, IS_NB);
798 /* fid setup is handled by the BSP at the end. */
800 } else { /* ! nb_cof_vid_update */
803 UpdateSinglePlaneNbVid();
806 fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8);
807 print_debug_fv("BSP fid = ", fv.common_fid);
809 #if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 && SET_FIDVID_CORE0_ONLY == 0
810 /* For all APs (We know the APIC ID of all APs even when the APIC ID
811 is lifted) remote read from AP LAPIC_MSG_REG about max fid.
812 Then calculate the common max fid that can be used for all
816 for_each_ap(bsp_apicid, SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx);
818 for (i = 0; i < ap_apicidx.num; i++) {
819 init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
822 for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
825 print_debug_fv("common_fid = ", fv.common_fid);
827 if (fv.common_fid & (1 << 16)) { /* check nb_cof_vid_update */
829 // Enable the common fid and other settings.
830 enable_fid_change((fv.common_fid >> 8) & 0x1F);
832 // nbfid change need warm reset, so reset at first
836 return 0; // No FID/VID changes. Don't reset