2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * Default MSR and errata settings.
32 } fam10_msr_default[] = {
33 { TOP_MEM2, AMD_DR_ALL, AMD_PTYPE_ALL,
34 0x00000000, 0x00000000,
35 0xFFFFFFFF, 0xFFFFFFFF },
37 { SYSCFG, AMD_DR_ALL, AMD_PTYPE_ALL,
39 3 << 21, 0x00000000 }, /* [MtrrTom2En]=1,[TOM2EnWB] = 1*/
41 { HWCR, AMD_DR_ALL, AMD_PTYPE_ALL,
43 1 << 4, 0x00000000 }, /* [INVD_WBINVD]=1 */
45 { MC4_CTL_MASK, AMD_DR_ALL, AMD_PTYPE_ALL,
46 0xF << 19, 0x00000000,
47 0xF << 19, 0x00000000 }, /* [RtryHt[0..3]]=1 */
49 { DC_CFG, AMD_DR_ALL, AMD_PTYPE_SVR,
50 0x00000000, 0x00000004,
51 0x00000000, 0x0000000C }, /* [REQ_CTR] = 1 for Server */
53 { DC_CFG, AMD_DR_Bx, AMD_PTYPE_SVR,
54 0x00000000, 0x00000000,
55 0x00000000, 0x00000C00 }, /* Errata 326 */
57 { NB_CFG, AMD_DR_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC,
59 0x00000000, 1 << 22 }, /* [ApicInitIDLo]=1 */
61 { BU_CFG2, AMD_DR_Bx, AMD_PTYPE_ALL,
63 1 << 29, 0x00000000 }, /* For Bx Smash1GPages=1 */
65 { DC_CFG, AMD_DR_ALL, AMD_PTYPE_ALL,
67 1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */
69 { LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL,
71 1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */
73 { BU_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL,
75 1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG[21]=1 */
77 { BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL,
79 1 << 23, 0x00000000 }, /* Erratum #309 BU_CFG[23]=1 */
81 /* CPUID_EXT_FEATURES */
82 { CPUIDFEATURES, AMD_DR_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC,
84 1 << 28, 0x00000000 }, /* [HyperThreadFeatEn]=1 */
86 { CPUIDFEATURES, AMD_DR_ALL, AMD_PTYPE_DC,
87 0x00000000, 1 << (33-32),
88 0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */
93 * Default PCI and errata settings.
102 } fam10_pci_default[] = {
104 /* Function 0 - HT Config */
106 { 0, 0x68, AMD_DR_ALL, AMD_PTYPE_ALL,
107 0x004E4800, 0x006E6800 }, /* [19:17] for 8bit APIC config,
108 [14:13] BufPriRel = 2h [11] RspPassPW set,
109 [22:21] DsNpReqLmt = 10b */
111 /* Errata 281 Workaround */
112 { 0, 0x68, (AMD_DR_B0 | AMD_DR_B1),
113 AMD_PTYPE_SVR, 0x00200000, 0x00600000 }, /* [22:21] DsNpReqLmt0 = 01b */
115 { 0, 0x84, AMD_DR_ALL, AMD_PTYPE_ALL,
116 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
118 { 0, 0xA4, AMD_DR_ALL, AMD_PTYPE_ALL,
119 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
121 { 0, 0xC4, AMD_DR_ALL, AMD_PTYPE_ALL,
122 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
124 { 0, 0xE4, AMD_DR_ALL, AMD_PTYPE_ALL,
125 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
127 /* Link Global Extended Control Register */
128 { 0, 0x16C, AMD_DR_ALL, AMD_PTYPE_ALL,
129 0x0000C000, 0x0000E000 }, /* [15:13] ForceFullT0 = 110b */
131 /* Function 1 - Map Init */
133 /* Before reading F1x114_x2 or F1x114_x3 software must
134 * initialize the registers or NB Array MCA errors may
135 * occur. BIOS should initialize index 0h of F1x114_x2 and
136 * F1x114_x3 to prevent reads from F1x114 from generating NB
137 * Array MCA errors. BKDG Doc #3116 Rev 1.07
140 { 1, 0x110, AMD_DR_ALL, AMD_PTYPE_ALL,
141 0x20000000, 0xFFFFFFFF }, /* Select extended MMIO Base */
143 { 1, 0x114, AMD_DR_ALL, AMD_PTYPE_ALL,
144 0x00000000, 0xFFFFFFFF }, /* Clear map */
146 { 1, 0x110, AMD_DR_ALL, AMD_PTYPE_ALL,
147 0x30000000, 0xFFFFFFFF }, /* Select extended MMIO Base */
149 { 1, 0x114, AMD_DR_ALL, AMD_PTYPE_ALL,
150 0x00000000, 0xFFFFFFFF }, /* Clear map */
152 /* Function 2 - DRAM Controller */
154 /* Function 3 - Misc. Control */
155 { 3, 0x40, AMD_DR_ALL, AMD_PTYPE_ALL,
156 0x00000100, 0x00000100 }, /* [8] MstrAbrtEn */
158 { 3, 0x44, AMD_DR_ALL, AMD_PTYPE_ALL,
159 0x4A30005C, 0x4A30005C }, /* [30] SyncOnDramAdrParErrEn = 1,
160 [27] NbMcaToMstCpuEn = 1,
161 [25] DisPciCfgCpuErrRsp = 1,
162 [21] SyncOnAnyErrEn = 1,
163 [20] SyncOnWDTEn = 1,
165 [4] SyncPktPropDis = 1,
166 [3] SyncPktGenDis = 1,
167 [2] SyncOnUcEccEn = 1 */
169 /* XBAR buffer settings */
170 { 3, 0x6C, AMD_DR_ALL, AMD_PTYPE_ALL,
171 0x00018052, 0x700780F7 },
173 /* Errata 281 Workaround */
174 { 3, 0x6C, ( AMD_DR_B0 | AMD_DR_B1),
175 AMD_PTYPE_SVR, 0x00010094, 0x700780F7 },
177 { 3, 0x6C, AMD_DR_ALL, AMD_PTYPE_UMA,
178 0x60018051, 0x700780F7 },
180 { 3, 0x70, AMD_DR_ALL, AMD_PTYPE_ALL,
181 0x00041153, 0x777777F7 },
183 { 3, 0x70, AMD_DR_ALL, AMD_PTYPE_UMA,
184 0x61221151, 0x777777F7 },
186 { 3, 0x74, AMD_DR_ALL, AMD_PTYPE_UMA,
187 0x00080101, 0x000F7777 },
189 { 3, 0x7C, AMD_DR_ALL, AMD_PTYPE_ALL,
190 0x00090914, 0x707FFF1F },
192 /* Errata 281 Workaround */
193 { 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1),
194 AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F },
196 { 3, 0x7C, AMD_DR_ALL, AMD_PTYPE_UMA,
197 0x00070814, 0x007FFF1F },
199 { 3, 0x140, AMD_DR_ALL, AMD_PTYPE_ALL,
200 0x00800756, 0x00F3FFFF },
202 { 3, 0x140, AMD_DR_ALL, AMD_PTYPE_UMA,
203 0x00C37756, 0x00F3FFFF },
205 { 3, 0x144, AMD_DR_ALL, AMD_PTYPE_UMA,
206 0x00000036, 0x000000FF },
208 /* Errata 281 Workaround */
209 { 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1),
210 AMD_PTYPE_SVR, 0x00000001, 0x0000000F },
211 /* [3:0] RspTok = 0001b */
213 { 3, 0x148, AMD_DR_ALL, AMD_PTYPE_UMA,
214 0x8000052A, 0xD5FFFFFF },
216 /* ACPI Power State Control Reg1 */
217 { 3, 0x80, AMD_DR_ALL, AMD_PTYPE_ALL,
218 0xE6002200, 0xFFFFFFFF },
220 /* ACPI Power State Control Reg2 */
221 { 3, 0x84, AMD_DR_ALL, AMD_PTYPE_ALL,
222 0xA0E641E6, 0xFFFFFFFF },
224 { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK,
225 0x00000080, 0x00000080 }, /* [7] PSIVidEnable */
227 { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_ALL,
228 0x00001800, 0x000003800 }, /* [13:11] PllLockTime = 3 */
230 /* Reported Temp Control Register */
231 { 3, 0xA4, AMD_DR_ALL, AMD_PTYPE_ALL,
232 0x00000080, 0x00000080 }, /* [7] TempSlewDnEn = 1 */
234 /* Clock Power/Timing Control 0 Register */
235 { 3, 0xD4, AMD_DR_ALL, AMD_PTYPE_ALL,
236 0xC0000F00, 0xF0000F00 }, /* [31] NbClkDivApplyAll = 1,
237 [30:28] NbClkDiv = 100b,[11:8] ClkRampHystSel = 1111b */
239 /* Clock Power/Timing Control 1 Register */
240 { 3, 0xD8, AMD_DR_ALL, AMD_PTYPE_ALL,
241 0x03000016, 0x0F000077 }, /* [6:4] VSRampTime = 1,
242 [2:0] VSSlamTime = 6, [27:24] ReConDel = 3 */
245 /* Clock Power/Timing Control 2 Register */
246 { 3, 0xDC, AMD_DR_ALL, AMD_PTYPE_ALL,
247 0x00005000, 0x00007000 }, /* [14:12] NbsynPtrAdj = 5 */
250 /* Extended NB MCA Config Register */
251 { 3, 0x180, AMD_DR_ALL, AMD_PTYPE_ALL,
252 0x007003E2, 0x007003E2 }, /* [22:20] = SyncFloodOn_Err = 7,
253 [9] SyncOnUncNbAryEn = 1 ,
254 [8] SyncOnProtEn = 1,
255 [7] SyncFloodOnTgtAbtErr = 1,
256 [6] SyncFloodOnDatErr = 1,
257 [5] DisPciCfgCpuMstAbtRsp = 1,
258 [1] SyncFloodOnUsPwDataErr = 1 */
260 /* L3 Control Register */
261 { 3, 0x1B8, AMD_DR_ALL, AMD_PTYPE_ALL,
262 0x00001000, 0x00001000 }, /* [12] = L3PrivReplEn */
264 /* IBS Control Register */
265 { 3, 0x1CC, AMD_DR_ALL, AMD_PTYPE_ALL,
266 0x00000100, 0x00000100 }, /* [8] = LvtOffsetVal */
271 * Default HyperTransport Phy and errata settings.
273 static const struct {
274 u16 htreg; /* HT Phy Register index */
280 } fam10_htphy_default[] = {
282 { 0x520A, AMD_DR_Bx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
283 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */
285 { 0x530A, AMD_DR_Bx, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
286 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */
288 { 0xCF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
289 0x00000000, 0x000000FF }, /* Provide clear setting for logical
292 { 0xDF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
293 0x00000000, 0x000000FF }, /* Provide clear setting for logical
296 { 0xCF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
297 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
299 { 0xDF, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
300 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
302 /* Link Phy Receiver Loop Filter Registers */
303 { 0xD1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
304 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
305 [21:14] LfcMin = 10h */
307 { 0xC1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
308 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
309 [21:14] LfcMin = 10h */
311 { 0xD1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
312 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
313 [21:14] LfcMin = 08h */
315 { 0xC1, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
316 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
317 [21:14] LfcMin = 08h */