2 * 2006.3 yhlu add copy data from CAR to ram
4 #include "cpu/amd/car/disable_cache_as_ram.c"
6 #include "cpu/amd/car/clear_init_ram.c"
8 static inline void print_debug_pcar(const char *strval, uint32_t val)
10 printk_debug("%s%08x\r\n", strval, val);
13 static void inline __attribute__((always_inline)) memcopy(void *dest, const void *src, unsigned long bytes)
19 : "S" (src), "D" (dest), "c" ((bytes)>>2)
22 /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 */
24 static void vErrata343(void)
28 unsigned int uiMask = 0xFFFFFFF7;
30 msr = rdmsr(BU_CFG2_MSR);
31 msr.hi &= uiMask; // set bit 35 to 0
32 wrmsr(BU_CFG2_MSR, msr);
36 static void post_cache_as_ram(void)
41 /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
47 print_debug_pcar("v_esp=", v_esp);
51 unsigned testx = 0x5a5a5a5a;
52 print_debug_pcar("testx = ", testx);
54 /* copy data from cache as ram to
55 ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead.
57 #if CONFIG_RAMTOP <= 0x100000
58 #error "You need to set CONFIG_RAMTOP greater than 1M"
61 set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_RAMTOP) */
63 // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00);
64 print_debug("Copying data from cache to RAM -- switching to use RAM as stack... ");
66 /* from here don't store more data in CAR */
75 memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
76 // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
79 /* set new esp */ /* before CONFIG_RAMBASE */
82 ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
83 ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp
91 /* We can put data to stack again */
93 /* only global variable sysinfo in cache need to be offset */
94 print_debug("Done\r\n");
95 print_debug_pcar("testx = ", testx);
97 print_debug("Disabling cache as ram now \r\n");
98 disable_cache_as_ram_bsp();
100 print_debug("Clearing initial memory region: ");
101 clear_init_ram(); //except the range from [(CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_RAMTOP))
102 print_debug("Done\r\n");
104 // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
106 set_sysinfo_in_ram(1); // So other core0 could start to train mem
108 #if CONFIG_MEM_TRAIN_SEQ == 1
109 // struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
111 // wait for ap memory to trained
112 // wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
114 /*copy and execute coreboot_ram */
116 /* We will not return */
118 print_debug("should not be here -\r\n");