11 * Bootstrap code for the STPC Consumer
12 * Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
16 * Written by Johan Rydberg, based on work by Daniel Kahlin.
17 * Rewritten by Eric Biederman
18 * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
21 * We use ELF as output format. So that we can
22 * debug the code in some form.
32 * First we place the code and read only data (typically const declared).
33 * This get placed in rom.
46 *(.rodata.console_drivers)
47 econsole_drivers = . ;
58 * kevinh/Ispiri - Added an align, because the objcopy tool
59 * incorrectly converts sections that are not long word aligned.
60 * This breaks the coreboot.rom target.
67 * After the code we place initialized data (typically initialized
68 * global variables). This gets copied into ram by startup code.
69 * __data_start and __data_end shows where in ram this should be placed,
70 * whereas __data_loadstart and __data_loadend shows where in rom to
90 * bss does not contain data, it is just a space that should be zero
91 * initialized on startup. (typically uninitialized global variables)
92 * crt0.S fills between _bss and _ebss with zeroes.
102 . = ALIGN(CONFIG_STACK_SIZE);
105 /* Reserve a stack for each possible cpu */
106 /* the stack for ap will be put after pgtbl in 1M to CONFIG_RAMTOP range when VGA and ROM_RUN and CONFIG_RAMTOP>1M*/
107 . = ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_RAMTOP>0x100000) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE);
112 /* Reserve CONFIG_HEAP_SIZE bytes for the heap */
113 . = CONFIG_HEAP_SIZE ;
118 * This is all address of the memory resident copy of coreboot.
123 _bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "please increase CONFIG_RAMTOP");
125 _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_RAMTOP and if still fail, try to set CONFIG_RAMBASE more than 1M");