1 #######################################################
3 # Main options file for coreboot
5 # Each option used by a part must be defined in
6 # this file. The format for options is:
9 # default <expr> | {<expr>} | "<string>" | none
11 # export always | used | never
17 # <name> is the name of the option
18 # <expr> is a numeric expression
19 # <string> is a string
21 # Either a default value or 'default none' must
22 # be specified for every option. An option
23 # specified as 'default none' will not be exported
24 # (i.e. will remain undefined) unless it has
25 # been assigned a value.
27 # Option values can be an immediate expression that
28 # evaluates to a numeric value, a delayed expression
29 # (surrounded by curley braces), or a string
30 # (surrounded by double quotes.)
32 # Immediate expressions are evaluated at the time an
33 # option is defined or set and the numeric result
34 # becomes the value of the option.
36 # Delayed expression are evaluated at the time the
37 # option is used, either in another expression or
38 # when being exported.
40 # String values will have the double quotes removed
43 # Format strings determine the print format that is
44 # used when exporting options. The default format
45 # is "%s" for strings and "%d" for numbers.
47 # Exported options generate entries in the
48 # Makefile.settings file. Options can be always
49 # exported, exported only if used, or never exported.
51 # A comment string must be supplied for every option.
53 #######################################################
55 ###############################################
56 # Architecture options
57 ###############################################
62 comment "Default architecture is i386, options are alpha and ppc"
67 comment "This cpu supports the MOVNTI directive"
70 ###############################################
72 ###############################################
77 comment "Cross compiler prefix"
80 default "$(CROSS_COMPILE)gcc"
82 comment "Target C Compiler"
87 comment "Host C Compiler"
92 comment "Additional per-cpu CFLAGS"
95 default "$(CROSS_COMPILE)objcopy --gap-fill 0xff"
97 comment "Objcopy command"
99 define COREBOOT_VERSION
103 comment "coreboot version"
105 define COREBOOT_EXTRA_VERSION
109 comment "coreboot extra version"
111 define COREBOOT_BUILD
112 default "$(shell date)"
117 define COREBOOT_COMPILE_TIME
118 default "$(shell date +%T)"
123 define COREBOOT_COMPILE_BY
124 default "$(shell whoami)"
127 comment "Who build this image"
129 define COREBOOT_COMPILE_HOST
130 default "$(shell hostname)"
136 define COREBOOT_COMPILE_DOMAIN
137 default "$(shell dnsdomainname)"
140 comment "Build domain name"
142 define COREBOOT_COMPILER
143 default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -n 1)"
146 comment "Build compiler"
148 define COREBOOT_LINKER
149 default "$(shell $(CC) -Wl,--version 2>&1 | grep version | tail -n 1)"
152 comment "Build linker"
154 define COREBOOT_ASSEMBLER
155 default "$(shell touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"
158 comment "Build assembler"
160 define CONFIG_CHIP_CONFIGURE
163 comment "Use new chip_configure method for configuring (non-pci) devices"
165 define CONFIG_USE_INIT
168 comment "Use stage 1 initialization code"
174 comment "This is used by code to determine v2 vs v3"
177 ###############################################
179 ###############################################
181 define HAVE_FALLBACK_BOOT
185 comment "Set if fallback booting required"
187 define HAVE_FAILOVER_BOOT
191 comment "Set if failover booting required"
193 define USE_FALLBACK_IMAGE
197 comment "Set to build a fallback image"
199 define USE_FAILOVER_IMAGE
203 comment "Set to build a failover image"
209 comment "Default fallback image size"
215 comment "Default failover image size"
221 comment "Size of your ROM"
223 define ROM_IMAGE_SIZE
227 comment "Default image size"
229 define ROM_SECTION_SIZE
230 default {FALLBACK_SIZE}
233 comment "Default rom section size"
235 define ROM_SECTION_OFFSET
236 default {ROM_SIZE - FALLBACK_SIZE}
239 comment "Default rom section offset"
242 default {ROM_SECTION_SIZE - ROM_IMAGE_SIZE}
245 comment "Default payload size"
248 default {PAYLOAD_SIZE}
251 comment "Base address of coreboot in ROM"
257 comment "Start address of coreboot in ROM"
263 comment "Hardware reset vector address"
265 define _EXCEPTION_VECTORS
266 default {_ROMBASE+0x100}
269 comment "Address of exception vector table"
275 comment "Default stack size"
281 comment "Default heap size"
287 comment "Base address of coreboot in RAM"
293 comment "Start address of coreboot in RAM"
295 define USE_DCACHE_RAM
298 comment "Use data cache as temporary RAM if possible"
303 comment "AMD family 10 CAR requires additional setup"
305 define DCACHE_RAM_BASE
309 comment "Base address of data cache when using it for temporary RAM"
311 define DCACHE_RAM_SIZE
315 comment "Size of data cache when using it for temporary RAM"
317 define DCACHE_RAM_GLOBAL_VAR_SIZE
321 comment "Size of region that for global variable of cache as ram stage"
323 define CONFIG_AP_CODE_IN_CAR
326 comment "will copy coreboot_apc to AP cache ane execute in AP"
331 comment "0: three for in bsp, 1: on every core0, 2: one for on bsp"
333 define WAIT_BEFORE_CPUS_INIT
336 comment "execute cpus_ready_for_init if it is set to 1"
342 comment "Start address of area to cache during coreboot execution directly from ROM"
348 comment "Size of area to cache during coreboot execution directly from ROM"
350 define CONFIG_COMPRESS
353 comment "Set for compressed image"
355 define CONFIG_UNCOMPRESSED
357 default {!CONFIG_COMPRESS}
359 comment "Set for uncompressed image"
361 define CONFIG_LB_MEM_TOPK
365 comment "Kilobytes of memory to initialized before executing code from RAM"
367 define HAVE_OPTION_TABLE
370 comment "Export CMOS option table"
372 define USE_OPTION_TABLE
374 default {HAVE_OPTION_TABLE && !USE_FALLBACK_IMAGE}
376 comment "Use option table"
379 ###############################################
380 # CMOS variable options
381 ###############################################
382 define LB_CKS_RANGE_START
386 comment "First CMOS byte to use for coreboot options"
388 define LB_CKS_RANGE_END
392 comment "Last CMOS byte to use for coreboot options"
398 comment "Pair of bytes to use for CMOS checksum"
402 ###############################################
404 ###############################################
407 default "$(TOP)/src/arch/$(ARCH)/init/crt0.S.lb"
409 comment "Main initialization target"
412 ###############################################
413 # Debugging/Logging options
414 ###############################################
419 comment "Enable x86emu debugging code"
421 define CONFIG_CONSOLE_VGA
424 comment "Log messages to any VGA-compatible device (may require *_ROM_RUN to bring up)"
426 define CONFIG_CONSOLE_VGA_MULTI
429 comment "Multi VGA console"
431 define CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
434 comment "Use onboard VGA instead of add on VGA card"
436 define CONFIG_CONSOLE_BTEXT
439 comment "Log messages to btext fb console"
441 define CONFIG_CONSOLE_LOGBUF
444 comment "Log messages to buffer"
446 define CONFIG_CONSOLE_SROM
449 comment "Log messages to SROM console"
451 define CONFIG_CONSOLE_SERIAL8250
454 comment "Log messages to 8250 uart based serial console"
456 define CONFIG_USBDEBUG_DIRECT
459 comment "Log messages to ehci debug port console"
461 define DEFAULT_CONSOLE_LOGLEVEL
464 comment "Console will log at this level unless changed"
466 define MAXIMUM_CONSOLE_LOGLEVEL
469 comment "Error messages up to this level can be printed"
471 define CONFIG_SERIAL_POST
474 comment "Enable SERIAL POST codes"
479 comment "Disable POST codes"
485 comment "Base address for 8250 uart for the serial console"
490 comment "Default baud rate for serial console"
496 comment "Allow UART divisor to be set explicitly"
502 comment "Default flow control settings for the 8250 serial console uart"
505 define CONFIG_USE_PRINTK_IN_CAR
508 comment "use printk instead of print in CAR stage code"
510 define ASSEMBLER_DEBUG
513 comment "Create disassembly files for debugging"
516 ###############################################
518 ###############################################
521 default "Mainboard_not_set"
523 comment "Mainboard name"
525 define MAINBOARD_PART_NUMBER
526 default "Part_number_not_set"
529 comment "Part number of mainboard"
531 define MAINBOARD_VENDOR
532 default "Vendor_not_set"
535 comment "Vendor of mainboard"
537 define MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
540 comment "PCI Vendor ID of mainboard manufacturer"
542 define MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
546 comment "PCI susbsystem device id assigned my mainboard manufacturer"
548 define MAINBOARD_POWER_ON_AFTER_POWER_FAIL
551 comment "Default power on after power fail setting"
553 define CONFIG_SYS_CLK_FREQ
556 comment "System clock frequency in MHz"
558 define CONFIG_MAX_PCI_BUSES
561 comment "Maximum number of PCI buses to search for devices"
563 ###############################################
565 ###############################################
570 comment "Define if we support SMP"
572 define CONFIG_MAX_CPUS
575 comment "Maximum CPU count for this machine"
577 define CONFIG_MAX_PHYSICAL_CPUS
580 comment "Maximum physical CPU count for this machine"
582 define CONFIG_LOGICAL_CPUS
585 comment "Should multiple cpus per die be enabled?"
587 define CONFIG_AP_IN_SIPI_WAIT
590 comment "Should application processors go to SIPI wait state after initialization? (Required for Intel Core Duo)"
595 comment "Define to build an MP table"
597 define SERIAL_CPU_INIT
600 comment "Serialize CPU init"
602 define APIC_ID_OFFSET
605 comment "We need to share this value between cache_as_ram_auto.c and northbridge.c"
607 define ENABLE_APIC_EXT_ID
610 comment "Enable APIC ext id mode 8 bit"
612 define LIFT_BSP_APIC_ID
615 comment "decide if we lift bsp apic id while ap apic id"
617 ###############################################
619 ###############################################
621 define CONFIG_MULTIBOOT
624 comment "Use Multiboot (rather than ELF boot notes) to boot the payload"
626 define CONFIG_IDE_PAYLOAD
629 comment "Boot from IDE device"
631 define CONFIG_ROM_PAYLOAD
634 comment "Boot image is located in ROM"
636 define CONFIG_ROM_PAYLOAD_START
637 default {0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1}
640 comment "ROM stream start location"
642 define CONFIG_COMPRESSED_PAYLOAD_NRV2B
645 comment "NRV2B compressed boot image is located in ROM"
647 define CONFIG_COMPRESSED_PAYLOAD_LZMA
650 comment "LZMA compressed boot image is located in ROM"
652 define CONFIG_PRECOMPRESSED_PAYLOAD
655 comment "boot image is already compressed"
657 define CONFIG_SERIAL_PAYLOAD
660 comment "Download boot image from serial port"
662 define CONFIG_FS_PAYLOAD
665 comment "Boot from a filesystem"
667 define CONFIG_FS_EXT2
670 comment "Enable ext2 filesystem support"
672 define CONFIG_FS_ISO9660
675 comment "Enable ISO9660 filesystem support"
680 comment "Enable FAT filesystem support"
682 define AUTOBOOT_DELAY
685 comment "Delay (in seconds) before autobooting"
687 define AUTOBOOT_CMDLINE
688 default "hdc1:/vmlinuz root=/dev/hdc3 console=tty0 console=ttyS0,115200"
691 comment "Default command line when autobooting"
694 define USE_WATCHDOG_ON_BOOT
697 comment "Use the watchdog on booting"
700 ###############################################
701 # Plugin Device support options
702 ###############################################
704 define CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
707 comment "Enable support for plugin Hypertransport busses"
709 define CONFIG_AGP_PLUGIN_SUPPORT
712 comment "Enable support for plugin AGP busses"
714 define CONFIG_CARDBUS_PLUGIN_SUPPORT
717 comment "Enable support cardbus plugin cards"
719 define CONFIG_PCIX_PLUGIN_SUPPORT
722 comment "Enable support for plugin PCI-X busses"
724 define CONFIG_PCIEXP_PLUGIN_SUPPORT
727 comment "Enable support for plugin PCI-E busses"
730 ###############################################
732 ###############################################
734 define HAVE_PIRQ_TABLE
737 comment "Define if we have a PIRQ table"
742 comment "Define if we have a PIRQ table and want routing IRQs"
744 define IRQ_SLOT_COUNT
747 comment "Number of IRQ slots"
749 define CONFIG_PCIBIOS_IRQ
752 comment "PCIBIOS IRQ support"
757 comment "IOAPIC support"
760 ###############################################
761 # IDE specific options
762 ###############################################
767 comment "Define to include IDE support"
769 define IDE_BOOT_DRIVE
772 comment "Disk number of boot drive"
777 comment "Swap bytes when reading from IDE device"
782 comment "Sector at which to start searching for boot image"
785 ###############################################
786 # Options for memory mapped I/O
787 ###############################################
789 define PCI_IO_CFG_EXT
792 comment "allow 4K register space via io CFG port"
799 comment "Address of PCI Configuration Address Register"
805 comment "Address of PCI Configuration Data Register"
811 comment "Base address of PCI/ISA I/O address range"
817 comment "Base address of PCI/ISA memory address range"
823 comment "PNP Configuration Address Register offset"
829 comment "PNP Configuration Data Register offset"
835 comment "Base address of memory mapped I/O operations"
838 ###############################################
839 # Options for embedded systems
840 ###############################################
842 define EMBEDDED_RAM_SIZE
845 comment "Embedded boards generally have fixed RAM size"
848 ###############################################
850 ###############################################
852 define CONFIG_CHIP_NAME
855 comment "Compile in the chip name"
858 define CONFIG_GDB_STUB
861 comment "Compile in gdb stub support?"
864 define HAVE_INIT_TIMER
867 comment "Have a init_timer function"
869 define HAVE_HARD_RESET
872 comment "Have hard reset"
874 define HAVE_SMI_HANDLER
877 comment "Set, if the board needs an SMI handler"
882 comment "Set to deal with memory hole"
884 define MAX_REBOOT_CNT
887 comment "Set maximum reboots"
890 ###############################################
891 # Misc device options
892 ###############################################
897 comment "Include board specific FAN control initialization"
899 define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
902 comment "Use timer2 to callibrate the x86 time stamp counter"
904 define INTEL_PPRO_MTRR
909 define CONFIG_UDELAY_TSC
912 comment "Implement udelay with the x86 time stamp counter"
914 define CONFIG_UDELAY_IO
917 comment "Implement udelay with x86 io registers"
922 comment "Use this to fake spd rom values"
925 define HAVE_ACPI_TABLES
928 comment "Define to build ACPI tables"
931 define ACPI_SSDTX_NUM
934 comment "extra ssdt num for PCI Device"
937 define AGP_APERTURE_SIZE
941 comment "AGP graphics virtual memory aperture size"
944 define HT_CHAIN_UNITID_BASE
947 comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
950 define HT_CHAIN_END_UNITID_BASE
953 comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than HT_CHAIN_UNITID_BASE, it could be 0"
956 define SB_HT_CHAIN_UNITID_OFFSET_ONLY
959 comment "this will decided if only offset SB hypertransport chain"
962 define SB_HT_CHAIN_ON_BUS0
965 comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
968 define PCI_BUS_SEGN_BITS
971 comment "It could be 0, 1, 2, 3 and 4 only"
974 define MMCONF_SUPPORT
977 comment "enable mmconfig for pci conf"
980 define MMCONF_SUPPORT_DEFAULT
983 comment "enable mmconfig for pci conf"
986 define HW_MEM_HOLE_SIZEK
989 comment "Opteron E0 later memory hole size in K, 0 mean disable"
992 define HW_MEM_HOLE_SIZE_AUTO_INC
995 comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
998 define CONFIG_VAR_MTRR_HOLE
1001 comment "using hole in MTRR instead of increasing method"
1004 define K8_HT_FREQ_1G_SUPPORT
1007 comment "Optern E0 later could support 1G HT, but still depends MB design"
1010 define K8_REV_F_SUPPORT
1013 comment "Opteron Rev F (DDR2) support"
1019 comment "Opteron cpu bus num base"
1025 comment "Opteron cpu device num base"
1031 comment "Hypertransport 3 support, include ac HT and unganged sublink feature"
1034 define EXT_RT_TBL_SUPPORT
1037 comment "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8"
1040 define EXT_CONF_SUPPORT
1043 comment "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4"
1050 comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg"
1053 define CPU_SOCKET_TYPE
1056 comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
1059 define CPU_ADDR_BITS
1062 comment "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48"
1065 define CONFIG_VGA_ROM_RUN
1068 comment "Init x86 ROMs on VGA-class PCI devices"
1071 define CONFIG_PCI_ROM_RUN
1074 comment "Init x86 ROMs on all PCI devices"
1077 define CONFIG_PCI_OPTION_ROM_RUN_YABEL
1080 comment "Use Yabel instead of old bios emulator"
1083 define CONFIG_PCI_OPTION_ROM_RUN_VM86
1086 comment "Use Yabel instead of old bios emulator"
1089 define CONFIG_PCI_64BIT_PREF_MEM
1092 comment "allow PCI device get 4G above Region as pref mem"
1095 define CONFIG_AMDMCT
1098 comment "use AMD MCT to init RAM instead of native code"
1101 define AMD_UCODE_PATCH_FILE
1105 comment "name of the microcode patch file"
1108 define K8_MEM_BANK_B_ONLY
1111 comment "use AMD K8's memory bank B only to make a 64bit memory system and memory bank A is free, such as Filbert."
1114 define CONFIG_VIDEO_MB
1117 comment "Integrated graphics with UMA has dynamic setup"
1120 define CONFIG_GFXUMA
1126 define HAVE_MAINBOARD_RESOURCES
1129 comment "Enable if the mainboard/chipset requires extra entries in the memory map"
1132 define HAVE_LOW_TABLES
1135 comment "Enable if ACPI, PIRQ, MP tables are supposed to live in the low megabyte"
1138 define HAVE_HIGH_TABLES
1141 comment "Enable if ACPI, PIRQ, MP tables are supposed to live at top of memory"
1144 define CONFIG_SPLASH_GRAPHIC
1147 comment "Paint a splash screen"
1150 define CONFIG_GX1_VIDEO
1153 comment "Build in GX1's graphic support"
1156 define CONFIG_GX1_VIDEOMODE
1159 comment "Define video mode after reset"
1168 define CONFIG_PCIE_CONFIGSPACE_HOLE
1171 comment "Leave a hole for PCIe config space in the device allocator"
1174 ###############################################
1175 # Board specific options
1176 ###############################################
1178 ###############################################
1179 # Options for motorola/sandpoint
1180 ###############################################
1181 define CONFIG_SANDPOINT_ALTIMUS
1184 comment "Configure Sandpoint with Altimus PMC"
1186 define CONFIG_SANDPOINT_TALUS
1189 comment "Configure Sandpoint with Talus PMC"
1191 define CONFIG_SANDPOINT_UNITY
1194 comment "Configure Sandpoint with Unity PMC"
1196 define CONFIG_SANDPOINT_VALIS
1199 comment "Configure Sandpoint with Valis PMC"
1201 define CONFIG_SANDPOINT_GYRUS
1204 comment "Configure Sandpoint with Gyrus PMC"
1207 ###############################################
1208 # Options for totalimpact/briq
1209 ###############################################
1210 define CONFIG_BRIQ_750FX
1213 comment "Configure briQ with PowerPC 750FX"
1215 define CONFIG_BRIQ_7400
1218 comment "Configure briQ with PowerPC G4"