1 #######################################################
3 # Main options file for coreboot
5 # Each option used by a part must be defined in
6 # this file. The format for options is:
9 # default <expr> | {<expr>} | "<string>" | none
11 # export always | used | never
17 # <name> is the name of the option
18 # <expr> is a numeric expression
19 # <string> is a string
21 # Either a default value or 'default none' must
22 # be specified for every option. An option
23 # specified as 'default none' will not be exported
24 # (i.e. will remain undefined) unless it has
25 # been assigned a value.
27 # Option values can be an immediate expression that
28 # evaluates to a numeric value, a delayed expression
29 # (surrounded by curley braces), or a string
30 # (surrounded by double quotes.)
32 # Immediate expressions are evaluated at the time an
33 # option is defined or set and the numeric result
34 # becomes the value of the option.
36 # Delayed expression are evaluated at the time the
37 # option is used, either in another expression or
38 # when being exported.
40 # String values will have the double quotes removed
43 # Format strings determine the print format that is
44 # used when exporting options. The default format
45 # is "%s" for strings and "%d" for numbers.
47 # Exported options generate entries in the
48 # Makefile.settings file. Options can be always
49 # exported, exported only if used, or never exported.
51 # A comment string must be supplied for every option.
53 #######################################################
55 ###############################################
56 # Architecture options
57 ###############################################
62 comment "Default architecture is i386, options are alpha and ppc"
67 comment "This cpu supports the MOVNTI directive"
70 ###############################################
72 ###############################################
77 comment "Cross compiler prefix"
80 default "$(CROSS_COMPILE)gcc"
82 comment "Target C Compiler"
87 comment "Host C Compiler"
92 comment "Additional per-cpu CFLAGS"
95 default "$(CROSS_COMPILE)objcopy --gap-fill 0xff"
97 comment "Objcopy command"
99 define COREBOOT_VERSION
103 comment "coreboot version"
105 define COREBOOT_EXTRA_VERSION
109 comment "coreboot extra version"
111 define COREBOOT_BUILD
112 default "$(shell date)"
117 define COREBOOT_COMPILE_TIME
118 default "$(shell date +%T)"
123 define COREBOOT_COMPILE_BY
124 default "$(shell whoami)"
127 comment "Who build this image"
129 define COREBOOT_COMPILE_HOST
130 default "$(shell hostname)"
136 define COREBOOT_COMPILE_DOMAIN
137 default "$(shell dnsdomainname)"
140 comment "Build domain name"
142 define COREBOOT_COMPILER
143 default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -n 1)"
146 comment "Build compiler"
148 define COREBOOT_LINKER
149 default "$(shell $(CC) -Wl,--version 2>&1 | grep version | tail -n 1)"
152 comment "Build linker"
154 define COREBOOT_ASSEMBLER
155 default "$(shell touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"
158 comment "Build assembler"
160 define CONFIG_CHIP_CONFIGURE
163 comment "Use new chip_configure method for configuring (non-pci) devices"
165 define CONFIG_USE_INIT
168 comment "Use stage 1 initialization code"
171 ###############################################
173 ###############################################
175 define HAVE_FALLBACK_BOOT
179 comment "Set if fallback booting required"
181 define HAVE_FAILOVER_BOOT
185 comment "Set if failover booting required"
187 define USE_FALLBACK_IMAGE
191 comment "Set to build a fallback image"
193 define USE_FAILOVER_IMAGE
197 comment "Set to build a failover image"
203 comment "Default fallback image size"
209 comment "Default failover image size"
215 comment "Size of your ROM"
217 define ROM_IMAGE_SIZE
221 comment "Default image size"
223 define ROM_SECTION_SIZE
224 default {FALLBACK_SIZE}
227 comment "Default rom section size"
229 define ROM_SECTION_OFFSET
230 default {ROM_SIZE - FALLBACK_SIZE}
233 comment "Default rom section offset"
236 default {ROM_SECTION_SIZE - ROM_IMAGE_SIZE}
239 comment "Default payload size"
242 default {PAYLOAD_SIZE}
245 comment "Base address of coreboot in ROM"
251 comment "Start address of coreboot in ROM"
257 comment "Hardware reset vector address"
259 define _EXCEPTION_VECTORS
260 default {_ROMBASE+0x100}
263 comment "Address of exception vector table"
269 comment "Default stack size"
275 comment "Default heap size"
281 comment "Base address of coreboot in RAM"
287 comment "Start address of coreboot in RAM"
289 define USE_DCACHE_RAM
292 comment "Use data cache as temporary RAM if possible"
297 comment "AMD family 10 CAR requires additional setup"
299 define DCACHE_RAM_BASE
303 comment "Base address of data cache when using it for temporary RAM"
305 define DCACHE_RAM_SIZE
309 comment "Size of data cache when using it for temporary RAM"
311 define DCACHE_RAM_GLOBAL_VAR_SIZE
315 comment "Size of region that for global variable of cache as ram stage"
317 define CONFIG_AP_CODE_IN_CAR
320 comment "will copy coreboot_apc to AP cache ane execute in AP"
325 comment "0: three for in bsp, 1: on every core0, 2: one for on bsp"
327 define WAIT_BEFORE_CPUS_INIT
330 comment "execute cpus_ready_for_init if it is set to 1"
336 comment "Start address of area to cache during coreboot execution directly from ROM"
342 comment "Size of area to cache during coreboot execution directly from ROM"
344 define CONFIG_COMPRESS
347 comment "Set for compressed image"
349 define CONFIG_UNCOMPRESSED
351 default {!CONFIG_COMPRESS}
353 comment "Set for uncompressed image"
355 define CONFIG_LB_MEM_TOPK
359 comment "Kilobytes of memory to initialized before executing code from RAM"
361 define HAVE_OPTION_TABLE
364 comment "Export CMOS option table"
366 define USE_OPTION_TABLE
368 default {HAVE_OPTION_TABLE && !USE_FALLBACK_IMAGE}
370 comment "Use option table"
373 ###############################################
374 # CMOS variable options
375 ###############################################
376 define LB_CKS_RANGE_START
380 comment "First CMOS byte to use for coreboot options"
382 define LB_CKS_RANGE_END
386 comment "Last CMOS byte to use for coreboot options"
392 comment "Pair of bytes to use for CMOS checksum"
396 ###############################################
398 ###############################################
401 default "$(TOP)/src/arch/$(ARCH)/init/crt0.S.lb"
403 comment "Main initialization target"
406 ###############################################
407 # Debugging/Logging options
408 ###############################################
413 comment "Enable debugging code"
415 define CONFIG_CONSOLE_VGA
418 comment "Log messages to any VGA-compatible device (may require *_ROM_RUN to bring up)"
420 define CONFIG_CONSOLE_VGA_MULTI
423 comment "Multi VGA console"
425 define CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
428 comment "Use onboard VGA instead of add on VGA card"
430 define CONFIG_CONSOLE_BTEXT
433 comment "Log messages to btext fb console"
435 define CONFIG_CONSOLE_LOGBUF
438 comment "Log messages to buffer"
440 define CONFIG_CONSOLE_SROM
443 comment "Log messages to SROM console"
445 define CONFIG_CONSOLE_SERIAL8250
448 comment "Log messages to 8250 uart based serial console"
450 define CONFIG_USBDEBUG_DIRECT
453 comment "Log messages to ehci debug port console"
455 define DEFAULT_CONSOLE_LOGLEVEL
458 comment "Console will log at this level unless changed"
460 define MAXIMUM_CONSOLE_LOGLEVEL
463 comment "Error messages up to this level can be printed"
465 define CONFIG_SERIAL_POST
468 comment "Enable SERIAL POST codes"
473 comment "Disable POST codes"
479 comment "Base address for 8250 uart for the serial console"
484 comment "Default baud rate for serial console"
490 comment "Allow UART divisor to be set explicitly"
496 comment "Default flow control settings for the 8250 serial console uart"
499 define CONFIG_USE_PRINTK_IN_CAR
502 comment "use printk instead of print in CAR stage code"
506 ###############################################
508 ###############################################
511 default "Mainboard_not_set"
513 comment "Mainboard name"
515 define MAINBOARD_PART_NUMBER
516 default "Part_number_not_set"
519 comment "Part number of mainboard"
521 define MAINBOARD_VENDOR
522 default "Vendor_not_set"
525 comment "Vendor of mainboard"
527 define MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
530 comment "PCI Vendor ID of mainboard manufacturer"
532 define MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
536 comment "PCI susbsystem device id assigned my mainboard manufacturer"
538 define MAINBOARD_POWER_ON_AFTER_POWER_FAIL
541 comment "Default power on after power fail setting"
543 define CONFIG_SYS_CLK_FREQ
546 comment "System clock frequency in MHz"
548 define CONFIG_MAX_PCI_BUSES
551 comment "Maximum number of PCI buses to search for devices"
553 ###############################################
555 ###############################################
560 comment "Define if we support SMP"
562 define CONFIG_MAX_CPUS
565 comment "Maximum CPU count for this machine"
567 define CONFIG_MAX_PHYSICAL_CPUS
570 comment "Maximum physical CPU count for this machine"
572 define CONFIG_LOGICAL_CPUS
575 comment "Should multiple cpus per die be enabled?"
580 comment "Define to build an MP table"
582 define SERIAL_CPU_INIT
585 comment "Serialize CPU init"
587 define APIC_ID_OFFSET
590 comment "We need to share this value between cache_as_ram_auto.c and northbridge.c"
592 define ENABLE_APIC_EXT_ID
595 comment "Enable APIC ext id mode 8 bit"
597 define LIFT_BSP_APIC_ID
600 comment "decide if we lift bsp apic id while ap apic id"
602 ###############################################
604 ###############################################
606 define CONFIG_IDE_PAYLOAD
609 comment "Boot from IDE device"
611 define CONFIG_ROM_PAYLOAD
614 comment "Boot image is located in ROM"
616 define CONFIG_ROM_PAYLOAD_START
617 default {0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1}
620 comment "ROM stream start location"
622 define CONFIG_COMPRESSED_PAYLOAD_NRV2B
625 comment "NRV2B compressed boot image is located in ROM"
627 define CONFIG_COMPRESSED_PAYLOAD_LZMA
630 comment "LZMA compressed boot image is located in ROM"
632 define CONFIG_PRECOMPRESSED_PAYLOAD
635 comment "boot image is already compressed"
637 define CONFIG_SERIAL_PAYLOAD
640 comment "Download boot image from serial port"
642 define CONFIG_FS_PAYLOAD
645 comment "Boot from a filesystem"
647 define CONFIG_FS_EXT2
650 comment "Enable ext2 filesystem support"
652 define CONFIG_FS_ISO9660
655 comment "Enable ISO9660 filesystem support"
660 comment "Enable FAT filesystem support"
662 define AUTOBOOT_DELAY
665 comment "Delay (in seconds) before autobooting"
667 define AUTOBOOT_CMDLINE
668 default "hdc1:/vmlinuz root=/dev/hdc3 console=tty0 console=ttyS0,115200"
671 comment "Default command line when autobooting"
674 define USE_WATCHDOG_ON_BOOT
677 comment "Use the watchdog on booting"
680 ###############################################
681 # Plugin Device support options
682 ###############################################
684 define CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
687 comment "Enable support for plugin Hypertransport busses"
689 define CONFIG_AGP_PLUGIN_SUPPORT
692 comment "Enable support for plugin AGP busses"
694 define CONFIG_CARDBUS_PLUGIN_SUPPORT
697 comment "Enable support cardbus plugin cards"
699 define CONFIG_PCIX_PLUGIN_SUPPORT
702 comment "Enable support for plugin PCI-X busses"
704 define CONFIG_PCIEXP_PLUGIN_SUPPORT
707 comment "Enable support for plugin PCI-E busses"
710 ###############################################
712 ###############################################
714 define HAVE_PIRQ_TABLE
717 comment "Define if we have a PIRQ table"
722 comment "Define if we have a PIRQ table and want routing IRQs"
724 define IRQ_SLOT_COUNT
727 comment "Number of IRQ slots"
729 define CONFIG_PCIBIOS_IRQ
732 comment "PCIBIOS IRQ support"
737 comment "IOAPIC support"
740 ###############################################
741 # IDE specific options
742 ###############################################
747 comment "Define to include IDE support"
749 define IDE_BOOT_DRIVE
752 comment "Disk number of boot drive"
757 comment "Swap bytes when reading from IDE device"
762 comment "Sector at which to start searching for boot image"
765 ###############################################
766 # Options for memory mapped I/O
767 ###############################################
769 define PCI_IO_CFG_EXT
772 comment "allow 4K register space via io CFG port"
779 comment "Address of PCI Configuration Address Register"
785 comment "Address of PCI Configuration Data Register"
791 comment "Base address of PCI/ISA I/O address range"
797 comment "Base address of PCI/ISA memory address range"
803 comment "PNP Configuration Address Register offset"
809 comment "PNP Configuration Data Register offset"
815 comment "Base address of memory mapped I/O operations"
818 ###############################################
819 # Options for embedded systems
820 ###############################################
822 define EMBEDDED_RAM_SIZE
825 comment "Embedded boards generally have fixed RAM size"
828 ###############################################
830 ###############################################
832 define CONFIG_CHIP_NAME
835 comment "Compile in the chip name"
838 define CONFIG_GDB_STUB
841 comment "Compile in gdb stub support?"
844 define HAVE_INIT_TIMER
847 comment "Have a init_timer function"
849 define HAVE_HARD_RESET
852 comment "Have hard reset"
857 comment "Set to deal with memory hole"
859 define MAX_REBOOT_CNT
862 comment "Set maximum reboots"
865 ###############################################
866 # Misc device options
867 ###############################################
872 comment "Include board specific FAN control initialization"
874 define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
877 comment "Use timer2 to callibrate the x86 time stamp counter"
879 define INTEL_PPRO_MTRR
884 define CONFIG_UDELAY_TSC
887 comment "Implement udelay with the x86 time stamp counter"
889 define CONFIG_UDELAY_IO
892 comment "Implement udelay with x86 io registers"
897 comment "Use this to fake spd rom values"
900 define HAVE_ACPI_TABLES
903 comment "Define to build ACPI tables"
906 define ACPI_SSDTX_NUM
909 comment "extra ssdt num for PCI Device"
912 define AGP_APERTURE_SIZE
916 comment "AGP graphics virtual memory aperture size"
919 define HT_CHAIN_UNITID_BASE
922 comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
925 define HT_CHAIN_END_UNITID_BASE
928 comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than HT_CHAIN_UNITID_BASE, it could be 0"
931 define SB_HT_CHAIN_UNITID_OFFSET_ONLY
934 comment "this will decided if only offset SB hypertransport chain"
937 define SB_HT_CHAIN_ON_BUS0
940 comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
943 define PCI_BUS_SEGN_BITS
946 comment "It could be 0, 1, 2, 3 and 4 only"
949 define MMCONF_SUPPORT
952 comment "enable mmconfig for pci conf"
955 define MMCONF_SUPPORT_DEFAULT
958 comment "enable mmconfig for pci conf"
961 define HW_MEM_HOLE_SIZEK
964 comment "Opteron E0 later memory hole size in K, 0 mean disable"
967 define HW_MEM_HOLE_SIZE_AUTO_INC
970 comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
973 define CONFIG_VAR_MTRR_HOLE
976 comment "using hole in MTRR instead of increasing method"
979 define K8_HT_FREQ_1G_SUPPORT
982 comment "Optern E0 later could support 1G HT, but still depends MB design"
985 define K8_REV_F_SUPPORT
988 comment "Opteron Rev F (DDR2) support"
994 comment "Opteron cpu bus num base"
1000 comment "Opteron cpu device num base"
1006 comment "Hypertransport 3 support, include ac HT and unganged sublink feature"
1009 define EXT_RT_TBL_SUPPORT
1012 comment "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8"
1015 define EXT_CONF_SUPPORT
1018 comment "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4"
1025 comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg"
1028 define CPU_SOCKET_TYPE
1031 comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
1034 define CPU_ADDR_BITS
1037 comment "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48"
1040 define CONFIG_VGA_ROM_RUN
1043 comment "Init x86 ROMs on VGA-class PCI devices"
1046 define CONFIG_PCI_ROM_RUN
1049 comment "Init x86 ROMs on all PCI devices"
1052 define CONFIG_PCI_64BIT_PREF_MEM
1055 comment "allow PCI device get 4G above Region as pref mem"
1058 define CONFIG_AMDMCT
1061 comment "use AMD MCT to init RAM instead of native code"
1064 define AMD_UCODE_PATCH_FILE
1068 comment "name of the micorcode patch file"
1070 define CONFIG_VIDEO_MB
1073 comment "Integrated graphics with UMA has dynamic setup"
1076 define CONFIG_SPLASH_GRAPHIC
1079 comment "Paint a splash screen"
1082 define CONFIG_GX1_VIDEO
1085 comment "Build in GX1's graphic support"
1088 define CONFIG_GX1_VIDEOMODE
1091 comment "Define video mode after reset"
1100 ###############################################
1101 # Board specific options
1102 ###############################################
1104 ###############################################
1105 # Options for motorola/sandpoint
1106 ###############################################
1107 define CONFIG_SANDPOINT_ALTIMUS
1110 comment "Configure Sandpoint with Altimus PMC"
1112 define CONFIG_SANDPOINT_TALUS
1115 comment "Configure Sandpoint with Talus PMC"
1117 define CONFIG_SANDPOINT_UNITY
1120 comment "Configure Sandpoint with Unity PMC"
1122 define CONFIG_SANDPOINT_VALIS
1125 comment "Configure Sandpoint with Valis PMC"
1127 define CONFIG_SANDPOINT_GYRUS
1130 comment "Configure Sandpoint with Gyrus PMC"
1133 ###############################################
1134 # Options for totalimpact/briq
1135 ###############################################
1136 define CONFIG_BRIQ_750FX
1139 comment "Configure briQ with PowerPC 750FX"
1141 define CONFIG_BRIQ_7400
1144 comment "Configure briQ with PowerPC G4"