1 #######################################################
3 # Main options file for coreboot
5 # Each option used by a part must be defined in
6 # this file. The format for options is:
9 # default <expr> | {<expr>} | "<string>" | none
11 # export always | used | never
17 # <name> is the name of the option
18 # <expr> is a numeric expression
19 # <string> is a string
21 # Either a default value or 'default none' must
22 # be specified for every option. An option
23 # specified as 'default none' will not be exported
24 # (i.e. will remain undefined) unless it has
25 # been assigned a value.
27 # Option values can be an immediate expression that
28 # evaluates to a numeric value, a delayed expression
29 # (surrounded by curley braces), or a string
30 # (surrounded by double quotes.)
32 # Immediate expressions are evaluated at the time an
33 # option is defined or set and the numeric result
34 # becomes the value of the option.
36 # Delayed expression are evaluated at the time the
37 # option is used, either in another expression or
38 # when being exported.
40 # String values will have the double quotes removed
43 # Format strings determine the print format that is
44 # used when exporting options. The default format
45 # is "%s" for strings and "%d" for numbers.
47 # Exported options generate entries in the
48 # Makefile.settings file. Options can be always
49 # exported, exported only if used, or never exported.
51 # A comment string must be supplied for every option.
53 #######################################################
55 ###############################################
56 # Architecture options
57 ###############################################
59 define CONFIG_ARCH_X86
62 comment "X86 is the default"
67 comment "Default architecture is i386, options are alpha and ppc"
69 define CONFIG_HAVE_MOVNTI
72 comment "This cpu supports the MOVNTI directive"
75 ###############################################
77 ###############################################
79 define CONFIG_CROSS_COMPILE
82 comment "Cross compiler prefix"
85 default "$(CONFIG_CROSS_COMPILE)gcc"
87 comment "Target C Compiler"
92 comment "Host C Compiler"
97 comment "Additional per-cpu CFLAGS"
100 default "$(CONFIG_CROSS_COMPILE)objcopy --gap-fill 0xff"
102 comment "Objcopy command"
105 # Try to determine svn revision first.
106 # If that fails, try last svn revision in git log.
107 define COREBOOT_VERSION
108 default "2.0.0-r$(shell if [ -d $(TOP)/.svn -a -f `which svnversion` ]; then svnversion $(TOP); else if [ -d $(TOP)/.git -a -f `which git` ]; then git --git-dir=/$(TOP)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)"
111 comment "coreboot version"
113 define COREBOOT_EXTRA_VERSION
117 comment "coreboot extra version"
119 define COREBOOT_BUILD
120 default "$(shell date)"
125 define COREBOOT_COMPILE_TIME
126 default "$(shell date +%T)"
131 define COREBOOT_COMPILE_BY
132 default "$(shell whoami)"
135 comment "Who build this image"
137 define COREBOOT_COMPILE_HOST
138 default "$(shell hostname)"
144 define COREBOOT_COMPILE_DOMAIN
145 default "$(shell dnsdomainname)"
148 comment "Build domain name"
150 define COREBOOT_COMPILER
151 default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -1)"
154 comment "Build compiler"
156 define COREBOOT_LINKER
157 default "$(shell $(CC) -Wl,--version 2>&1 | grep \" ld\")"
160 comment "Build linker"
162 define COREBOOT_ASSEMBLER
163 default "$(shell touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"
166 comment "Build assembler"
168 define CONFIG_CHIP_CONFIGURE
171 comment "Use new chip_configure method for configuring (non-pci) devices"
173 define CONFIG_USE_INIT
176 comment "Use stage 1 initialization code"
179 ###############################################
181 ###############################################
183 define CONFIG_HAVE_FALLBACK_BOOT
187 comment "Set if fallback booting required"
189 define CONFIG_HAVE_FAILOVER_BOOT
193 comment "Set if failover booting required"
195 define CONFIG_USE_FALLBACK_IMAGE
199 comment "Set to build a fallback image"
201 define CONFIG_USE_FAILOVER_IMAGE
205 comment "Set to build a failover image"
207 define CONFIG_FALLBACK_SIZE
211 comment "Default fallback image size"
213 define CONFIG_FAILOVER_SIZE
217 comment "Default failover image size"
219 define CONFIG_ROM_SIZE
223 comment "Size of your ROM"
225 define CONFIG_ROM_IMAGE_SIZE
229 comment "Default image size"
231 define CONFIG_ROM_SECTION_SIZE
232 default {CONFIG_FALLBACK_SIZE}
235 comment "Default rom section size"
237 define CONFIG_ROM_SECTION_OFFSET
238 default {CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE}
241 comment "Default rom section offset"
243 define CONFIG_ROMBASE
244 default {0xffffffff - CONFIG_ROM_SIZE + 1}
247 comment "Base address of coreboot in ROM"
249 define CONFIG_ROMSTART
253 comment "Start address of coreboot in ROM"
256 default {CONFIG_ROMBASE}
259 comment "Hardware reset vector address"
261 define CONFIG_STACK_SIZE
265 comment "Default stack size"
267 define CONFIG_HEAP_SIZE
271 comment "Default heap size"
273 define CONFIG_RAMBASE
277 comment "Base address of coreboot in RAM"
279 define CONFIG_RAMSTART
283 comment "Start address of coreboot in RAM"
285 define CONFIG_USE_DCACHE_RAM
288 comment "Use data cache as temporary RAM if possible"
290 define CONFIG_DCACHE_RAM_BASE
294 comment "Base address of data cache when using it for temporary RAM"
296 define CONFIG_DCACHE_RAM_SIZE
300 comment "Size of data cache when using it for temporary RAM"
302 define CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
306 comment "Size of region that for global variable of cache as ram stage"
308 define CONFIG_AP_CODE_IN_CAR
311 comment "will copy coreboot_apc to AP cache ane execute in AP"
313 define CONFIG_MEM_TRAIN_SEQ
316 comment "0: three for in bsp, 1: on every core0, 2: one for on bsp"
318 define CONFIG_WAIT_BEFORE_CPUS_INIT
321 comment "execute cpus_ready_for_init if it is set to 1"
323 define CONFIG_XIP_ROM_BASE
327 comment "Start address of area to cache during coreboot execution directly from ROM"
329 define CONFIG_XIP_ROM_SIZE
333 comment "Size of area to cache during coreboot execution directly from ROM"
335 define CONFIG_COMPRESS
338 comment "Set for compressed image"
340 define CONFIG_UNCOMPRESSED
342 default {!CONFIG_COMPRESS}
344 comment "Set for uncompressed image"
350 comment "Highest RAM that coreboot_ram will use"
352 define CONFIG_HAVE_OPTION_TABLE
355 comment "Export CMOS option table"
357 define CONFIG_USE_OPTION_TABLE
359 default {CONFIG_HAVE_OPTION_TABLE && !CONFIG_USE_FALLBACK_IMAGE}
361 comment "Use option table"
364 ###############################################
365 # CMOS variable options
366 ###############################################
367 define CONFIG_LB_CKS_RANGE_START
371 comment "First CMOS byte to use for coreboot options"
373 define CONFIG_LB_CKS_RANGE_END
377 comment "Last CMOS byte to use for coreboot options"
379 define CONFIG_LB_CKS_LOC
383 comment "Pair of bytes to use for CMOS checksum"
387 ###############################################
389 ###############################################
392 default "$(TOP)/src/arch/$(CONFIG_ARCH)/init/crt0.S.lb"
394 comment "Main initialization target"
397 ###############################################
398 # Debugging/Logging options
399 ###############################################
404 comment "Enable x86emu debugging code"
406 define CONFIG_VGA_BRIDGE_SETUP
409 comment "Set bridge bits to enable legacy VGA ranges"
411 define CONFIG_CONSOLE_VGA
414 comment "Log messages to any VGA-compatible device (may require *_ROM_RUN to bring up)"
416 define CONFIG_CONSOLE_VGA_MULTI
419 comment "Multi VGA console"
421 define CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
424 comment "Use onboard VGA instead of add on VGA card"
426 define CONFIG_CONSOLE_BTEXT
429 comment "Log messages to btext fb console"
431 define CONFIG_CONSOLE_LOGBUF
434 comment "Log messages to buffer"
436 define CONFIG_CONSOLE_SROM
439 comment "Log messages to SROM console"
441 define CONFIG_CONSOLE_SERIAL8250
444 comment "Log messages to 8250 uart based serial console"
446 define CONFIG_USBDEBUG_DIRECT
449 comment "Log messages to ehci debug port console"
451 define CONFIG_DEFAULT_CONSOLE_LOGLEVEL
454 comment "Console will log at this level unless changed"
456 define CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
459 comment "Error messages up to this level can be printed"
461 define CONFIG_SERIAL_POST
464 comment "Enable SERIAL POST codes"
466 define CONFIG_NO_POST
469 comment "Disable POST codes"
471 define CONFIG_TTYS0_BASE
475 comment "Base address for 8250 uart for the serial console"
477 define CONFIG_TTYS0_BAUD
480 comment "Default baud rate for serial console"
482 define CONFIG_TTYS0_DIV
486 comment "Allow UART divisor to be set explicitly"
488 define CONFIG_TTYS0_LCS
492 comment "Default flow control settings for the 8250 serial console uart"
495 define CONFIG_USE_PRINTK_IN_CAR
498 comment "use printk instead of print in CAR stage code"
500 define CONFIG_ASSEMBLER_DEBUG
503 comment "Create disassembly files for debugging"
506 ###############################################
508 ###############################################
510 define CONFIG_MAINBOARD
511 default "Mainboard_not_set"
513 comment "Mainboard name"
515 define CONFIG_MAINBOARD_PART_NUMBER
516 default "Part_number_not_set"
519 comment "Part number of mainboard"
521 define CONFIG_MAINBOARD_VENDOR
522 default "Vendor_not_set"
525 comment "Vendor of mainboard"
527 define CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
530 comment "PCI Vendor ID of mainboard manufacturer"
532 define CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
536 comment "PCI susbsystem device id assigned my mainboard manufacturer"
538 define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
541 comment "Default power on after power fail setting"
543 define CONFIG_SYS_CLK_FREQ
546 comment "System clock frequency in MHz"
548 define CONFIG_EPIA_VT8237R_INIT
551 comment "Enable EPIA Specific Initialisation of VT8237R SB"
553 ###############################################
555 ###############################################
560 comment "Define if we support SMP"
562 define CONFIG_MAX_CPUS
565 comment "Maximum CPU count for this machine"
567 define CONFIG_MAX_PHYSICAL_CPUS
570 comment "Maximum physical CPU count for this machine"
572 define CONFIG_LOGICAL_CPUS
575 comment "Should multiple cpus per die be enabled?"
577 define CONFIG_AP_IN_SIPI_WAIT
580 comment "Should application processors go to SIPI wait state after initialization? (Required for Intel Core Duo)"
582 define CONFIG_GENERATE_MP_TABLE
585 comment "Define to build an MP table"
587 define CONFIG_SERIAL_CPU_INIT
590 comment "Serialize CPU init"
592 define CONFIG_APIC_ID_OFFSET
595 comment "We need to share this value between cache_as_ram_auto.c and northbridge.c"
597 define CONFIG_ENABLE_APIC_EXT_ID
600 comment "Enable APIC ext id mode 8 bit"
602 define CONFIG_LIFT_BSP_APIC_ID
605 comment "decide if we lift bsp apic id while ap apic id"
607 ###############################################
609 ###############################################
611 define CONFIG_MULTIBOOT
614 comment "Use Multiboot (rather than ELF boot notes) to boot the payload"
616 define CONFIG_ROM_PAYLOAD
619 comment "Boot image is located in ROM"
621 define CONFIG_COMPRESSED_PAYLOAD_NRV2B
624 comment "NRV2B compressed boot image is located in ROM"
626 define CONFIG_COMPRESSED_PAYLOAD_LZMA
629 comment "LZMA compressed boot image is located in ROM"
631 define CONFIG_PRECOMPRESSED_PAYLOAD
634 comment "boot image is already compressed"
637 define CONFIG_USE_WATCHDOG_ON_BOOT
640 comment "Use the watchdog on booting"
643 ###############################################
644 # Plugin Device support options
645 ###############################################
647 define CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
650 comment "Enable support for plugin Hypertransport busses"
652 define CONFIG_AGP_PLUGIN_SUPPORT
655 comment "Enable support for plugin AGP busses"
657 define CONFIG_CARDBUS_PLUGIN_SUPPORT
660 comment "Enable support cardbus plugin cards"
662 define CONFIG_PCIX_PLUGIN_SUPPORT
665 comment "Enable support for plugin PCI-X busses"
667 define CONFIG_PCIEXP_PLUGIN_SUPPORT
670 comment "Enable support for plugin PCI-E busses"
673 ###############################################
675 ###############################################
677 define CONFIG_GENERATE_PIRQ_TABLE
680 comment "Define if we have a PIRQ table"
682 define CONFIG_PIRQ_ROUTE
685 comment "Define if we have a PIRQ table and want routing IRQs"
687 define CONFIG_IRQ_SLOT_COUNT
690 comment "Number of IRQ slots"
692 define CONFIG_PCIBIOS_IRQ
695 comment "PCIBIOS IRQ support"
700 comment "IOAPIC support"
703 ###############################################
704 # Options for memory mapped I/O
705 ###############################################
707 define CONFIG_PCI_IO_CFG_EXT
710 comment "allow 4K register space via io CFG port"
713 define CONFIG_PCIC0_CFGADDR
717 comment "Address of PCI Configuration Address Register"
719 define CONFIG_PCIC0_CFGDATA
723 comment "Address of PCI Configuration Data Register"
725 define CONFIG_ISA_IO_BASE
729 comment "Base address of PCI/ISA I/O address range"
731 define CONFIG_ISA_MEM_BASE
735 comment "Base address of PCI/ISA memory address range"
737 define CONFIG_PNP_CFGADDR
741 comment "PNP Configuration Address Register offset"
743 define CONFIG_PNP_CFGDATA
747 comment "PNP Configuration Data Register offset"
749 define CONFIG_IO_BASE
753 comment "Base address of memory mapped I/O operations"
756 ###############################################
757 # Options for embedded systems
758 ###############################################
760 define CONFIG_EMBEDDED_RAM_SIZE
763 comment "Embedded boards generally have fixed RAM size"
766 ###############################################
768 ###############################################
770 define CONFIG_GDB_STUB
773 comment "Compile in gdb stub support?"
776 define CONFIG_HAVE_INIT_TIMER
779 comment "Have a init_timer function"
781 define CONFIG_HAVE_HARD_RESET
784 comment "Have hard reset"
786 define CONFIG_HAVE_SMI_HANDLER
789 comment "Set, if the board needs an SMI handler"
791 define CONFIG_MEMORY_HOLE
794 comment "Set to deal with memory hole"
796 define CONFIG_MAX_REBOOT_CNT
799 comment "Set maximum reboots"
802 ###############################################
803 # Misc device options
804 ###############################################
806 define CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
809 comment "Include board specific FAN control initialization"
811 define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
814 comment "Use timer2 to callibrate the x86 time stamp counter"
816 define CONFIG_INTEL_PPRO_MTRR
821 define CONFIG_UDELAY_TSC
824 comment "Implement udelay with the x86 time stamp counter"
826 define CONFIG_UDELAY_IO
829 comment "Implement udelay with x86 io registers"
831 define CONFIG_UDELAY_LAPIC
834 comment "Implement udelay with the x86 Local APIC"
837 define CONFIG_GENERATE_ACPI_TABLES
840 comment "Define to build ACPI tables"
843 define CONFIG_HAVE_ACPI_RESUME
846 comment "Define to build ACPI with resume support"
849 define CONFIG_ACPI_SSDTX_NUM
852 comment "extra ssdt num for PCI Device"
855 define CONFIG_AGP_APERTURE_SIZE
859 comment "AGP graphics virtual memory aperture size"
862 define CONFIG_HT_CHAIN_UNITID_BASE
865 comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
868 define CONFIG_HT_CHAIN_END_UNITID_BASE
871 comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than CONFIG_HT_CHAIN_UNITID_BASE, it could be 0"
874 define CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
877 comment "this will decided if only offset SB hypertransport chain"
880 define CONFIG_SB_HT_CHAIN_ON_BUS0
883 comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
886 define CONFIG_PCI_BUS_SEGN_BITS
889 comment "It could be 0, 1, 2, 3 and 4 only"
892 define CONFIG_MMCONF_SUPPORT
895 comment "enable mmconfig for pci conf"
898 define CONFIG_MMCONF_SUPPORT_DEFAULT
901 comment "enable mmconfig for pci conf"
904 define CONFIG_MMCONF_BASE_ADDRESS
908 comment "enable mmconfig base address"
911 define CONFIG_HW_MEM_HOLE_SIZEK
914 comment "Opteron E0 later memory hole size in K, 0 mean disable"
917 define CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
920 comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
923 define CONFIG_VAR_MTRR_HOLE
926 comment "using hole in MTRR instead of increasing method"
929 define CONFIG_K8_HT_FREQ_1G_SUPPORT
932 comment "Optern E0 later could support 1G HT, but still depends MB design"
935 define CONFIG_K8_REV_F_SUPPORT
938 comment "Opteron Rev F (DDR2) support"
944 comment "Opteron cpu bus num base"
950 comment "Opteron cpu device num base"
953 define CONFIG_HT3_SUPPORT
956 comment "Hypertransport 3 support, include ac HT and unganged sublink feature"
959 define CONFIG_EXT_RT_TBL_SUPPORT
962 comment "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8"
965 define CONFIG_EXT_CONF_SUPPORT
968 comment "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4"
971 define CONFIG_DIMM_SUPPORT
975 comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg"
978 define CONFIG_CPU_SOCKET_TYPE
981 comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
984 define CONFIG_CPU_ADDR_BITS
987 comment "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48"
993 comment "Include VGA initialisation code"
996 define CONFIG_VGA_ROM_RUN
999 comment "Init x86 ROMs on VGA-class PCI devices"
1002 define CONFIG_PCI_ROM_RUN
1005 comment "Init x86 ROMs on all PCI devices"
1008 define CONFIG_PCI_OPTION_ROM_RUN_YABEL
1011 comment "Use Yabel instead of old bios emulator"
1014 define CONFIG_YABEL_DEBUG_FLAGS
1017 comment "YABEL debug flags, for possible values, see util/x86emu/yabel/debug.h"
1020 define CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES
1023 comment "Allow Option ROMs executed by YABEL to access the config space of devices other than the one YABEL is running for. This may be needed by some onboard Graphics cards ROMs."
1027 define CONFIG_PCI_OPTION_ROM_RUN_REALMODE
1030 comment "Use Yabel instead of old bios emulator"
1033 define CONFIG_PCI_64BIT_PREF_MEM
1036 comment "allow PCI device get 4G above Region as pref mem"
1039 define CONFIG_AMDMCT
1042 comment "use AMD MCT to init RAM instead of native code"
1045 define CONFIG_AMD_UCODE_PATCH_FILE
1049 comment "name of the microcode patch file"
1052 define CONFIG_K8_MEM_BANK_B_ONLY
1055 comment "use AMD K8's memory bank B only to make a 64bit memory system and memory bank A is free, such as Filbert."
1058 define CONFIG_VIDEO_MB
1061 comment "Integrated graphics with UMA has dynamic setup"
1064 define CONFIG_GFXUMA
1070 define CONFIG_HAVE_MAINBOARD_RESOURCES
1073 comment "Enable if the mainboard/chipset requires extra entries in the memory map"
1076 define CONFIG_HAVE_LOW_TABLES
1079 comment "Enable if ACPI, PIRQ, MP tables are supposed to live in the low megabyte"
1082 define CONFIG_WRITE_HIGH_TABLES
1085 comment "Enable if ACPI, PIRQ, MP tables are supposed to live at top of memory"
1088 define CONFIG_SPLASH_GRAPHIC
1091 comment "Paint a splash screen"
1094 define CONFIG_GX1_VIDEO
1097 comment "Build in GX1's graphic support"
1100 define CONFIG_GX1_VIDEOMODE
1103 comment "Define video mode after reset"
1112 define CONFIG_PCIE_CONFIGSPACE_HOLE
1115 comment "Leave a hole for PCIe config space in the device allocator"
1118 define CONFIG_ID_SECTION_OFFSET
1121 comment "Offset of the .id section. Only needs to change if something like a romstrap is in the way"