2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
5 ## Copyright (C) 2009 Ronald G. Minnich
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; version 2 of the License.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #######################################################################
22 # Take care of subdirectories
29 ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
30 ramstage-srcs += $(obj)/option_table.c
31 OPTION_TABLE_H:=$(obj)/option_table.h
34 #######################################################################
35 # Build the final rom image
36 COREBOOT_ROM_DEPENDENCIES:=
37 ifeq ($(CONFIG_PAYLOAD_ELF),y)
38 COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_PAYLOAD_FILE)
40 ifeq ($(CONFIG_PAYLOAD_SEABIOS),y)
41 COREBOOT_ROM_DEPENDENCIES+=seabios
43 ifeq ($(CONFIG_VGA_BIOS),y)
44 COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_VGA_BIOS_FILE)
46 ifeq ($(CONFIG_INTEL_MBI),y)
47 COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_MBI_FILE)
49 ifeq ($(CONFIG_BOOTSPLASH),y)
50 COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_BOOTSPLASH_FILE)
52 ifeq ($(CONFIG_AP_CODE_IN_CAR),y)
53 COREBOOT_ROM_DEPENDENCIES+=$(obj)/coreboot_ap
55 ifeq ($(CONFIG_GEODE_VSA_FILE),y)
56 COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_VSA_FILENAME)
59 extract_nth=$(word $(1), $(subst |, ,$(2)))
61 ifneq ($(CONFIG_UPDATE_IMAGE),y)
63 $(foreach file,$(cbfs-files), \
64 $(CBFSTOOL) $@ add $(call extract_nth,1,$(file)) $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) $(call extract_nth,4,$(file)); )
65 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
67 $(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $(prebuilt-files) $(CBFSTOOL)
69 $(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock
72 $(obj)/coreboot.pre1: $(CBFSTOOL)
73 mv $(obj)/coreboot.rom $@
76 $(obj)/coreboot.rom: $(obj)/coreboot.pre $(obj)/coreboot_ram $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES))
77 @printf " CBFS $(subst $(obj)/,,$(@))\n"
78 cp $(obj)/coreboot.pre $@.tmp
79 if [ -f $(obj)/coreboot_ap ]; \
81 $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ap $(CONFIG_CBFS_PREFIX)/coreboot_ap $(CBFS_COMPRESS_FLAG); \
83 $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ram $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG)
84 ifeq ($(CONFIG_PAYLOAD_NONE),y)
85 @printf " PAYLOAD \e[1;31mnone (as specified by user)\e[0m\n"
87 ifeq ($(CONFIG_PAYLOAD_ELF),y)
88 @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n"
89 $(CBFSTOOL) $@.tmp add-payload $(CONFIG_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG)
91 ifeq ($(CONFIG_PAYLOAD_SEABIOS),y)
92 @printf " PAYLOAD SeaBIOS (internal, compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n"
93 $(CBFSTOOL) $@.tmp add-payload $(CONFIG_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG)
95 ifeq ($(CONFIG_VGA_BIOS),y)
96 @printf " VGABIOS $(CONFIG_VGA_BIOS_FILE) $(CONFIG_VGA_BIOS_ID)\n"
97 $(CBFSTOOL) $@.tmp add $(CONFIG_VGA_BIOS_FILE) "pci$(CONFIG_VGA_BIOS_ID).rom" optionrom
99 ifeq ($(CONFIG_INTEL_MBI),y)
100 @printf " MBI $(CONFIG_MBI_FILE)\n"
101 $(CBFSTOOL) $@.tmp add $(CONFIG_MBI_FILE) mbi.bin mbi
103 ifeq ($(CONFIG_BOOTSPLASH),y)
104 @printf " BOOTSPLASH $(CONFIG_BOOTSPLASH_FILE)\n"
105 $(CBFSTOOL) $@.tmp add $(CONFIG_BOOTSPLASH_FILE) bootsplash.jpg bootsplash
107 ifeq ($(CONFIG_GEODE_VSA_FILE),y)
108 @printf " VSA $(CONFIG_VSA_FILENAME)\n"
109 $(OBJCOPY) --set-start 0x20 --adjust-vma 0x60000 -I binary -O elf32-i386 -B i386 $(CONFIG_VSA_FILENAME) $(obj)/vsa.o
110 $(LD) -m elf_i386 -e 0x60020 --section-start .data=0x60000 $(obj)/vsa.o -o $(obj)/vsa.elf
111 $(CBFSTOOL) $@.tmp add-stage $(obj)/vsa.elf vsa
114 @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n"
117 #######################################################################
118 # i386 specific tools
120 $(OPTION_TABLE_H): $(objutil)/options/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout
121 @printf " OPTION $(subst $(obj)/,,$(@))\n"
122 $(objutil)/options/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --header $@
124 $(obj)/option_table.c: $(objutil)/options/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout
125 @printf " OPTION $(subst $(obj)/,,$(@))\n"
126 $(objutil)/options/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --option $@
128 $(objutil)/options/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src/include/pc80/mc146818rtc.h $(top)/src/include/boot/coreboot_tables.h
129 @printf " HOSTCC $(subst $(obj)/,,$(@))\n"
130 $(HOSTCC) $(HOSTCFLAGS) $< -o $@
132 #######################################################################
133 # Build the coreboot_ram (stage 2)
135 $(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld #ldoptions
136 @printf " CC $(subst $(obj)/,,$(@))\n"
137 $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $(obj)/coreboot_ram.o
138 $(NM) -n $(obj)/coreboot_ram | sort > $(obj)/coreboot_ram.map
139 $(OBJCOPY) --only-keep-debug $@ $(obj)/coreboot_ram.debug
140 $(OBJCOPY) --strip-debug $@
141 $(OBJCOPY) --add-gnu-debuglink=$(obj)/coreboot_ram.debug $@
143 $(obj)/coreboot_ram.o: $(obj)/arch/x86/lib/c_start.ramstage.o $$(driver-objs) $(obj)/coreboot.a $(LIBGCC_FILE_NAME)
144 @printf " CC $(subst $(obj)/,,$(@))\n"
145 $(CC) -nostdlib -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(obj)/coreboot.a $(LIBGCC_FILE_NAME) -Wl,--end-group
147 $(obj)/coreboot.a: $$(ramstage-objs)
148 @printf " AR $(subst $(obj)/,,$(@))\n"
149 rm -f $(obj)/coreboot.a
150 $(AR) cr $(obj)/coreboot.a $^
152 #######################################################################
155 ifeq ($(CONFIG_AP_CODE_IN_CAR),y)
157 $(obj)/coreboot_ap: $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o
158 @printf " CC $(subst $(obj)/,,$(@))\n"
159 $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/init/ldscript_apc.lb $^
160 $(OBJCOPY) --only-keep-debug $@ $(obj)/coreboot_ap.debug
161 $(OBJCOPY) --strip-debug $@
162 $(OBJCOPY) --add-gnu-debuglink=$(obj)/coreboot_ap.debug $@
163 $(NM) -n $(obj)/coreboot_ap | sort > $(obj)/coreboot_ap.map
168 #######################################################################
171 crt0s = $(src)/arch/x86/init/prologue.inc
173 ldscripts += $(src)/arch/x86/init/ldscript_fallback_cbfs.lb
174 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
175 crt0s += $(src)/cpu/x86/16bit/entry16.inc
176 ldscripts += $(src)/cpu/x86/16bit/entry16.lds
178 crt0s += $(src)/cpu/x86/32bit/entry32.inc
179 ldscripts += $(src)/cpu/x86/32bit/entry32.lds
180 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
181 crt0s += $(src)/cpu/x86/16bit/reset16.inc
182 ldscripts += $(src)/cpu/x86/16bit/reset16.lds
183 crt0s += $(src)/arch/x86/lib/id.inc
184 ldscripts += $(src)/arch/x86/lib/id.lds
187 crt0s += $(src)/cpu/x86/fpu_enable.inc
188 ifeq ($(CONFIG_SSE),y)
189 crt0s += $(src)/cpu/x86/sse_enable.inc
195 # FIXME move to CPU_INTEL_SOCKET_MPGA604
197 ifeq ($(CONFIG_BOARD_TYAN_S2735),y)
198 crt0s += $(src)/cpu/intel/car/cache_as_ram.inc
201 ifeq ($(CONFIG_LLSHELL),y)
202 crt0s += $(src)/arch/x86/llshell/llshell.inc
205 crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
207 ifeq ($(CONFIG_SSE),y)
208 crt0s += $(src)/cpu/x86/sse_disable.inc
210 ifeq ($(CONFIG_MMX),y)
211 crt0s += $(src)/cpu/x86/mmx_disable.inc
214 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
215 crt0s += $(chipset_bootblock_inc)
216 ldscripts += $(chipset_bootblock_lds)
219 ifeq ($(CONFIG_ROMCC),y)
220 crt0s += $(src)/arch/x86/init/crt0_romcc_epilogue.inc
223 ifeq ($(CONFIG_ROMCC),y)
224 ROMCCFLAGS ?= -mcpu=p2 -O2
226 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
227 printf " ROMCC romstage.inc\n"
228 $(ROMCC) -c -S $(ROMCCFLAGS) -D__PRE_RAM__ -I. $(INCLUDES) $< -o $@
231 $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(OPTION_TABLE_H)
232 @printf " CC $(subst $(obj)/,,$(@))\n"
233 $(CC) -MMD $(CFLAGS) -I$(src) -I. -I$(obj) -c $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
235 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h
236 @printf " CC romstage.inc\n"
237 $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
239 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
240 @printf " POST romstage.inc\n"
241 sed -e 's/\.rodata/.rom.data/g' -e 's/\.text/.section .rom.text/g' $^ > $@.tmp
245 # Things that appear in every board
246 romstage-srcs += $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s
247 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
248 ifeq ($(CONFIG_GENERATE_MP_TABLE),y)
249 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mptable.c
251 ifeq ($(CONFIG_GENERATE_PIRQ_TABLE),y)
252 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/irq_tables.c
254 ifeq ($(CONFIG_BOARD_HAS_HARD_RESET),y)
255 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/reset.c
257 ifeq ($(CONFIG_GENERATE_ACPI_TABLES),y)
258 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c
259 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/dsdt.asl
260 # make doesn't have arithmetic operators or greater-than comparisons
261 ifeq ($(subst 5,4,$(CONFIG_ACPI_SSDTX_NUM)),4)
262 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt2.asl
263 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt3.asl
264 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt4.asl
266 ifeq ($(CONFIG_ACPI_SSDTX_NUM),5)
267 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt5.asl
269 ifeq ($(CONFIG_BOARD_HAS_FADT),y)
270 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/fadt.c
274 ifeq ($(CONFIG_HAVE_BUS_CONFIG),y)
275 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c
278 ifeq ($(CONFIG_TINY_BOOTBLOCK),y)
279 include $(src)/arch/x86/Makefile.bootblock.inc
281 include $(src)/arch/x86/Makefile.bigbootblock.inc
285 $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \
286 CC="$(CC)" LD="$(LD)" \
287 CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \
288 CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE)