2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2000 AG Electronics Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /* In the MSR, not all bits are interesting to us
21 16 - EE - External interrupts
22 17 - PR - Privilege level
23 18 - FP - Floating Point available
24 19 - ME - Machine check exception enable
25 20 - FE0 - Floating exception mode 0
26 23 - FE1 - Floating exception mode 1
27 MSR_MASK is the bits we do not change.
30 #define MSR_MASK 0xfff8008c
31 #define MSR_EE 0x00008000
32 #define MSR_PR 0x00004000
33 #define MSR_FP 0x00002000
34 #define MSR_ME 0x00001000
35 #define MSR_FE0 0x00000800
36 #define MSR_FE1 0x00000100
38 #define MSR_DEFAULT (MSR_FP | MSR_IR | MSR_DR)
45 * BL field in upper BAT register
47 #define BAT_BL_128K 0x00000000
48 #define BAT_BL_256K 0x00000004
49 #define BAT_BL_512K 0x0000000C
50 #define BAT_BL_1M 0x0000001C
51 #define BAT_BL_2M 0x0000003C
52 #define BAT_BL_4M 0x0000007C
53 #define BAT_BL_8M 0x000000FC
54 #define BAT_BL_16M 0x000001FC
55 #define BAT_BL_32M 0x000003FC
56 #define BAT_BL_64M 0x000007FC
57 #define BAT_BL_128M 0x00000FFC
58 #define BAT_BL_256M 0x00001FFC
61 * Supervisor/user valid mode in upper BAT register
63 #define BAT_VALID_SUPERVISOR 0x00000002
64 #define BAT_VALID_USER 0x00000001
65 #define BAT_INVALID 0x00000000
68 * WIMG bit setting in lower BAT register
70 #define BAT_WRITE_THROUGH 0x00000040
71 #define BAT_CACHE_INHIBITED 0x00000020
72 #define BAT_COHERENT 0x00000010
73 #define BAT_GUARDED 0x00000008
76 * Protection bits in lower BAT register
78 #define BAT_NO_ACCESS 0x00000000
79 #define BAT_READ_ONLY 0x00000001
80 #define BAT_READ_WRITE 0x00000002
82 /* Processor Version Register */
84 /* Processor Version Register (PVR) field extraction */
86 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
87 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
90 * IBM has further subdivided the standard PowerPC 16-bit version and
91 * revision subfields of the PVR for the PowerPC 403s into the following:
94 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
95 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
96 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
97 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
98 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
99 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
101 /* Processor Version Numbers */
103 #define PVR_403GA 0x00200000
104 #define PVR_403GB 0x00200100
105 #define PVR_403GC 0x00200200
106 #define PVR_403GCX 0x00201400
107 #define PVR_405GP 0x40110000
108 #define PVR_405GP_RB 0x40110040
109 #define PVR_405GP_RC 0x40110082
110 #define PVR_405GP_RD 0x401100C4
111 #define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
112 #define PVR_405CR_RA 0x40110041
113 #define PVR_405CR_RB 0x401100C5
114 #define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
115 #define PVR_405GPR_RB 0x50910951
116 #define PVR_440GP_RB 0x40120440
117 #define PVR_440GP_RC 0x40120481
118 #define PVR_405EP_RB 0x51210950
119 #define PVR_601 0x00010000
120 #define PVR_602 0x00050000
121 #define PVR_603 0x00030000
122 #define PVR_603e 0x00060000
123 #define PVR_603ev 0x00070000
124 #define PVR_603r 0x00071000
125 #define PVR_604 0x00040000
126 #define PVR_604e 0x00090000
127 #define PVR_604r 0x000A0000
128 #define PVR_620 0x00140000
129 #define PVR_740 0x00080000
130 #define PVR_750 PVR_740
131 #define PVR_740P 0x10080000
132 #define PVR_750P PVR_740P
134 * For the 8xx processors, all of them report the same PVR family for
135 * the PowerPC core. The various versions of these processors must be
136 * differentiated by the version number in the Communication Processor
139 #define PVR_821 0x00500000
140 #define PVR_823 PVR_821
141 #define PVR_850 PVR_821
142 #define PVR_860 PVR_821
143 #define PVR_7400 0x000C0000
144 #define PVR_8240 0x00810100
145 #define PVR_8260 PVR_8240
147 /*----------------------------------------------------------------------------+
148 | Processor Version Register (PVR) values
149 +----------------------------------------------------------------------------*/
150 #define PVR_970 0x0039 /* 970 any revision*/
151 #define PVR_970DD_1_0 0x00391100 /* 970 DD1.0 */
152 #define PVR_970FX 0x003C /* 970FX any revision*/
153 #define PVR_970FX_DD_2_0 0x003C0200 /* 970FX DD2.0 */
154 #define PVR_970FX_DD_2_1 0x003C0201 /* 970FX DD2.1 */
155 #define PVR_970FX_DD_3_0 0x003C0300 /* 970FX DD3.0 */
156 #define PVR_RESERVED 0x000000F0 /* reserved nibble */
158 #define SPR_SRR0 0x01a
159 #define SPR_SRR1 0x01b
160 #define SPR_SPRG0 0x110
161 #define SPR_SPRG1 0x111
162 #define SPR_SPRG2 0x112
163 #define SPR_SPRG3 0x113
164 #define SPR_PVR 0x11f
165 #define SPR_TBLR 0x10c
166 #define SPR_TBUR 0x10d
169 #define LOAD_64BIT_VAL(ra,value) addis ra,r0,value@highest; \
170 ori ra,ra,value@higher; \
172 oris ra,ra,value@h; \
174 #define TLBIEL(rb) .long 0x7C000000|\
176 #define HRFID() .long 0x4C000000|\
181 unsigned __getmsr(void);
182 void __setmsr(unsigned value);
183 unsigned __gethid0(void);
184 unsigned __gethid1(void);
185 void __sethid0(unsigned value);
186 unsigned __getpvr(void);