7 * Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer
9 * This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * Originally this code was part of ucl the data compression library
15 * for upx the ``Ultimate Packer of eXecutables''.
17 * - Converted to gas assembly, and refitted to work with etherboot.
18 * Eric Biederman 20 Aug 2002
19 * - Merged the nrv2b decompressor into crt0.base of coreboot
20 * Eric Biederman 26 Sept 2002
25 #include <arch/intel.h>
26 #include <console/loglevel.h>
29 * This is the entry code the code in .reset section
30 * jumps to this address.
33 .section ".rom.data", "a", @progbits
34 .section ".rom.text", "ax", @progbits
36 intel_chip_post_macro(0x01) /* delay for chipsets */
38 #include "crt0_includes.h"
40 #if CONFIG_USE_DCACHE_RAM == 0
41 #ifndef CONSOLE_DEBUG_TX_STRING
42 /* uses: esp, ebx, ax, dx */
43 # define __CRT_CONSOLE_TX_STRING(string) \
45 CALLSP(crt_console_tx_string)
47 # if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
48 # define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string)
50 # define CONSOLE_DEBUG_TX_STRING(string)
54 /* clear boot_complete flag */
57 CONSOLE_DEBUG_TX_STRING($str_copying_to_ram)
60 * Copy data into RAM and clear the BSS. Since these segments
61 * isn\'t really that big we just copy/clear using bytes, not
64 intel_chip_post_macro(0x11) /* post 11 */
66 cld /* clear direction flag */
68 /* copy coreboot from it's initial load location to
69 * the location it is compiled to run at.
70 * Normally this is copying from FLASH ROM to RAM.
73 /* FIXME: look for a proper place for the stack */
78 pushl $str_coreboot_ram_name
79 call cbfs_and_run_core
88 call copy_and_run_core
92 intel_chip_post_macro(0xee) /* post fe */
96 #ifdef __CRT_CONSOLE_TX_STRING
97 /* Uses esp, ebx, ax, dx */
98 crt_console_tx_string:
106 #ifndef CONFIG_TTYS0_BASE
107 #define CONFIG_TTYS0_BASE 0x3f8
110 #define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00)
113 #define TTYS0_TBR TTYS0_RBR
114 #define TTYS0_IER (CONFIG_TTYS0_BASE+0x01)
115 #define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02)
116 #define TTYS0_FCR TTYS0_IIR
117 #define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03)
118 #define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04)
119 #define TTYS0_DLL TTYS0_RBR
120 #define TTYS0_DLM TTYS0_IER
123 #define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05)
124 #define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06)
125 #define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07)
128 10: mov $TTYS0_LSR, %dx
136 jmp crt_console_tx_string
137 #endif /* __CRT_CONSOLE_TX_STRING */
139 #if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
142 str_copying_to_ram: .string "Uncompressing coreboot to RAM.\r\n"
144 str_copying_to_ram: .string "Copying coreboot to RAM.\r\n"
146 str_pre_main: .string "Jumping to coreboot.\r\n"
149 #endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
152 # if CONFIG_USE_FALLBACK_IMAGE == 1
153 str_coreboot_ram_name: .string "fallback/coreboot_ram"
155 str_coreboot_ram_name: .string "normal/coreboot_ram"
159 #endif /* CONFIG_USE_DCACHE_RAM */