1 #######################################################################
2 # Take care of subdirectories
8 obj-$(CONFIG_HAVE_OPTION_TABLE) += ../../option_table.o
12 #######################################################################
13 # Build the final rom image
14 $(obj)/coreboot.rom: $(obj)/coreboot.pre $(obj)/coreboot_ram $(CBFSTOOL)
15 cp $(obj)/coreboot.pre $@
16 if [ -f fallback/coreboot_apc ]; \
18 $(CBFSTOOL) $@ add-stage fallback/coreboot_apc $(CONFIG_CBFS_PREFIX)/coreboot_apc $(CBFS_COMPRESS_FLAG); \
20 $(CBFSTOOL) $@ add-stage $(obj)/coreboot_ram $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG)
21 ifeq ($(CONFIG_PAYLOAD_NONE),y)
22 @printf " PAYLOAD none (as specified by user)\n"
24 @printf " PAYLOAD $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CBFS_PAYLOAD_COMPRESS_FLAG)\n"
25 $(CBFSTOOL) $(obj)/coreboot.rom add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG)
27 ifeq ($(CONFIG_VGA_BIOS),y)
28 @printf " VGABIOS $(CONFIG_FALLBACK_VGA_BIOS_FILE) $(CONFIG_FALLBACK_VGA_BIOS_ID)\n"
29 $(CBFSTOOL) $(obj)/coreboot.rom add $(CONFIG_FALLBACK_VGA_BIOS_FILE) "pci$(CONFIG_FALLBACK_VGA_BIOS_ID).rom" optionrom
31 @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n"
32 $(CBFSTOOL) $(obj)/coreboot.rom print
34 #######################################################################
37 $(obj)/option_table.h $(obj)/option_table.c $(obj)/arch/i386/../../option_table.c: $(obj)/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout
38 @printf " OPTION $(subst $(obj)/,,$(@))\n"
39 $(obj)/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --header $(obj)/option_table.h --option $(obj)/option_table.c
41 $(obj)/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src/include/pc80/mc146818rtc.h $(top)/src/include/boot/coreboot_tables.h $(obj)/config.h
42 @printf " HOSTCC $(subst $(obj)/,,$(@))\n"
43 $(HOSTCC) $(HOSTCFLAGS) -include $(obj)/config.h $< -o $@
45 #######################################################################
46 # Build the coreboot_ram (stage 2)
48 $(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/arch/i386/coreboot_ram.ld #ldoptions
49 @printf " CC $(subst $(obj)/,,$(@))\n"
50 $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/i386/coreboot_ram.ld $(obj)/coreboot_ram.o
51 $(NM) -n $(obj)/coreboot_ram | sort > $(obj)/coreboot_ram.map
53 $(obj)/coreboot_ram.o: $(obj)/arch/i386/lib/c_start.o $(drivers) $(obj)/coreboot.a $(LIBGCC_FILE_NAME)
54 @printf " CC $(subst $(obj)/,,$(@))\n"
55 $(CC) -nostdlib -r -o $@ $(obj)/arch/i386/lib/c_start.o $(drivers) -Wl,-\( $(obj)/coreboot.a $(LIBGCC_FILE_NAME) -Wl,-\)
57 $(obj)/coreboot.a: $(objs)
58 @printf " AR $(subst $(obj)/,,$(@))\n"
59 rm -f $(obj)/coreboot.a
60 $(AR) cr $(obj)/coreboot.a $(objs)
62 #######################################################################
67 ldscripts += $(src)/arch/i386/init/ldscript_fallback_cbfs.lb
68 ldscripts += $(src)/arch/i386/lib/failover.lds
69 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
70 crt0s += $(src)/cpu/x86/16bit/entry16.inc
71 ldscripts += $(src)/cpu/x86/16bit/entry16.lds
73 crt0s += $(src)/cpu/x86/32bit/entry32.inc
74 ldscripts += $(src)/cpu/x86/32bit/entry32.lds
75 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
76 crt0s += $(src)/cpu/x86/16bit/reset16.inc
77 ldscripts += $(src)/cpu/x86/16bit/reset16.lds
78 ifeq ($(CONFIG_ROMCC),y)
79 crt0s += $(src)/arch/i386/lib/cpu_reset.inc
81 crt0s += $(src)/arch/i386/lib/id.inc
82 ldscripts += $(src)/arch/i386/lib/id.lds
85 crt0s += $(src)/cpu/x86/fpu_enable.inc
86 ifeq ($(CONFIG_CPU_AMD_GX1),y)
87 crt0s += $(src)/cpu/amd/model_gx1/cpu_setup.inc
88 crt0s += $(src)/cpu/amd/model_gx1/gx_setup.inc
90 ifeq ($(CONFIG_SSE),y)
91 crt0s += $(src)/cpu/x86/sse_enable.inc
94 ifeq ($(CONFIG_CPU_AMD_LX),y)
95 crt0s += $(src)/cpu/amd/model_lx/cache_as_ram.inc
97 ifeq ($(CONFIG_CPU_AMD_SOCKET_F),y)
98 crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
100 ifeq ($(CONFIG_CPU_AMD_SOCKET_F_1207),y)
101 crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
103 ifeq ($(CONFIG_CPU_AMD_SOCKET_AM2),y)
104 crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
106 ifeq ($(CONFIG_CPU_AMD_SOCKET_S1G1),y)
107 crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
109 ifeq ($(CONFIG_CPU_AMD_SOCKET_754),y)
110 crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
112 ifeq ($(CONFIG_CPU_AMD_SOCKET_939),y)
113 crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
115 ifeq ($(CONFIG_CPU_AMD_SOCKET_940),y)
116 crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
118 ifeq ($(CONFIG_CPU_INTEL_CORE),y)
119 crt0s += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
121 # Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
122 ifeq ($(CONFIG_CPU_INTEL_SOCKET_BGA956),y)
123 crt0s += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
125 # should be CONFIG_CPU_VIA_C7, but bcom/winnetp680, jetway/j7f24, via/epia-cn, via/pc2500e don't use CAR yet
126 ifeq ($(CONFIG_BOARD_VIA_VT8454C),y)
127 crt0s += $(src)/cpu/via/car/cache_as_ram.inc
129 ifeq ($(CONFIG_BOARD_VIA_EPIA_M700),y)
130 crt0s += $(src)/cpu/via/car/cache_as_ram.inc
132 # who else could use this?
133 ifeq ($(CONFIG_BOARD_TYAN_S2735),y)
134 crt0s += $(src)/cpu/x86/car/cache_as_ram.inc
135 ldscripts += $(src)/cpu/x86/car/cache_as_ram.lds
138 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
139 ifeq ($(CONFIG_ROMCC),y)
140 crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc
143 crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
145 ifeq ($(CONFIG_SSE),y)
146 crt0s += $(src)/cpu/x86/sse_disable.inc
148 ifeq ($(CONFIG_MMX),y)
149 crt0s += $(src)/cpu/x86/mmx_disable.inc
152 ifeq ($(CONFIG_AP_CODE_IN_CAR),y)
153 ldscripts += $(src)/arch/i386/init/ldscript_apc.lb
156 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
157 ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_CK804),y)
158 crt0s += $(src)/southbridge/nvidia/ck804/romstrap.inc
159 ldscripts += $(src)/southbridge/nvidia/ck804/romstrap.lds
161 ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55),y)
162 crt0s += $(src)/southbridge/nvidia/mcp55/romstrap.inc
163 ldscripts += $(src)/southbridge/nvidia/mcp55/romstrap.lds
165 ifeq ($(CONFIG_SOUTHBRIDGE_VIA_K8T890),y)
166 crt0s += $(src)/southbridge/via/k8t890/romstrap.inc
167 ldscripts += $(src)/southbridge/via/k8t890/romstrap.lds
169 ifeq ($(CONFIG_NORTHBRIDGE_VIA_VX800),y)
170 crt0s += $(src)/northbridge/via/vx800/romstrap.inc
171 ldscripts += $(src)/northbridge/via/vx800/romstrap.lds
176 ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
177 OPTION_TABLE_H:=$(obj)/option_table.h
180 ifeq ($(CONFIG_ROMCC),y)
181 ROMCCFLAGS ?= -mcpu=p2 -O2
183 $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c
184 $(obj)/romcc $(ROMCCFLAGS) --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@
186 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/romcc $(OPTION_TABLE_H) $(obj)/build.h
187 $(obj)/romcc $(ROMCCFLAGS) -include $(obj)/build.h $(INCLUDES) $< -o $@
191 $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(obj)/option_table.h
192 $(CC) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
194 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h
195 $(CC) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -include $(obj)/build.h -I$(src) -I. -c -S $< -o $@.tmp1
196 sed -e 's/\.rodata/.rom.data/g' -e 's/\.text/.section .rom.text/g' $@.tmp1 > $@.tmp
202 ifeq ($(CONFIG_TINY_BOOTBLOCK),y)
203 include $(src)/arch/i386/Makefile.bootblock.inc
205 include $(src)/arch/i386/Makefile.bigbootblock.inc