2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
85 source src/mainboard/Kconfig
86 source src/arch/i386/Kconfig
91 source src/cpu/Kconfig
94 menu "HyperTransport setup"
95 depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
98 prompt "HyperTransport frequency"
99 default LIMIT_HT_SPEED_AUTO
101 This option sets the maximum permissible HyperTransport link
104 Use of this option will only limit the autodetected HT frequency.
105 It will not (and cannot) increase the frequency beyond the
108 This is primarily used to work around poorly designed or laid out
109 HT traces on certain motherboards.
111 config LIMIT_HT_SPEED_200
112 bool "Limit HT frequency to 200MHz"
113 config LIMIT_HT_SPEED_400
114 bool "Limit HT frequency to 400MHz"
115 config LIMIT_HT_SPEED_600
116 bool "Limit HT frequency to 600MHz"
117 config LIMIT_HT_SPEED_800
118 bool "Limit HT frequency to 800MHz"
119 config LIMIT_HT_SPEED_1000
120 bool "Limit HT frequency to 1.0GHz"
121 config LIMIT_HT_SPEED_1200
122 bool "Limit HT frequency to 1.2GHz"
123 config LIMIT_HT_SPEED_1400
124 bool "Limit HT frequency to 1.4GHz"
125 config LIMIT_HT_SPEED_1600
126 bool "Limit HT frequency to 1.6GHz"
127 config LIMIT_HT_SPEED_1800
128 bool "Limit HT frequency to 1.8GHz"
129 config LIMIT_HT_SPEED_2000
130 bool "Limit HT frequency to 2.0GHz"
131 config LIMIT_HT_SPEED_2200
132 bool "Limit HT frequency to 2.2GHz"
133 config LIMIT_HT_SPEED_2400
134 bool "Limit HT frequency to 2.4GHz"
135 config LIMIT_HT_SPEED_2600
136 bool "Limit HT frequency to 2.6GHz"
137 config LIMIT_HT_SPEED_AUTO
138 bool "Autodetect HT frequency"
142 prompt "HyperTransport downlink width"
143 default LIMIT_HT_DOWN_WIDTH_16
145 This option sets the maximum permissible HyperTransport
148 Use of this option will only limit the autodetected HT width.
149 It will not (and cannot) increase the width beyond the autodetected
152 This is primarily used to work around poorly designed or laid out HT
153 traces on certain motherboards.
155 config LIMIT_HT_DOWN_WIDTH_8
157 config LIMIT_HT_DOWN_WIDTH_16
162 prompt "HyperTransport uplink width"
163 default LIMIT_HT_UP_WIDTH_16
165 This option sets the maximum permissible HyperTransport
168 Use of this option will only limit the autodetected HT width.
169 It will not (and cannot) increase the width beyond the autodetected
172 This is primarily used to work around poorly designed or laid out HT
173 traces on certain motherboards.
175 config LIMIT_HT_UP_WIDTH_8
177 config LIMIT_HT_UP_WIDTH_16
183 source src/northbridge/Kconfig
184 comment "Southbridge"
185 source src/southbridge/Kconfig
187 source src/superio/Kconfig
189 source src/devices/Kconfig
193 config PCI_BUS_SEGN_BITS
197 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
201 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
217 config LB_CKS_RANGE_START
221 config LB_CKS_RANGE_END
245 config USE_PRINTK_IN_CAR
249 config USE_OPTION_TABLE
257 config MMCONF_SUPPORT_DEFAULT
261 config MMCONF_SUPPORT
272 source src/console/Kconfig
274 config HAVE_ACPI_RESUME
278 config ACPI_SSDTX_NUM
282 config HAVE_HARD_RESET
284 default y if BOARD_HAS_HARD_RESET
287 This variable specifies whether a given board has a hard_reset
288 function, no matter if it's provided by board code or chipset code.
290 config HAVE_INIT_TIMER
292 default n if UDELAY_IO
295 config HAVE_MAINBOARD_RESOURCES
299 config HAVE_OPTION_TABLE
303 This variable specifies whether a given board has a cmos.layout
304 file containing NVRAM/CMOS bit definitions.
305 It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
311 config HAVE_SMI_HANDLER
315 config PCI_IO_CFG_EXT
323 # TODO: Can probably be removed once all chipsets have kconfig options for it.
328 config USE_WATCHDOG_ON_BOOT
336 Build board-specific VGA code.
342 Enable Unified Memory Architecture for graphics.
349 #TODO Remove this option or make it useful.
350 config HAVE_LOW_TABLES
354 This Option is unused in the code. Since two boards try to set it to
355 'n', they may be broken. We either need to make the option useful or
356 get rid of it. The broken boards are:
360 config HAVE_HIGH_TABLES
364 This variable specifies whether a given northbridge has high table
366 It is set in northbridge/*/Kconfig.
367 Whether or not the high tables are actually written by coreboot is
368 configurable by the user via WRITE_HIGH_TABLES.
370 config HAVE_ACPI_TABLES
373 This variable specifies whether a given board has ACPI table support.
374 It is usually set in mainboard/*/Kconfig.
375 Whether or not the ACPI tables are actually generated by coreboot
376 is configurable by the user via GENERATE_ACPI_TABLES.
381 This variable specifies whether a given board has MP table support.
382 It is usually set in mainboard/*/Kconfig.
383 Whether or not the MP table is actually generated by coreboot
384 is configurable by the user via GENERATE_MP_TABLE.
386 config HAVE_PIRQ_TABLE
389 This variable specifies whether a given board has PIRQ table support.
390 It is usually set in mainboard/*/Kconfig.
391 Whether or not the PIRQ table is actually generated by coreboot
392 is configurable by the user via GENERATE_PIRQ_TABLE.
394 #These Options are here to avoid "undefined" warnings.
395 #The actual selection and help texts are in the following menu.
397 config GENERATE_ACPI_TABLES
399 default HAVE_ACPI_TABLES
401 config GENERATE_MP_TABLE
403 default HAVE_MP_TABLE
405 config GENERATE_PIRQ_TABLE
407 default HAVE_PIRQ_TABLE
409 config WRITE_HIGH_TABLES
411 default HAVE_HIGH_TABLES
415 config WRITE_HIGH_TABLES
416 bool "Write 'high' tables to avoid being overwritten in F segment"
417 depends on HAVE_HIGH_TABLES
421 bool "Generate Multiboot tables (for GRUB2)"
424 config GENERATE_ACPI_TABLES
425 depends on HAVE_ACPI_TABLES
426 bool "Generate ACPI tables"
429 Generate ACPI tables for this board.
433 config GENERATE_MP_TABLE
434 depends on HAVE_MP_TABLE
435 bool "Generate an MP table"
438 Generate an MP table (conforming to the Intel MultiProcessor
439 specification 1.4) for this board.
443 config GENERATE_PIRQ_TABLE
444 depends on HAVE_PIRQ_TABLE
445 bool "Generate a PIRQ table"
448 Generate a PIRQ table for this board.
457 prompt "Add a payload"
463 Select this option if you want to create an "empty" coreboot
464 ROM image for a certain mainboard, i.e. a coreboot ROM image
465 which does not yet contain a payload.
467 For such an image to be useful, you have to use 'cbfstool'
468 to add a payload to the ROM image later.
471 bool "An ELF executable payload"
473 Select this option if you have a payload image (an ELF file)
474 which coreboot should run as soon as the basic hardware
475 initialization is completed.
477 You will be able to specify the location and file name of the
482 config FALLBACK_PAYLOAD_FILE
483 string "Payload path and filename"
484 depends on PAYLOAD_ELF
485 default "payload.elf"
487 The path and filename of the ELF executable file to use as payload.
489 # TODO: Defined if no payload? Breaks build?
490 config COMPRESSED_PAYLOAD_LZMA
491 bool "Use LZMA compression for payloads"
493 depends on PAYLOAD_ELF
495 In order to reduce the size payloads take up in the ROM chip
496 coreboot can compress them using the LZMA algorithm.
498 config COMPRESSED_PAYLOAD_NRV2B
507 bool "Add a VGA BIOS image"
509 Select this option if you have a VGA BIOS image that you would
510 like to add to your ROM.
512 You will be able to specify the location and file name of the
515 config FALLBACK_VGA_BIOS_FILE
516 string "VGA BIOS path and filename"
518 default "vgabios.bin"
520 The path and filename of the file to use as VGA BIOS.
522 config FALLBACK_VGA_BIOS_ID
523 string "VGA device PCI IDs"
527 The comma-separated PCI vendor and device ID that would associate
528 your VGA BIOS to your video card.
532 In the above example 1106 is the PCI vendor ID (in hex, but without
533 the "0x" prefix) and 3230 specifies the PCI device ID of the
534 video card (also in hex, without "0x" prefix).
537 bool "Add an MBI image"
538 depends on NORTHBRIDGE_INTEL_I82830
540 Select this option if you have an Intel MBI image that you would
541 like to add to your ROM.
543 You will be able to specify the location and file name of the
546 config FALLBACK_MBI_FILE
547 string "Intel MBI path and filename"
551 The path and filename of the file to use as VGA BIOS.
556 depends on PCI_OPTION_ROM_RUN_YABEL
559 prompt "Show graphical bootsplash"
561 depends on PCI_OPTION_ROM_RUN_YABEL
563 This option shows a graphical bootsplash screen. The grapics are
564 loaded from the CBFS file bootsplash.jpg.
566 config FALLBACK_BOOTSPLASH_FILE
567 string "Bootsplash path and filename"
568 depends on BOOTSPLASH
569 default "bootsplash.jpg"
571 The path and filename of the file to use as graphical bootsplash
572 screen. The file format has to be jpg.
574 # TODO: Turn this into a "choice".
575 config FRAMEBUFFER_VESA_MODE
576 prompt "VESA framebuffer video mode"
579 depends on BOOTSPLASH
581 This option sets the resolution used for the coreboot framebuffer and
582 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
583 some day make this a "choice".
585 config COREBOOT_KEEP_FRAMEBUFFER
586 prompt "Keep VESA framebuffer"
588 depends on BOOTSPLASH
590 This option keeps the framebuffer mode set after coreboot finishes
591 execution. If this option is enabled, coreboot will pass a
592 framebuffer entry in its coreboot table and the payload will need a
593 framebuffer driver. If this option is disabled, coreboot will switch
594 back to text mode before handing control to a payload.
600 # TODO: Better help text and detailed instructions.
602 bool "GDB debugging support"
605 If enabled, you will be able to set breakpoints for gdb debugging.
606 See src/arch/i386/lib/c_start.S for details.
608 config DEBUG_RAM_SETUP
609 bool "Output verbose RAM init debug messages"
611 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
612 || NORTHBRIDGE_AMD_AMDK8 \
613 || NORTHBRIDGE_VIA_CN700 \
614 || NORTHBRIDGE_VIA_CX700 \
615 || NORTHBRIDGE_VIA_VX800 \
616 || NORTHBRIDGE_INTEL_E7501 \
617 || NORTHBRIDGE_INTEL_I440BX \
618 || NORTHBRIDGE_INTEL_I82810 \
619 || NORTHBRIDGE_INTEL_I82830 \
620 || NORTHBRIDGE_INTEL_I945)
622 This option enables additional RAM init related debug messages.
623 It is recommended to enable this when debugging issues on your
624 board which might be RAM init related.
626 Note: This option will increase the size of the coreboot image.
631 bool "Output verbose SMBus debug messages"
633 depends on (SOUTHBRIDGE_VIA_VT8237R \
634 || NORTHBRIDGE_VIA_VX800 \
635 || NORTHBRIDGE_VIA_CX700 \
636 || NORTHBRIDGE_AMD_AMDK8)
638 This option enables additional SMBus (and SPD) debug messages.
640 Note: This option will increase the size of the coreboot image.
645 bool "Output verbose SMI debug messages"
647 depends on HAVE_SMI_HANDLER
649 This option enables additional SMI related debug messages.
651 Note: This option will increase the size of the coreboot image.
656 bool "Output verbose x86emu debug messages"
658 depends on PCI_OPTION_ROM_RUN_YABEL
660 This option enables additional x86emu related debug messages.
662 Note: This option will increase the size of the coreboot image.
666 config X86EMU_DEBUG_JMP
667 bool "Trace JMP/RETF"
669 depends on X86EMU_DEBUG
671 Print information about JMP and RETF opcodes from x86emu.
673 Note: This option will increase the size of the coreboot image.
677 config X86EMU_DEBUG_TRACE
678 bool "Trace all opcodes"
680 depends on X86EMU_DEBUG
682 Print _all_ opcodes that are executed by x86emu.
684 WARNING: This will produce a LOT of output and take a long time.
686 Note: This option will increase the size of the coreboot image.
690 config X86EMU_DEBUG_PNP
691 bool "Log Plug&Play accesses"
693 depends on X86EMU_DEBUG
695 Print Plug And Play accesses made by option ROMs.
697 Note: This option will increase the size of the coreboot image.
701 config X86EMU_DEBUG_DISK
704 depends on X86EMU_DEBUG
706 Print Disk I/O related messages.
708 Note: This option will increase the size of the coreboot image.
712 config X86EMU_DEBUG_PMM
715 depends on X86EMU_DEBUG
717 Print messages related to POST Memory Manager (PMM).
719 Note: This option will increase the size of the coreboot image.
724 config X86EMU_DEBUG_VBE
725 bool "Debug VESA BIOS Extensions"
727 depends on X86EMU_DEBUG
729 Print messages related to VESA BIOS Extension (VBE) functions.
731 Note: This option will increase the size of the coreboot image.
735 config X86EMU_DEBUG_INT10
736 bool "Redirect INT10 output to console"
738 depends on X86EMU_DEBUG
740 Let INT10 (i.e. character output) calls print messages to debug output.
742 Note: This option will increase the size of the coreboot image.
746 config X86EMU_DEBUG_INTERRUPTS
747 bool "Log intXX calls"
749 depends on X86EMU_DEBUG
751 Print messages related to interrupt handling.
753 Note: This option will increase the size of the coreboot image.
757 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
758 bool "Log special memory accesses"
760 depends on X86EMU_DEBUG
762 Print messages related to accesses to certain areas of the virtual
763 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
765 Note: This option will increase the size of the coreboot image.
769 config X86EMU_DEBUG_MEM
770 bool "Log all memory accesses"
772 depends on X86EMU_DEBUG
774 Print memory accesses made by option ROM.
775 Note: This also includes accesses to fetch instructions.
777 Note: This option will increase the size of the coreboot image.
781 config X86EMU_DEBUG_IO
782 bool "Log IO accesses"
784 depends on X86EMU_DEBUG
786 Print I/O accesses made by option ROM.
788 Note: This option will increase the size of the coreboot image.
793 bool "Built-in low-level shell"
796 If enabled, you will have a low level shell to examine your machine.
797 Put llshell() in your (romstage) code to start the shell.
798 See src/arch/i386/llshell/llshell.inc for details.
802 config LIFT_BSP_APIC_ID
806 # These probably belong somewhere else, but they are needed somewhere.
807 config AP_CODE_IN_CAR
815 config ENABLE_APIC_EXT_ID
819 config WARNINGS_ARE_ERRORS
823 config ID_SECTION_OFFSET
827 source src/Kconfig.deprecated_options