2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
85 source src/mainboard/Kconfig
86 source src/arch/i386/Kconfig
91 source src/cpu/Kconfig
93 source src/northbridge/Kconfig
95 source src/southbridge/Kconfig
97 source src/superio/Kconfig
99 source src/devices/Kconfig
103 config PCI_BUS_SEGN_BITS
107 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
111 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
135 config USE_PRINTK_IN_CAR
139 config USE_OPTION_TABLE
147 config MMCONF_SUPPORT_DEFAULT
151 config MMCONF_SUPPORT
162 source src/console/Kconfig
164 config HAVE_ACPI_RESUME
168 config ACPI_SSDTX_NUM
172 config HAVE_HARD_RESET
174 default y if BOARD_HAS_HARD_RESET
177 This variable specifies whether a given board has a hard_reset
178 function, no matter if it's provided by board code or chipset code.
180 config HAVE_INIT_TIMER
182 default n if UDELAY_IO
185 config HAVE_MAINBOARD_RESOURCES
189 config HAVE_OPTION_TABLE
193 This variable specifies whether a given board has a cmos.layout
194 file containing NVRAM/CMOS bit definitions.
195 It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
201 config HAVE_SMI_HANDLER
205 config PCI_IO_CFG_EXT
213 # TODO: Can probably be removed once all chipsets have kconfig options for it.
218 config USE_WATCHDOG_ON_BOOT
226 Build board-specific VGA code.
232 Enable Unified Memory Architecture for graphics.
239 #TODO Remove this option or make it useful.
240 config HAVE_LOW_TABLES
244 This Option is unused in the code. Since two boards try to set it to
245 'n', they may be broken. We either need to make the option useful or
246 get rid of it. The broken boards are:
250 config HAVE_HIGH_TABLES
254 This variable specifies whether a given northbridge has high table
256 It is set in northbridge/*/Kconfig.
257 Whether or not the high tables are actually written by coreboot is
258 configurable by the user via WRITE_HIGH_TABLES.
260 config HAVE_ACPI_TABLES
263 This variable specifies whether a given board has ACPI table support.
264 It is usually set in mainboard/*/Kconfig.
265 Whether or not the ACPI tables are actually generated by coreboot
266 is configurable by the user via GENERATE_ACPI_TABLES.
271 This variable specifies whether a given board has MP table support.
272 It is usually set in mainboard/*/Kconfig.
273 Whether or not the MP table is actually generated by coreboot
274 is configurable by the user via GENERATE_MP_TABLE.
276 config HAVE_PIRQ_TABLE
279 This variable specifies whether a given board has PIRQ table support.
280 It is usually set in mainboard/*/Kconfig.
281 Whether or not the PIRQ table is actually generated by coreboot
282 is configurable by the user via GENERATE_PIRQ_TABLE.
284 #These Options are here to avoid "undefined" warnings.
285 #The actual selection and help texts are in the following menu.
287 config GENERATE_ACPI_TABLES
289 default HAVE_ACPI_TABLES
291 config GENERATE_MP_TABLE
293 default HAVE_MP_TABLE
295 config GENERATE_PIRQ_TABLE
297 default HAVE_PIRQ_TABLE
299 config WRITE_HIGH_TABLES
301 default HAVE_HIGH_TABLES
305 config WRITE_HIGH_TABLES
306 bool "Write 'high' tables to avoid being overwritten in F segment"
307 depends on HAVE_HIGH_TABLES
311 bool "Generate Multiboot tables (for GRUB2)"
314 config GENERATE_ACPI_TABLES
315 depends on HAVE_ACPI_TABLES
316 bool "Generate ACPI tables"
319 Generate ACPI tables for this board.
323 config GENERATE_MP_TABLE
324 depends on HAVE_MP_TABLE
325 bool "Generate an MP table"
328 Generate an MP table (conforming to the Intel MultiProcessor
329 specification 1.4) for this board.
333 config GENERATE_PIRQ_TABLE
334 depends on HAVE_PIRQ_TABLE
335 bool "Generate a PIRQ table"
338 Generate a PIRQ table for this board.
347 prompt "Add a payload"
353 Select this option if you want to create an "empty" coreboot
354 ROM image for a certain mainboard, i.e. a coreboot ROM image
355 which does not yet contain a payload.
357 For such an image to be useful, you have to use 'cbfstool'
358 to add a payload to the ROM image later.
361 bool "An ELF executable payload"
363 Select this option if you have a payload image (an ELF file)
364 which coreboot should run as soon as the basic hardware
365 initialization is completed.
367 You will be able to specify the location and file name of the
372 config FALLBACK_PAYLOAD_FILE
373 string "Payload path and filename"
374 depends on PAYLOAD_ELF
375 default "payload.elf"
377 The path and filename of the ELF executable file to use as payload.
379 # TODO: Defined if no payload? Breaks build?
380 config COMPRESSED_PAYLOAD_LZMA
381 bool "Use LZMA compression for payloads"
383 depends on PAYLOAD_ELF
385 In order to reduce the size payloads take up in the ROM chip
386 coreboot can compress them using the LZMA algorithm.
388 config COMPRESSED_PAYLOAD_NRV2B
397 bool "Add a VGA BIOS image"
399 Select this option if you have a VGA BIOS image that you would
400 like to add to your ROM.
402 You will be able to specify the location and file name of the
405 config FALLBACK_VGA_BIOS_FILE
406 string "VGA BIOS path and filename"
408 default "vgabios.bin"
410 The path and filename of the file to use as VGA BIOS.
412 config FALLBACK_VGA_BIOS_ID
413 string "VGA device PCI IDs"
417 The comma-separated PCI vendor and device ID that would associate
418 your VGA BIOS to your video card.
422 In the above example 1106 is the PCI vendor ID (in hex, but without
423 the "0x" prefix) and 3230 specifies the PCI device ID of the
424 video card (also in hex, without "0x" prefix).
427 bool "Add an MBI image"
428 depends on NORTHBRIDGE_INTEL_I82830
430 Select this option if you have an Intel MBI image that you would
431 like to add to your ROM.
433 You will be able to specify the location and file name of the
436 config FALLBACK_MBI_FILE
437 string "Intel MBI path and filename"
441 The path and filename of the file to use as VGA BIOS.
446 depends on PCI_OPTION_ROM_RUN_YABEL
449 prompt "Show graphical bootsplash"
451 depends on PCI_OPTION_ROM_RUN_YABEL
453 This option shows a graphical bootsplash screen. The grapics are
454 loaded from the CBFS file bootsplash.jpg.
456 config FALLBACK_BOOTSPLASH_FILE
457 string "Bootsplash path and filename"
458 depends on BOOTSPLASH
459 default "bootsplash.jpg"
461 The path and filename of the file to use as graphical bootsplash
462 screen. The file format has to be jpg.
464 # TODO: Turn this into a "choice".
465 config FRAMEBUFFER_VESA_MODE
466 prompt "VESA framebuffer video mode"
469 depends on BOOTSPLASH
471 This option sets the resolution used for the coreboot framebuffer and
472 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
473 some day make this a "choice".
475 config COREBOOT_KEEP_FRAMEBUFFER
476 prompt "Keep VESA framebuffer"
478 depends on BOOTSPLASH
480 This option keeps the framebuffer mode set after coreboot finishes
481 execution. If this option is enabled, coreboot will pass a
482 framebuffer entry in its coreboot table and the payload will need a
483 framebuffer driver. If this option is disabled, coreboot will switch
484 back to text mode before handing control to a payload.
490 # TODO: Better help text and detailed instructions.
492 bool "GDB debugging support"
495 If enabled, you will be able to set breakpoints for gdb debugging.
496 See src/arch/i386/lib/c_start.S for details.
498 config DEBUG_RAM_SETUP
499 bool "Output verbose RAM init debug messages"
501 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
502 || NORTHBRIDGE_AMD_AMDK8 \
503 || NORTHBRIDGE_VIA_CN700 \
504 || NORTHBRIDGE_VIA_CX700 \
505 || NORTHBRIDGE_VIA_VX800 \
506 || NORTHBRIDGE_INTEL_E7501 \
507 || NORTHBRIDGE_INTEL_I440BX \
508 || NORTHBRIDGE_INTEL_I82810 \
509 || NORTHBRIDGE_INTEL_I82830 \
510 || NORTHBRIDGE_INTEL_I945)
512 This option enables additional RAM init related debug messages.
513 It is recommended to enable this when debugging issues on your
514 board which might be RAM init related.
516 Note: This option will increase the size of the coreboot image.
521 bool "Output verbose SMBus debug messages"
523 depends on (SOUTHBRIDGE_VIA_VT8237R \
524 || NORTHBRIDGE_VIA_VX800 \
525 || NORTHBRIDGE_VIA_CX700 \
526 || NORTHBRIDGE_AMD_AMDK8 \
527 || NORTHBRIDGE_AMD_AMDFAM10 \
528 || SOUTHBRIDGE_VIA_VT8231)
530 This option enables additional SMBus (and SPD) debug messages.
532 Note: This option will increase the size of the coreboot image.
537 bool "Output verbose SMI debug messages"
539 depends on HAVE_SMI_HANDLER
541 This option enables additional SMI related debug messages.
543 Note: This option will increase the size of the coreboot image.
548 bool "Output verbose x86emu debug messages"
550 depends on PCI_OPTION_ROM_RUN_YABEL
552 This option enables additional x86emu related debug messages.
554 Note: This option will increase the size of the coreboot image.
558 config X86EMU_DEBUG_JMP
559 bool "Trace JMP/RETF"
561 depends on X86EMU_DEBUG
563 Print information about JMP and RETF opcodes from x86emu.
565 Note: This option will increase the size of the coreboot image.
569 config X86EMU_DEBUG_TRACE
570 bool "Trace all opcodes"
572 depends on X86EMU_DEBUG
574 Print _all_ opcodes that are executed by x86emu.
576 WARNING: This will produce a LOT of output and take a long time.
578 Note: This option will increase the size of the coreboot image.
582 config X86EMU_DEBUG_PNP
583 bool "Log Plug&Play accesses"
585 depends on X86EMU_DEBUG
587 Print Plug And Play accesses made by option ROMs.
589 Note: This option will increase the size of the coreboot image.
593 config X86EMU_DEBUG_DISK
596 depends on X86EMU_DEBUG
598 Print Disk I/O related messages.
600 Note: This option will increase the size of the coreboot image.
604 config X86EMU_DEBUG_PMM
607 depends on X86EMU_DEBUG
609 Print messages related to POST Memory Manager (PMM).
611 Note: This option will increase the size of the coreboot image.
616 config X86EMU_DEBUG_VBE
617 bool "Debug VESA BIOS Extensions"
619 depends on X86EMU_DEBUG
621 Print messages related to VESA BIOS Extension (VBE) functions.
623 Note: This option will increase the size of the coreboot image.
627 config X86EMU_DEBUG_INT10
628 bool "Redirect INT10 output to console"
630 depends on X86EMU_DEBUG
632 Let INT10 (i.e. character output) calls print messages to debug output.
634 Note: This option will increase the size of the coreboot image.
638 config X86EMU_DEBUG_INTERRUPTS
639 bool "Log intXX calls"
641 depends on X86EMU_DEBUG
643 Print messages related to interrupt handling.
645 Note: This option will increase the size of the coreboot image.
649 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
650 bool "Log special memory accesses"
652 depends on X86EMU_DEBUG
654 Print messages related to accesses to certain areas of the virtual
655 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
657 Note: This option will increase the size of the coreboot image.
661 config X86EMU_DEBUG_MEM
662 bool "Log all memory accesses"
664 depends on X86EMU_DEBUG
666 Print memory accesses made by option ROM.
667 Note: This also includes accesses to fetch instructions.
669 Note: This option will increase the size of the coreboot image.
673 config X86EMU_DEBUG_IO
674 bool "Log IO accesses"
676 depends on X86EMU_DEBUG
678 Print I/O accesses made by option ROM.
680 Note: This option will increase the size of the coreboot image.
685 bool "Built-in low-level shell"
688 If enabled, you will have a low level shell to examine your machine.
689 Put llshell() in your (romstage) code to start the shell.
690 See src/arch/i386/llshell/llshell.inc for details.
694 config LIFT_BSP_APIC_ID
698 # These probably belong somewhere else, but they are needed somewhere.
699 config AP_CODE_IN_CAR
703 config ENABLE_APIC_EXT_ID
707 config WARNINGS_ARE_ERRORS
711 config ID_SECTION_OFFSET
715 source src/Kconfig.deprecated_options