2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
83 config SCONFIG_GENPARSER
84 bool "Generate SCONFIG parser using flex and bison"
88 Enable this option if you are working on the sconfig
89 device tree parser and made changes to sconfig.l and
93 config USE_OPTION_TABLE
94 bool "Use CMOS for configuration values"
96 depends on HAVE_OPTION_TABLE
98 Enable this option if coreboot shall read options from the "CMOS"
99 NVRAM instead of using hard coded values.
103 source src/mainboard/Kconfig
105 # This option is used to set the architecture of a mainboard to X86.
106 # It is usually set in mainboard/*/Kconfig.
112 source src/arch/x86/Kconfig
118 source src/cpu/Kconfig
119 comment "Northbridge"
120 source src/northbridge/Kconfig
121 comment "Southbridge"
122 source src/southbridge/Kconfig
124 source src/superio/Kconfig
126 source src/devices/Kconfig
130 menu "Generic Drivers"
131 source src/drivers/Kconfig
134 config PCI_BUS_SEGN_BITS
138 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
142 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
157 config MMCONF_SUPPORT_DEFAULT
161 config MMCONF_SUPPORT
168 source src/console/Kconfig
170 config HAVE_ACPI_RESUME
174 config HAVE_ACPI_SLIC
178 config ACPI_SSDTX_NUM
182 config HAVE_HARD_RESET
184 default y if BOARD_HAS_HARD_RESET
187 This variable specifies whether a given board has a hard_reset
188 function, no matter if it's provided by board code or chipset code.
190 config HAVE_INIT_TIMER
192 default n if UDELAY_IO
195 config HAVE_MAINBOARD_RESOURCES
199 config USE_OPTION_TABLE
203 config HAVE_OPTION_TABLE
207 This variable specifies whether a given board has a cmos.layout
208 file containing NVRAM/CMOS bit definitions.
209 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
215 config HAVE_SMI_HANDLER
219 config PCI_IO_CFG_EXT
227 # TODO: Can probably be removed once all chipsets have kconfig options for it.
232 config USE_WATCHDOG_ON_BOOT
240 Build board-specific VGA code.
246 Enable Unified Memory Architecture for graphics.
253 config HAVE_ACPI_TABLES
256 This variable specifies whether a given board has ACPI table support.
257 It is usually set in mainboard/*/Kconfig.
258 Whether or not the ACPI tables are actually generated by coreboot
259 is configurable by the user via GENERATE_ACPI_TABLES.
264 This variable specifies whether a given board has MP table support.
265 It is usually set in mainboard/*/Kconfig.
266 Whether or not the MP table is actually generated by coreboot
267 is configurable by the user via GENERATE_MP_TABLE.
269 config HAVE_PIRQ_TABLE
272 This variable specifies whether a given board has PIRQ table support.
273 It is usually set in mainboard/*/Kconfig.
274 Whether or not the PIRQ table is actually generated by coreboot
275 is configurable by the user via GENERATE_PIRQ_TABLE.
277 #These Options are here to avoid "undefined" warnings.
278 #The actual selection and help texts are in the following menu.
280 config GENERATE_ACPI_TABLES
282 default HAVE_ACPI_TABLES
284 config GENERATE_MP_TABLE
286 default HAVE_MP_TABLE
288 config GENERATE_PIRQ_TABLE
290 default HAVE_PIRQ_TABLE
294 config WRITE_HIGH_TABLES
295 bool "Write 'high' tables to avoid being overwritten in F segment"
299 bool "Generate Multiboot tables (for GRUB2)"
302 config GENERATE_ACPI_TABLES
303 depends on HAVE_ACPI_TABLES
304 bool "Generate ACPI tables"
307 Generate ACPI tables for this board.
311 config GENERATE_MP_TABLE
312 depends on HAVE_MP_TABLE
313 bool "Generate an MP table"
316 Generate an MP table (conforming to the Intel MultiProcessor
317 specification 1.4) for this board.
321 config GENERATE_PIRQ_TABLE
322 depends on HAVE_PIRQ_TABLE
323 bool "Generate a PIRQ table"
326 Generate a PIRQ table for this board.
335 prompt "Add a payload"
336 default PAYLOAD_NONE if !ARCH_X86
337 default PAYLOAD_SEABIOS if ARCH_X86
342 Select this option if you want to create an "empty" coreboot
343 ROM image for a certain mainboard, i.e. a coreboot ROM image
344 which does not yet contain a payload.
346 For such an image to be useful, you have to use 'cbfstool'
347 to add a payload to the ROM image later.
350 bool "An ELF executable payload"
352 Select this option if you have a payload image (an ELF file)
353 which coreboot should run as soon as the basic hardware
354 initialization is completed.
356 You will be able to specify the location and file name of the
359 config PAYLOAD_SEABIOS
363 Select this option if you want to build a coreboot image
364 with a SeaBIOS payload. If you don't know what this is
365 about, just leave it enabled.
367 See http://coreboot.org/Payloads for more information.
372 prompt "SeaBIOS version"
373 default SEABIOS_STABLE
374 depends on PAYLOAD_SEABIOS
376 config SEABIOS_STABLE
379 Stable SeaBIOS version
380 config SEABIOS_MASTER
383 Newest SeaBIOS version
387 string "Payload path and filename"
388 depends on PAYLOAD_ELF
389 default "payload.elf"
391 The path and filename of the ELF executable file to use as payload.
394 depends on PAYLOAD_SEABIOS
395 default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
397 # TODO: Defined if no payload? Breaks build?
398 config COMPRESSED_PAYLOAD_LZMA
399 bool "Use LZMA compression for payloads"
401 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS
403 In order to reduce the size payloads take up in the ROM chip
404 coreboot can compress them using the LZMA algorithm.
406 config COMPRESSED_PAYLOAD_NRV2B
415 bool "Add a VGA BIOS image"
417 Select this option if you have a VGA BIOS image that you would
418 like to add to your ROM.
420 You will be able to specify the location and file name of the
424 string "VGA BIOS path and filename"
426 default "vgabios.bin"
428 The path and filename of the file to use as VGA BIOS.
431 string "VGA device PCI IDs"
435 The comma-separated PCI vendor and device ID that would associate
436 your VGA BIOS to your video card.
440 In the above example 1106 is the PCI vendor ID (in hex, but without
441 the "0x" prefix) and 3230 specifies the PCI device ID of the
442 video card (also in hex, without "0x" prefix).
445 bool "Add an MBI image"
446 depends on NORTHBRIDGE_INTEL_I82830
448 Select this option if you have an Intel MBI image that you would
449 like to add to your ROM.
451 You will be able to specify the location and file name of the
455 string "Intel MBI path and filename"
459 The path and filename of the file to use as VGA BIOS.
464 depends on PCI_OPTION_ROM_RUN_YABEL
467 prompt "Show graphical bootsplash"
469 depends on PCI_OPTION_ROM_RUN_YABEL
471 This option shows a graphical bootsplash screen. The grapics are
472 loaded from the CBFS file bootsplash.jpg.
474 config BOOTSPLASH_FILE
475 string "Bootsplash path and filename"
476 depends on BOOTSPLASH
477 default "bootsplash.jpg"
479 The path and filename of the file to use as graphical bootsplash
480 screen. The file format has to be jpg.
482 # TODO: Turn this into a "choice".
483 config FRAMEBUFFER_VESA_MODE
484 prompt "VESA framebuffer video mode"
487 depends on BOOTSPLASH
489 This option sets the resolution used for the coreboot framebuffer and
490 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
491 some day make this a "choice".
493 config COREBOOT_KEEP_FRAMEBUFFER
494 prompt "Keep VESA framebuffer"
496 depends on BOOTSPLASH
498 This option keeps the framebuffer mode set after coreboot finishes
499 execution. If this option is enabled, coreboot will pass a
500 framebuffer entry in its coreboot table and the payload will need a
501 framebuffer driver. If this option is disabled, coreboot will switch
502 back to text mode before handing control to a payload.
508 # TODO: Better help text and detailed instructions.
510 bool "GDB debugging support"
513 If enabled, you will be able to set breakpoints for gdb debugging.
514 See src/arch/x86/lib/c_start.S for details.
516 config HAVE_DEBUG_RAM_SETUP
519 config DEBUG_RAM_SETUP
520 bool "Output verbose RAM init debug messages"
522 depends on HAVE_DEBUG_RAM_SETUP
524 This option enables additional RAM init related debug messages.
525 It is recommended to enable this when debugging issues on your
526 board which might be RAM init related.
528 Note: This option will increase the size of the coreboot image.
532 config HAVE_DEBUG_CAR
537 depends on HAVE_DEBUG_CAR
539 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
540 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
541 # printk(BIOS_DEBUG, ...) calls.
543 bool "Output verbose Cache-as-RAM debug messages"
545 depends on HAVE_DEBUG_CAR
547 This option enables additional CAR related debug messages.
551 bool "Check PIRQ table consistency"
553 depends on GENERATE_PIRQ_TABLE
557 config HAVE_DEBUG_SMBUS
561 bool "Output verbose SMBus debug messages"
563 depends on HAVE_DEBUG_SMBUS
565 This option enables additional SMBus (and SPD) debug messages.
567 Note: This option will increase the size of the coreboot image.
572 bool "Output verbose SMI debug messages"
574 depends on HAVE_SMI_HANDLER
576 This option enables additional SMI related debug messages.
578 Note: This option will increase the size of the coreboot image.
582 config DEBUG_SMM_RELOCATION
583 bool "Debug SMM relocation code"
585 depends on HAVE_SMI_HANDLER
587 This option enables additional SMM handler relocation related
590 Note: This option will increase the size of the coreboot image.
597 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
598 # printk(BIOS_DEBUG, ...) calls.
599 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
601 bool "Output verbose malloc debug messages"
604 This option enables additional malloc related debug messages.
606 Note: This option will increase the size of the coreboot image.
611 config REALMODE_DEBUG
613 depends on PCI_OPTION_ROM_RUN_REALMODE
615 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
616 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
617 # printk(BIOS_DEBUG, ...) calls.
618 config REALMODE_DEBUG
619 bool "Enable debug messages for option ROM execution"
621 depends on PCI_OPTION_ROM_RUN_REALMODE
623 This option enables additional x86emu related debug messages.
625 Note: This option will increase the time to emulate a ROM.
631 bool "Output verbose x86emu debug messages"
633 depends on PCI_OPTION_ROM_RUN_YABEL
635 This option enables additional x86emu related debug messages.
637 Note: This option will increase the size of the coreboot image.
641 config X86EMU_DEBUG_JMP
642 bool "Trace JMP/RETF"
644 depends on X86EMU_DEBUG
646 Print information about JMP and RETF opcodes from x86emu.
648 Note: This option will increase the size of the coreboot image.
652 config X86EMU_DEBUG_TRACE
653 bool "Trace all opcodes"
655 depends on X86EMU_DEBUG
657 Print _all_ opcodes that are executed by x86emu.
659 WARNING: This will produce a LOT of output and take a long time.
661 Note: This option will increase the size of the coreboot image.
665 config X86EMU_DEBUG_PNP
666 bool "Log Plug&Play accesses"
668 depends on X86EMU_DEBUG
670 Print Plug And Play accesses made by option ROMs.
672 Note: This option will increase the size of the coreboot image.
676 config X86EMU_DEBUG_DISK
679 depends on X86EMU_DEBUG
681 Print Disk I/O related messages.
683 Note: This option will increase the size of the coreboot image.
687 config X86EMU_DEBUG_PMM
690 depends on X86EMU_DEBUG
692 Print messages related to POST Memory Manager (PMM).
694 Note: This option will increase the size of the coreboot image.
699 config X86EMU_DEBUG_VBE
700 bool "Debug VESA BIOS Extensions"
702 depends on X86EMU_DEBUG
704 Print messages related to VESA BIOS Extension (VBE) functions.
706 Note: This option will increase the size of the coreboot image.
710 config X86EMU_DEBUG_INT10
711 bool "Redirect INT10 output to console"
713 depends on X86EMU_DEBUG
715 Let INT10 (i.e. character output) calls print messages to debug output.
717 Note: This option will increase the size of the coreboot image.
721 config X86EMU_DEBUG_INTERRUPTS
722 bool "Log intXX calls"
724 depends on X86EMU_DEBUG
726 Print messages related to interrupt handling.
728 Note: This option will increase the size of the coreboot image.
732 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
733 bool "Log special memory accesses"
735 depends on X86EMU_DEBUG
737 Print messages related to accesses to certain areas of the virtual
738 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
740 Note: This option will increase the size of the coreboot image.
744 config X86EMU_DEBUG_MEM
745 bool "Log all memory accesses"
747 depends on X86EMU_DEBUG
749 Print memory accesses made by option ROM.
750 Note: This also includes accesses to fetch instructions.
752 Note: This option will increase the size of the coreboot image.
756 config X86EMU_DEBUG_IO
757 bool "Log IO accesses"
759 depends on X86EMU_DEBUG
761 Print I/O accesses made by option ROM.
763 Note: This option will increase the size of the coreboot image.
768 bool "Built-in low-level shell"
771 If enabled, you will have a low level shell to examine your machine.
772 Put llshell() in your (romstage) code to start the shell.
773 See src/arch/x86/llshell/llshell.inc for details.
777 config LIFT_BSP_APIC_ID
781 # These probably belong somewhere else, but they are needed somewhere.
782 config AP_CODE_IN_CAR
786 config RAMINIT_SYSINFO
790 config ENABLE_APIC_EXT_ID
794 config WARNINGS_ARE_ERRORS
798 config ID_SECTION_OFFSET
802 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
803 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
804 # mutually exclusive. One of these options must be selected in the
805 # mainboard Kconfig if the chipset supports enabling and disabling of
806 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
807 # in mainboard/Kconfig to know if the button should be enabled or not.
809 config POWER_BUTTON_DEFAULT_ENABLE
812 Select when the board has a power button which can optionally be
813 disabled by the user.
815 config POWER_BUTTON_DEFAULT_DISABLE
818 Select when the board has a power button which can optionally be
819 enabled by the user, e.g. when the board ships with a jumper over
820 the power switch contacts.
822 config POWER_BUTTON_FORCE_ENABLE
825 Select when the board requires that the power button is always
828 config POWER_BUTTON_FORCE_DISABLE
831 Select when the board requires that the power button is always
832 disabled, e.g. when it has been hardwired to ground.
834 config POWER_BUTTON_IS_OPTIONAL
836 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
837 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
839 Internal option that controls ENABLE_POWER_BUTTON visibility.
841 source src/Kconfig.deprecated_options