2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
83 config SCONFIG_GENPARSER
84 bool "Generate SCONFIG parser using flex and bison"
88 Enable this option if you are working on the sconfig
89 device tree parser and made changes to sconfig.l and
93 config USE_OPTION_TABLE
94 bool "Use CMOS for configuration values"
96 depends on HAVE_OPTION_TABLE
98 Enable this option if coreboot shall read options from the "CMOS"
99 NVRAM instead of using hard coded values.
103 source src/mainboard/Kconfig
105 # This option is used to set the architecture of a mainboard to X86.
106 # It is usually set in mainboard/*/Kconfig.
112 source src/arch/x86/Kconfig
118 source src/cpu/Kconfig
119 comment "Northbridge"
120 source src/northbridge/Kconfig
121 comment "Southbridge"
122 source src/southbridge/Kconfig
124 source src/superio/Kconfig
126 source src/devices/Kconfig
127 comment "Embedded Controllers"
128 source src/ec/Kconfig
132 menu "Generic Drivers"
133 source src/drivers/Kconfig
136 config PCI_BUS_SEGN_BITS
152 config MMCONF_SUPPORT_DEFAULT
156 config MMCONF_SUPPORT
160 source src/console/Kconfig
162 config HAVE_ACPI_RESUME
166 config HAVE_ACPI_SLIC
170 config ACPI_SSDTX_NUM
174 config HAVE_HARD_RESET
176 default y if BOARD_HAS_HARD_RESET
179 This variable specifies whether a given board has a hard_reset
180 function, no matter if it's provided by board code or chipset code.
182 config HAVE_INIT_TIMER
184 default n if UDELAY_IO
187 config HAVE_MAINBOARD_RESOURCES
191 config USE_OPTION_TABLE
195 config HAVE_OPTION_TABLE
199 This variable specifies whether a given board has a cmos.layout
200 file containing NVRAM/CMOS bit definitions.
201 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
207 config HAVE_SMI_HANDLER
211 config PCI_IO_CFG_EXT
219 # TODO: Can probably be removed once all chipsets have kconfig options for it.
224 config USE_WATCHDOG_ON_BOOT
232 Build board-specific VGA code.
238 Enable Unified Memory Architecture for graphics.
245 config HAVE_ACPI_TABLES
248 This variable specifies whether a given board has ACPI table support.
249 It is usually set in mainboard/*/Kconfig.
250 Whether or not the ACPI tables are actually generated by coreboot
251 is configurable by the user via GENERATE_ACPI_TABLES.
256 This variable specifies whether a given board has MP table support.
257 It is usually set in mainboard/*/Kconfig.
258 Whether or not the MP table is actually generated by coreboot
259 is configurable by the user via GENERATE_MP_TABLE.
261 config HAVE_PIRQ_TABLE
264 This variable specifies whether a given board has PIRQ table support.
265 It is usually set in mainboard/*/Kconfig.
266 Whether or not the PIRQ table is actually generated by coreboot
267 is configurable by the user via GENERATE_PIRQ_TABLE.
269 #These Options are here to avoid "undefined" warnings.
270 #The actual selection and help texts are in the following menu.
272 config GENERATE_ACPI_TABLES
274 default HAVE_ACPI_TABLES
276 config GENERATE_MP_TABLE
278 default HAVE_MP_TABLE
280 config GENERATE_PIRQ_TABLE
282 default HAVE_PIRQ_TABLE
286 config WRITE_HIGH_TABLES
287 bool "Write 'high' tables to avoid being overwritten in F segment"
291 bool "Generate Multiboot tables (for GRUB2)"
294 config GENERATE_ACPI_TABLES
295 depends on HAVE_ACPI_TABLES
296 bool "Generate ACPI tables"
299 Generate ACPI tables for this board.
303 config GENERATE_MP_TABLE
304 depends on HAVE_MP_TABLE
305 bool "Generate an MP table"
308 Generate an MP table (conforming to the Intel MultiProcessor
309 specification 1.4) for this board.
313 config GENERATE_PIRQ_TABLE
314 depends on HAVE_PIRQ_TABLE
315 bool "Generate a PIRQ table"
318 Generate a PIRQ table for this board.
327 prompt "Add a payload"
328 default PAYLOAD_NONE if !ARCH_X86
329 default PAYLOAD_SEABIOS if ARCH_X86
334 Select this option if you want to create an "empty" coreboot
335 ROM image for a certain mainboard, i.e. a coreboot ROM image
336 which does not yet contain a payload.
338 For such an image to be useful, you have to use 'cbfstool'
339 to add a payload to the ROM image later.
342 bool "An ELF executable payload"
344 Select this option if you have a payload image (an ELF file)
345 which coreboot should run as soon as the basic hardware
346 initialization is completed.
348 You will be able to specify the location and file name of the
351 config PAYLOAD_SEABIOS
355 Select this option if you want to build a coreboot image
356 with a SeaBIOS payload. If you don't know what this is
357 about, just leave it enabled.
359 See http://coreboot.org/Payloads for more information.
364 prompt "SeaBIOS version"
365 default SEABIOS_STABLE
366 depends on PAYLOAD_SEABIOS
368 config SEABIOS_STABLE
371 Stable SeaBIOS version
372 config SEABIOS_MASTER
375 Newest SeaBIOS version
379 string "Payload path and filename"
380 depends on PAYLOAD_ELF
381 default "payload.elf"
383 The path and filename of the ELF executable file to use as payload.
386 depends on PAYLOAD_SEABIOS
387 default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
389 # TODO: Defined if no payload? Breaks build?
390 config COMPRESSED_PAYLOAD_LZMA
391 bool "Use LZMA compression for payloads"
393 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS
395 In order to reduce the size payloads take up in the ROM chip
396 coreboot can compress them using the LZMA algorithm.
398 config COMPRESSED_PAYLOAD_NRV2B
407 bool "Add a VGA BIOS image"
409 Select this option if you have a VGA BIOS image that you would
410 like to add to your ROM.
412 You will be able to specify the location and file name of the
416 string "VGA BIOS path and filename"
418 default "vgabios.bin"
420 The path and filename of the file to use as VGA BIOS.
423 string "VGA device PCI IDs"
427 The comma-separated PCI vendor and device ID that would associate
428 your VGA BIOS to your video card.
432 In the above example 1106 is the PCI vendor ID (in hex, but without
433 the "0x" prefix) and 3230 specifies the PCI device ID of the
434 video card (also in hex, without "0x" prefix).
437 bool "Add an MBI image"
438 depends on NORTHBRIDGE_INTEL_I82830
440 Select this option if you have an Intel MBI image that you would
441 like to add to your ROM.
443 You will be able to specify the location and file name of the
447 string "Intel MBI path and filename"
451 The path and filename of the file to use as VGA BIOS.
456 depends on PCI_OPTION_ROM_RUN_YABEL
459 prompt "Show graphical bootsplash"
461 depends on PCI_OPTION_ROM_RUN_YABEL
463 This option shows a graphical bootsplash screen. The grapics are
464 loaded from the CBFS file bootsplash.jpg.
466 config BOOTSPLASH_FILE
467 string "Bootsplash path and filename"
468 depends on BOOTSPLASH
469 default "bootsplash.jpg"
471 The path and filename of the file to use as graphical bootsplash
472 screen. The file format has to be jpg.
474 # TODO: Turn this into a "choice".
475 config FRAMEBUFFER_VESA_MODE
476 prompt "VESA framebuffer video mode"
479 depends on BOOTSPLASH
481 This option sets the resolution used for the coreboot framebuffer and
482 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
483 some day make this a "choice".
485 config COREBOOT_KEEP_FRAMEBUFFER
486 prompt "Keep VESA framebuffer"
488 depends on BOOTSPLASH
490 This option keeps the framebuffer mode set after coreboot finishes
491 execution. If this option is enabled, coreboot will pass a
492 framebuffer entry in its coreboot table and the payload will need a
493 framebuffer driver. If this option is disabled, coreboot will switch
494 back to text mode before handing control to a payload.
500 # TODO: Better help text and detailed instructions.
502 bool "GDB debugging support"
505 If enabled, you will be able to set breakpoints for gdb debugging.
506 See src/arch/x86/lib/c_start.S for details.
508 config HAVE_DEBUG_RAM_SETUP
511 config DEBUG_RAM_SETUP
512 bool "Output verbose RAM init debug messages"
514 depends on HAVE_DEBUG_RAM_SETUP
516 This option enables additional RAM init related debug messages.
517 It is recommended to enable this when debugging issues on your
518 board which might be RAM init related.
520 Note: This option will increase the size of the coreboot image.
524 config HAVE_DEBUG_CAR
529 depends on HAVE_DEBUG_CAR
531 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
532 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
533 # printk(BIOS_DEBUG, ...) calls.
535 bool "Output verbose Cache-as-RAM debug messages"
537 depends on HAVE_DEBUG_CAR
539 This option enables additional CAR related debug messages.
543 bool "Check PIRQ table consistency"
545 depends on GENERATE_PIRQ_TABLE
549 config HAVE_DEBUG_SMBUS
553 bool "Output verbose SMBus debug messages"
555 depends on HAVE_DEBUG_SMBUS
557 This option enables additional SMBus (and SPD) debug messages.
559 Note: This option will increase the size of the coreboot image.
564 bool "Output verbose SMI debug messages"
566 depends on HAVE_SMI_HANDLER
568 This option enables additional SMI related debug messages.
570 Note: This option will increase the size of the coreboot image.
574 config DEBUG_SMM_RELOCATION
575 bool "Debug SMM relocation code"
577 depends on HAVE_SMI_HANDLER
579 This option enables additional SMM handler relocation related
582 Note: This option will increase the size of the coreboot image.
589 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
590 # printk(BIOS_DEBUG, ...) calls.
591 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
593 bool "Output verbose malloc debug messages"
596 This option enables additional malloc related debug messages.
598 Note: This option will increase the size of the coreboot image.
603 config REALMODE_DEBUG
605 depends on PCI_OPTION_ROM_RUN_REALMODE
607 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
608 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
609 # printk(BIOS_DEBUG, ...) calls.
610 config REALMODE_DEBUG
611 bool "Enable debug messages for option ROM execution"
613 depends on PCI_OPTION_ROM_RUN_REALMODE
615 This option enables additional x86emu related debug messages.
617 Note: This option will increase the time to emulate a ROM.
623 bool "Output verbose x86emu debug messages"
625 depends on PCI_OPTION_ROM_RUN_YABEL
627 This option enables additional x86emu related debug messages.
629 Note: This option will increase the size of the coreboot image.
633 config X86EMU_DEBUG_JMP
634 bool "Trace JMP/RETF"
636 depends on X86EMU_DEBUG
638 Print information about JMP and RETF opcodes from x86emu.
640 Note: This option will increase the size of the coreboot image.
644 config X86EMU_DEBUG_TRACE
645 bool "Trace all opcodes"
647 depends on X86EMU_DEBUG
649 Print _all_ opcodes that are executed by x86emu.
651 WARNING: This will produce a LOT of output and take a long time.
653 Note: This option will increase the size of the coreboot image.
657 config X86EMU_DEBUG_PNP
658 bool "Log Plug&Play accesses"
660 depends on X86EMU_DEBUG
662 Print Plug And Play accesses made by option ROMs.
664 Note: This option will increase the size of the coreboot image.
668 config X86EMU_DEBUG_DISK
671 depends on X86EMU_DEBUG
673 Print Disk I/O related messages.
675 Note: This option will increase the size of the coreboot image.
679 config X86EMU_DEBUG_PMM
682 depends on X86EMU_DEBUG
684 Print messages related to POST Memory Manager (PMM).
686 Note: This option will increase the size of the coreboot image.
691 config X86EMU_DEBUG_VBE
692 bool "Debug VESA BIOS Extensions"
694 depends on X86EMU_DEBUG
696 Print messages related to VESA BIOS Extension (VBE) functions.
698 Note: This option will increase the size of the coreboot image.
702 config X86EMU_DEBUG_INT10
703 bool "Redirect INT10 output to console"
705 depends on X86EMU_DEBUG
707 Let INT10 (i.e. character output) calls print messages to debug output.
709 Note: This option will increase the size of the coreboot image.
713 config X86EMU_DEBUG_INTERRUPTS
714 bool "Log intXX calls"
716 depends on X86EMU_DEBUG
718 Print messages related to interrupt handling.
720 Note: This option will increase the size of the coreboot image.
724 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
725 bool "Log special memory accesses"
727 depends on X86EMU_DEBUG
729 Print messages related to accesses to certain areas of the virtual
730 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
732 Note: This option will increase the size of the coreboot image.
736 config X86EMU_DEBUG_MEM
737 bool "Log all memory accesses"
739 depends on X86EMU_DEBUG
741 Print memory accesses made by option ROM.
742 Note: This also includes accesses to fetch instructions.
744 Note: This option will increase the size of the coreboot image.
748 config X86EMU_DEBUG_IO
749 bool "Log IO accesses"
751 depends on X86EMU_DEBUG
753 Print I/O accesses made by option ROM.
755 Note: This option will increase the size of the coreboot image.
760 bool "Built-in low-level shell"
763 If enabled, you will have a low level shell to examine your machine.
764 Put llshell() in your (romstage) code to start the shell.
765 See src/arch/x86/llshell/llshell.inc for details.
769 config LIFT_BSP_APIC_ID
773 # These probably belong somewhere else, but they are needed somewhere.
774 config AP_CODE_IN_CAR
778 config RAMINIT_SYSINFO
782 config ENABLE_APIC_EXT_ID
786 config WARNINGS_ARE_ERRORS
790 config ID_SECTION_OFFSET
794 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
795 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
796 # mutually exclusive. One of these options must be selected in the
797 # mainboard Kconfig if the chipset supports enabling and disabling of
798 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
799 # in mainboard/Kconfig to know if the button should be enabled or not.
801 config POWER_BUTTON_DEFAULT_ENABLE
804 Select when the board has a power button which can optionally be
805 disabled by the user.
807 config POWER_BUTTON_DEFAULT_DISABLE
810 Select when the board has a power button which can optionally be
811 enabled by the user, e.g. when the board ships with a jumper over
812 the power switch contacts.
814 config POWER_BUTTON_FORCE_ENABLE
817 Select when the board requires that the power button is always
820 config POWER_BUTTON_FORCE_DISABLE
823 Select when the board requires that the power button is always
824 disabled, e.g. when it has been hardwired to ground.
826 config POWER_BUTTON_IS_OPTIONAL
828 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
829 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
831 Internal option that controls ENABLE_POWER_BUTTON visibility.
833 source src/Kconfig.deprecated_options