2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
83 config SCONFIG_GENPARSER
84 bool "Generate SCONFIG parser using flex and bison"
88 Enable this option if you are working on the sconfig
89 device tree parser and made changes to sconfig.l and
93 config USE_OPTION_TABLE
94 bool "Use CMOS for configuration values"
96 depends on HAVE_OPTION_TABLE
98 Enable this option if coreboot shall read options from the "CMOS"
99 NVRAM instead of using hard coded values.
101 config COMPRESS_RAMSTAGE
102 bool "Compress ramstage with LZMA"
105 Compress ramstage to save memory in the flash image. Note
106 that decompression might slow down booting if the boot flash
107 is connected through a slow Link (i.e. SPI)
109 config INCLUDE_CONFIG_FILE
110 bool "Include the coreboot config file into the ROM image"
113 Include in CBFS the coreboot config file that was used to compile the ROM image
117 source src/mainboard/Kconfig
119 # This option is used to set the architecture of a mainboard to X86.
120 # It is usually set in mainboard/*/Kconfig.
126 source src/arch/x86/Kconfig
132 source src/cpu/Kconfig
133 comment "Northbridge"
134 source src/northbridge/Kconfig
135 comment "Southbridge"
136 source src/southbridge/Kconfig
138 source src/superio/Kconfig
140 source src/devices/Kconfig
141 comment "Embedded Controllers"
142 source src/ec/Kconfig
146 menu "Generic Drivers"
147 source src/drivers/Kconfig
150 config PCI_BUS_SEGN_BITS
166 config MMCONF_SUPPORT_DEFAULT
170 config MMCONF_SUPPORT
174 source src/console/Kconfig
176 # This should default to N and be set by SuperI/O drivers that have an UART
177 config HAVE_UART_IO_MAPPED
181 config HAVE_UART_MEMORY_MAPPED
185 config HAVE_ACPI_RESUME
189 config HAVE_ACPI_SLIC
193 config ACPI_SSDTX_NUM
197 config HAVE_HARD_RESET
199 default y if BOARD_HAS_HARD_RESET
202 This variable specifies whether a given board has a hard_reset
203 function, no matter if it's provided by board code or chipset code.
205 config HAVE_INIT_TIMER
207 default n if UDELAY_IO
210 config HAVE_MAINBOARD_RESOURCES
214 config USE_OPTION_TABLE
218 config HAVE_OPTION_TABLE
222 This variable specifies whether a given board has a cmos.layout
223 file containing NVRAM/CMOS bit definitions.
224 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
230 config HAVE_SMI_HANDLER
234 config PCI_IO_CFG_EXT
242 # TODO: Can probably be removed once all chipsets have kconfig options for it.
247 config USE_WATCHDOG_ON_BOOT
255 Build board-specific VGA code.
261 Enable Unified Memory Architecture for graphics.
268 config HAVE_ACPI_TABLES
271 This variable specifies whether a given board has ACPI table support.
272 It is usually set in mainboard/*/Kconfig.
273 Whether or not the ACPI tables are actually generated by coreboot
274 is configurable by the user via GENERATE_ACPI_TABLES.
279 This variable specifies whether a given board has MP table support.
280 It is usually set in mainboard/*/Kconfig.
281 Whether or not the MP table is actually generated by coreboot
282 is configurable by the user via GENERATE_MP_TABLE.
284 config HAVE_PIRQ_TABLE
287 This variable specifies whether a given board has PIRQ table support.
288 It is usually set in mainboard/*/Kconfig.
289 Whether or not the PIRQ table is actually generated by coreboot
290 is configurable by the user via GENERATE_PIRQ_TABLE.
292 #These Options are here to avoid "undefined" warnings.
293 #The actual selection and help texts are in the following menu.
295 config GENERATE_ACPI_TABLES
297 default HAVE_ACPI_TABLES
299 config GENERATE_MP_TABLE
301 default HAVE_MP_TABLE
303 config GENERATE_PIRQ_TABLE
305 default HAVE_PIRQ_TABLE
309 config WRITE_HIGH_TABLES
310 bool "Write 'high' tables to avoid being overwritten in F segment"
314 bool "Generate Multiboot tables (for GRUB2)"
317 config GENERATE_ACPI_TABLES
318 depends on HAVE_ACPI_TABLES
319 bool "Generate ACPI tables"
322 Generate ACPI tables for this board.
326 config GENERATE_MP_TABLE
327 depends on HAVE_MP_TABLE
328 bool "Generate an MP table"
331 Generate an MP table (conforming to the Intel MultiProcessor
332 specification 1.4) for this board.
336 config GENERATE_PIRQ_TABLE
337 depends on HAVE_PIRQ_TABLE
338 bool "Generate a PIRQ table"
341 Generate a PIRQ table for this board.
350 prompt "Add a payload"
351 default PAYLOAD_NONE if !ARCH_X86
352 default PAYLOAD_SEABIOS if ARCH_X86
357 Select this option if you want to create an "empty" coreboot
358 ROM image for a certain mainboard, i.e. a coreboot ROM image
359 which does not yet contain a payload.
361 For such an image to be useful, you have to use 'cbfstool'
362 to add a payload to the ROM image later.
365 bool "An ELF executable payload"
367 Select this option if you have a payload image (an ELF file)
368 which coreboot should run as soon as the basic hardware
369 initialization is completed.
371 You will be able to specify the location and file name of the
374 config PAYLOAD_SEABIOS
378 Select this option if you want to build a coreboot image
379 with a SeaBIOS payload. If you don't know what this is
380 about, just leave it enabled.
382 See http://coreboot.org/Payloads for more information.
387 Select this option if you want to build a coreboot image
388 with a FILO payload. If you don't know what this is
389 about, just leave it enabled.
391 See http://coreboot.org/Payloads for more information.
396 prompt "SeaBIOS version"
397 default SEABIOS_STABLE
398 depends on PAYLOAD_SEABIOS
400 config SEABIOS_STABLE
403 Stable SeaBIOS version
404 config SEABIOS_MASTER
407 Newest SeaBIOS version
411 prompt "FILO version"
413 depends on PAYLOAD_FILO
426 string "Payload path and filename"
427 depends on PAYLOAD_ELF
428 default "payload.elf"
430 The path and filename of the ELF executable file to use as payload.
433 depends on PAYLOAD_SEABIOS
434 default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
437 depends on PAYLOAD_FILO
438 default "payloads/external/FILO/filo/build/filo.elf"
440 # TODO: Defined if no payload? Breaks build?
441 config COMPRESSED_PAYLOAD_LZMA
442 bool "Use LZMA compression for payloads"
444 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO
446 In order to reduce the size payloads take up in the ROM chip
447 coreboot can compress them using the LZMA algorithm.
449 config COMPRESSED_PAYLOAD_NRV2B
458 bool "Add a VGA BIOS image"
460 Select this option if you have a VGA BIOS image that you would
461 like to add to your ROM.
463 You will be able to specify the location and file name of the
467 string "VGA BIOS path and filename"
469 default "vgabios.bin"
471 The path and filename of the file to use as VGA BIOS.
474 string "VGA device PCI IDs"
478 The comma-separated PCI vendor and device ID that would associate
479 your VGA BIOS to your video card.
483 In the above example 1106 is the PCI vendor ID (in hex, but without
484 the "0x" prefix) and 3230 specifies the PCI device ID of the
485 video card (also in hex, without "0x" prefix).
488 bool "Add an MBI image"
489 depends on NORTHBRIDGE_INTEL_I82830
491 Select this option if you have an Intel MBI image that you would
492 like to add to your ROM.
494 You will be able to specify the location and file name of the
498 string "Intel MBI path and filename"
502 The path and filename of the file to use as VGA BIOS.
507 depends on PCI_OPTION_ROM_RUN_YABEL
510 prompt "Show graphical bootsplash"
512 depends on PCI_OPTION_ROM_RUN_YABEL
514 This option shows a graphical bootsplash screen. The grapics are
515 loaded from the CBFS file bootsplash.jpg.
517 config BOOTSPLASH_FILE
518 string "Bootsplash path and filename"
519 depends on BOOTSPLASH
520 default "bootsplash.jpg"
522 The path and filename of the file to use as graphical bootsplash
523 screen. The file format has to be jpg.
525 # TODO: Turn this into a "choice".
526 config FRAMEBUFFER_VESA_MODE
527 prompt "VESA framebuffer video mode"
530 depends on BOOTSPLASH
532 This option sets the resolution used for the coreboot framebuffer and
533 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
534 some day make this a "choice".
536 config COREBOOT_KEEP_FRAMEBUFFER
537 prompt "Keep VESA framebuffer"
539 depends on BOOTSPLASH
541 This option keeps the framebuffer mode set after coreboot finishes
542 execution. If this option is enabled, coreboot will pass a
543 framebuffer entry in its coreboot table and the payload will need a
544 framebuffer driver. If this option is disabled, coreboot will switch
545 back to text mode before handing control to a payload.
551 # TODO: Better help text and detailed instructions.
553 bool "GDB debugging support"
556 If enabled, you will be able to set breakpoints for gdb debugging.
557 See src/arch/x86/lib/c_start.S for details.
559 config HAVE_DEBUG_RAM_SETUP
562 config DEBUG_RAM_SETUP
563 bool "Output verbose RAM init debug messages"
565 depends on HAVE_DEBUG_RAM_SETUP
567 This option enables additional RAM init related debug messages.
568 It is recommended to enable this when debugging issues on your
569 board which might be RAM init related.
571 Note: This option will increase the size of the coreboot image.
575 config HAVE_DEBUG_CAR
580 depends on HAVE_DEBUG_CAR
582 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
583 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
584 # printk(BIOS_DEBUG, ...) calls.
586 bool "Output verbose Cache-as-RAM debug messages"
588 depends on HAVE_DEBUG_CAR
590 This option enables additional CAR related debug messages.
594 bool "Check PIRQ table consistency"
596 depends on GENERATE_PIRQ_TABLE
600 config HAVE_DEBUG_SMBUS
604 bool "Output verbose SMBus debug messages"
606 depends on HAVE_DEBUG_SMBUS
608 This option enables additional SMBus (and SPD) debug messages.
610 Note: This option will increase the size of the coreboot image.
615 bool "Output verbose SMI debug messages"
617 depends on HAVE_SMI_HANDLER
619 This option enables additional SMI related debug messages.
621 Note: This option will increase the size of the coreboot image.
625 config DEBUG_SMM_RELOCATION
626 bool "Debug SMM relocation code"
628 depends on HAVE_SMI_HANDLER
630 This option enables additional SMM handler relocation related
633 Note: This option will increase the size of the coreboot image.
640 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
641 # printk(BIOS_DEBUG, ...) calls.
642 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
644 bool "Output verbose malloc debug messages"
647 This option enables additional malloc related debug messages.
649 Note: This option will increase the size of the coreboot image.
654 config REALMODE_DEBUG
656 depends on PCI_OPTION_ROM_RUN_REALMODE
658 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
659 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
660 # printk(BIOS_DEBUG, ...) calls.
661 config REALMODE_DEBUG
662 bool "Enable debug messages for option ROM execution"
664 depends on PCI_OPTION_ROM_RUN_REALMODE
666 This option enables additional x86emu related debug messages.
668 Note: This option will increase the time to emulate a ROM.
674 bool "Output verbose x86emu debug messages"
676 depends on PCI_OPTION_ROM_RUN_YABEL
678 This option enables additional x86emu related debug messages.
680 Note: This option will increase the size of the coreboot image.
684 config X86EMU_DEBUG_JMP
685 bool "Trace JMP/RETF"
687 depends on X86EMU_DEBUG
689 Print information about JMP and RETF opcodes from x86emu.
691 Note: This option will increase the size of the coreboot image.
695 config X86EMU_DEBUG_TRACE
696 bool "Trace all opcodes"
698 depends on X86EMU_DEBUG
700 Print _all_ opcodes that are executed by x86emu.
702 WARNING: This will produce a LOT of output and take a long time.
704 Note: This option will increase the size of the coreboot image.
708 config X86EMU_DEBUG_PNP
709 bool "Log Plug&Play accesses"
711 depends on X86EMU_DEBUG
713 Print Plug And Play accesses made by option ROMs.
715 Note: This option will increase the size of the coreboot image.
719 config X86EMU_DEBUG_DISK
722 depends on X86EMU_DEBUG
724 Print Disk I/O related messages.
726 Note: This option will increase the size of the coreboot image.
730 config X86EMU_DEBUG_PMM
733 depends on X86EMU_DEBUG
735 Print messages related to POST Memory Manager (PMM).
737 Note: This option will increase the size of the coreboot image.
742 config X86EMU_DEBUG_VBE
743 bool "Debug VESA BIOS Extensions"
745 depends on X86EMU_DEBUG
747 Print messages related to VESA BIOS Extension (VBE) functions.
749 Note: This option will increase the size of the coreboot image.
753 config X86EMU_DEBUG_INT10
754 bool "Redirect INT10 output to console"
756 depends on X86EMU_DEBUG
758 Let INT10 (i.e. character output) calls print messages to debug output.
760 Note: This option will increase the size of the coreboot image.
764 config X86EMU_DEBUG_INTERRUPTS
765 bool "Log intXX calls"
767 depends on X86EMU_DEBUG
769 Print messages related to interrupt handling.
771 Note: This option will increase the size of the coreboot image.
775 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
776 bool "Log special memory accesses"
778 depends on X86EMU_DEBUG
780 Print messages related to accesses to certain areas of the virtual
781 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
783 Note: This option will increase the size of the coreboot image.
787 config X86EMU_DEBUG_MEM
788 bool "Log all memory accesses"
790 depends on X86EMU_DEBUG
792 Print memory accesses made by option ROM.
793 Note: This also includes accesses to fetch instructions.
795 Note: This option will increase the size of the coreboot image.
799 config X86EMU_DEBUG_IO
800 bool "Log IO accesses"
802 depends on X86EMU_DEBUG
804 Print I/O accesses made by option ROM.
806 Note: This option will increase the size of the coreboot image.
811 bool "Built-in low-level shell"
814 If enabled, you will have a low level shell to examine your machine.
815 Put llshell() in your (romstage) code to start the shell.
816 See src/arch/x86/llshell/llshell.inc for details.
820 config LIFT_BSP_APIC_ID
824 # These probably belong somewhere else, but they are needed somewhere.
825 config AP_CODE_IN_CAR
829 config RAMINIT_SYSINFO
833 config ENABLE_APIC_EXT_ID
837 config WARNINGS_ARE_ERRORS
841 config ID_SECTION_OFFSET
845 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
846 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
847 # mutually exclusive. One of these options must be selected in the
848 # mainboard Kconfig if the chipset supports enabling and disabling of
849 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
850 # in mainboard/Kconfig to know if the button should be enabled or not.
852 config POWER_BUTTON_DEFAULT_ENABLE
855 Select when the board has a power button which can optionally be
856 disabled by the user.
858 config POWER_BUTTON_DEFAULT_DISABLE
861 Select when the board has a power button which can optionally be
862 enabled by the user, e.g. when the board ships with a jumper over
863 the power switch contacts.
865 config POWER_BUTTON_FORCE_ENABLE
868 Select when the board requires that the power button is always
871 config POWER_BUTTON_FORCE_DISABLE
874 Select when the board requires that the power button is always
875 disabled, e.g. when it has been hardwired to ground.
877 config POWER_BUTTON_IS_OPTIONAL
879 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
880 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
882 Internal option that controls ENABLE_POWER_BUTTON visibility.
884 source src/Kconfig.deprecated_options