2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
49 config SCANBUILD_ENABLE
50 bool "build with scan-build for static analysis"
53 Changes the build process to scan-build is used.
54 Requires scan-build in path.
56 config SCANBUILD_REPORT_LOCATION
57 string "directory to put scan-build report in"
59 depends on SCANBUILD_ENABLE
61 Where the scan-build report should be stored
65 source src/mainboard/Kconfig
66 source src/arch/i386/Kconfig
71 source src/cpu/Kconfig
74 menu "HyperTransport setup"
75 depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
78 prompt "HyperTransport frequency"
79 default LIMIT_HT_SPEED_AUTO
81 This option sets the maximum permissible HyperTransport link
84 Use of this option will only limit the autodetected HT frequency.
85 It will not (and cannot) increase the frequency beyond the
88 This is primarily used to work around poorly designed or laid out
89 HT traces on certain motherboards.
91 config LIMIT_HT_SPEED_200
92 bool "Limit HT frequency to 200MHz"
93 config LIMIT_HT_SPEED_400
94 bool "Limit HT frequency to 400MHz"
95 config LIMIT_HT_SPEED_600
96 bool "Limit HT frequency to 600MHz"
97 config LIMIT_HT_SPEED_800
98 bool "Limit HT frequency to 800MHz"
99 config LIMIT_HT_SPEED_1000
100 bool "Limit HT frequency to 1.0GHz"
101 config LIMIT_HT_SPEED_1200
102 bool "Limit HT frequency to 1.2GHz"
103 config LIMIT_HT_SPEED_1400
104 bool "Limit HT frequency to 1.4GHz"
105 config LIMIT_HT_SPEED_1600
106 bool "Limit HT frequency to 1.6GHz"
107 config LIMIT_HT_SPEED_1800
108 bool "Limit HT frequency to 1.8GHz"
109 config LIMIT_HT_SPEED_2000
110 bool "Limit HT frequency to 2.0GHz"
111 config LIMIT_HT_SPEED_2200
112 bool "Limit HT frequency to 2.2GHz"
113 config LIMIT_HT_SPEED_2400
114 bool "Limit HT frequency to 2.4GHz"
115 config LIMIT_HT_SPEED_2600
116 bool "Limit HT frequency to 2.6GHz"
117 config LIMIT_HT_SPEED_AUTO
118 bool "Autodetect HT frequency"
122 prompt "HyperTransport downlink width"
123 default LIMIT_HT_DOWN_WIDTH_16
125 This option sets the maximum permissible HyperTransport
128 Use of this option will only limit the autodetected HT width.
129 It will not (and cannot) increase the width beyond the autodetected
132 This is primarily used to work around poorly designed or laid out HT
133 traces on certain motherboards.
135 config LIMIT_HT_DOWN_WIDTH_8
137 config LIMIT_HT_DOWN_WIDTH_16
142 prompt "HyperTransport uplink width"
143 default LIMIT_HT_UP_WIDTH_16
145 This option sets the maximum permissible HyperTransport
148 Use of this option will only limit the autodetected HT width.
149 It will not (and cannot) increase the width beyond the autodetected
152 This is primarily used to work around poorly designed or laid out HT
153 traces on certain motherboards.
155 config LIMIT_HT_UP_WIDTH_8
157 config LIMIT_HT_UP_WIDTH_16
163 source src/northbridge/Kconfig
164 comment "Southbridge"
165 source src/southbridge/Kconfig
167 source src/superio/Kconfig
169 source src/devices/Kconfig
173 config PCI_BUS_SEGN_BITS
177 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
181 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
197 config LB_CKS_RANGE_START
201 config LB_CKS_RANGE_END
225 config USE_PRINTK_IN_CAR
229 config USE_OPTION_TABLE
237 config MMCONF_SUPPORT_DEFAULT
241 config MMCONF_SUPPORT
252 source src/console/Kconfig
254 config HAVE_ACPI_RESUME
258 config ACPI_SSDTX_NUM
262 config HAVE_FALLBACK_BOOT
266 config USE_FALLBACK_IMAGE
270 config HAVE_FAILOVER_BOOT
274 config USE_FAILOVER_IMAGE
278 config HAVE_HARD_RESET
280 default y if BOARD_HAS_HARD_RESET
283 This variable specifies whether a given board has a hard_reset
284 function, no matter if it's provided by board code or chipset code.
286 config HAVE_INIT_TIMER
288 default n if UDELAY_IO
291 config HAVE_MAINBOARD_RESOURCES
295 config HAVE_OPTION_TABLE
299 This variable specifies whether a given board has a cmos.layout
300 file containing NVRAM/CMOS bit definitions.
301 It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
307 config HAVE_SMI_HANDLER
311 config PCI_IO_CFG_EXT
319 # TODO: Can probably be removed once all chipsets have kconfig options for it.
324 config USE_WATCHDOG_ON_BOOT
332 Build board-specific VGA code.
338 Enable Unified Memory Architecture for graphics.
345 #TODO Remove this option or make it useful.
346 config HAVE_LOW_TABLES
350 This Option is unused in the code. Since two boards try to set it to
351 'n', they may be broken. We either need to make the option useful or
352 get rid of it. The broken boards are:
356 config HAVE_HIGH_TABLES
360 This variable specifies whether a given northbridge has high table
362 It is set in northbridge/*/Kconfig.
363 Whether or not the high tables are actually written by coreboot is
364 configurable by the user via WRITE_HIGH_TABLES.
366 config HAVE_ACPI_TABLES
369 This variable specifies whether a given board has ACPI table support.
370 It is usually set in mainboard/*/Kconfig.
371 Whether or not the ACPI tables are actually generated by coreboot
372 is configurable by the user via GENERATE_ACPI_TABLES.
377 This variable specifies whether a given board has MP table support.
378 It is usually set in mainboard/*/Kconfig.
379 Whether or not the MP table is actually generated by coreboot
380 is configurable by the user via GENERATE_MP_TABLE.
382 config HAVE_PIRQ_TABLE
385 This variable specifies whether a given board has PIRQ table support.
386 It is usually set in mainboard/*/Kconfig.
387 Whether or not the PIRQ table is actually generated by coreboot
388 is configurable by the user via GENERATE_PIRQ_TABLE.
390 #These Options are here to avoid "undefined" warnings.
391 #The actual selection and help texts are in the following menu.
393 config GENERATE_ACPI_TABLES
395 default HAVE_ACPI_TABLES
397 config GENERATE_MP_TABLE
399 default HAVE_MP_TABLE
401 config GENERATE_PIRQ_TABLE
403 default HAVE_PIRQ_TABLE
405 config WRITE_HIGH_TABLES
407 default HAVE_HIGH_TABLES
411 config WRITE_HIGH_TABLES
412 bool "Write 'high' tables to avoid being overwritten in F segment"
413 depends on HAVE_HIGH_TABLES
417 bool "Generate Multiboot tables (for GRUB2)"
420 config GENERATE_ACPI_TABLES
421 depends on HAVE_ACPI_TABLES
422 bool "Generate ACPI tables"
425 Generate ACPI tables for this board.
429 config GENERATE_MP_TABLE
430 depends on HAVE_MP_TABLE
431 bool "Generate an MP table"
434 Generate an MP table (conforming to the Intel MultiProcessor
435 specification 1.4) for this board.
439 config GENERATE_PIRQ_TABLE
440 depends on HAVE_PIRQ_TABLE
441 bool "Generate a PIRQ table"
444 Generate a PIRQ table for this board.
453 prompt "Add a payload"
459 Select this option if you want to create an "empty" coreboot
460 ROM image for a certain mainboard, i.e. a coreboot ROM image
461 which does not yet contain a payload.
463 For such an image to be useful, you have to use 'cbfstool'
464 to add a payload to the ROM image later.
467 bool "An ELF executable payload"
469 Select this option if you have a payload image (an ELF file)
470 which coreboot should run as soon as the basic hardware
471 initialization is completed.
473 You will be able to specify the location and file name of the
478 config FALLBACK_PAYLOAD_FILE
479 string "Payload path and filename"
480 depends on PAYLOAD_ELF
481 default "payload.elf"
483 The path and filename of the ELF executable file to use as payload.
485 # TODO: Defined if no payload? Breaks build?
486 config COMPRESSED_PAYLOAD_LZMA
487 bool "Use LZMA compression for payloads"
489 depends on PAYLOAD_ELF
491 In order to reduce the size payloads take up in the ROM chip
492 coreboot can compress them using the LZMA algorithm.
494 config COMPRESSED_PAYLOAD_NRV2B
503 bool "Add a VGA BIOS image"
505 Select this option if you have a VGA BIOS image that you would
506 like to add to your ROM.
508 You will be able to specify the location and file name of the
511 config FALLBACK_VGA_BIOS_FILE
512 string "VGA BIOS path and filename"
514 default "vgabios.bin"
516 The path and filename of the file to use as VGA BIOS.
518 config FALLBACK_VGA_BIOS_ID
519 string "VGA device PCI IDs"
523 The comma-separated PCI vendor and device ID that would associate
524 your VGA BIOS to your video card.
528 In the above example 1106 is the PCI vendor ID (in hex, but without
529 the "0x" prefix) and 3230 specifies the PCI device ID of the
530 video card (also in hex, without "0x" prefix).
533 bool "Add an MBI image"
534 depends on NORTHBRIDGE_INTEL_I82830
536 Select this option if you have an Intel MBI image that you would
537 like to add to your ROM.
539 You will be able to specify the location and file name of the
542 config FALLBACK_MBI_FILE
543 string "Intel MBI path and filename"
547 The path and filename of the file to use as VGA BIOS.
552 depends on PCI_OPTION_ROM_RUN_YABEL
555 prompt "Show graphical bootsplash"
557 depends on PCI_OPTION_ROM_RUN_YABEL
559 This option shows a graphical bootsplash screen. The grapics are
560 loaded from the CBFS file bootsplash.jpg.
562 config FALLBACK_BOOTSPLASH_FILE
563 string "Bootsplash path and filename"
564 depends on BOOTSPLASH
565 default "bootsplash.jpg"
567 The path and filename of the file to use as graphical bootsplash
568 screen. The file format has to be jpg.
570 # TODO: Turn this into a "choice".
571 config FRAMEBUFFER_VESA_MODE
572 prompt "VESA framebuffer video mode"
575 depends on BOOTSPLASH
577 This option sets the resolution used for the coreboot framebuffer and
578 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
579 some day make this a "choice".
581 config COREBOOT_KEEP_FRAMEBUFFER
582 prompt "Keep VESA framebuffer"
584 depends on BOOTSPLASH
586 This option keeps the framebuffer mode set after coreboot finishes
587 execution. If this option is enabled, coreboot will pass a
588 framebuffer entry in its coreboot table and the payload will need a
589 framebuffer driver. If this option is disabled, coreboot will switch
590 back to text mode before handing control to a payload.
596 # TODO: Better help text and detailed instructions.
598 bool "GDB debugging support"
601 If enabled, you will be able to set breakpoints for gdb debugging.
602 See src/arch/i386/lib/c_start.S for details.
604 config DEBUG_RAM_SETUP
605 bool "Output verbose RAM init debug messages"
607 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
608 || NORTHBRIDGE_AMD_AMDK8 \
609 || NORTHBRIDGE_VIA_CN700 \
610 || NORTHBRIDGE_VIA_CX700 \
611 || NORTHBRIDGE_VIA_VX800 \
612 || NORTHBRIDGE_INTEL_E7501 \
613 || NORTHBRIDGE_INTEL_I440BX \
614 || NORTHBRIDGE_INTEL_I82810 \
615 || NORTHBRIDGE_INTEL_I82830 \
616 || NORTHBRIDGE_INTEL_I945)
618 This option enables additional RAM init related debug messages.
619 It is recommended to enable this when debugging issues on your
620 board which might be RAM init related.
622 Note: This option will increase the size of the coreboot image.
627 bool "Output verbose SMBus debug messages"
629 depends on (SOUTHBRIDGE_VIA_VT8237R \
630 || NORTHBRIDGE_VIA_VX800 \
631 || NORTHBRIDGE_VIA_CX700 \
632 || NORTHBRIDGE_AMD_AMDK8)
634 This option enables additional SMBus (and SPD) debug messages.
636 Note: This option will increase the size of the coreboot image.
641 bool "Output verbose SMI debug messages"
643 depends on HAVE_SMI_HANDLER
645 This option enables additional SMI related debug messages.
647 Note: This option will increase the size of the coreboot image.
652 bool "Output verbose x86emu debug messages"
654 depends on PCI_OPTION_ROM_RUN_YABEL
656 This option enables additional x86emu related debug messages.
658 Note: This option will increase the size of the coreboot image.
662 config X86EMU_DEBUG_JMP
663 bool "Trace JMP/RETF"
665 depends on X86EMU_DEBUG
667 Print information about JMP and RETF opcodes from x86emu.
669 Note: This option will increase the size of the coreboot image.
673 config X86EMU_DEBUG_TRACE
674 bool "Trace all opcodes"
676 depends on X86EMU_DEBUG
678 Print _all_ opcodes that are executed by x86emu.
680 WARNING: This will produce a LOT of output and take a long time.
682 Note: This option will increase the size of the coreboot image.
686 config X86EMU_DEBUG_PNP
687 bool "Log Plug&Play accesses"
689 depends on X86EMU_DEBUG
691 Print Plug And Play accesses made by option ROMs.
693 Note: This option will increase the size of the coreboot image.
697 config X86EMU_DEBUG_DISK
700 depends on X86EMU_DEBUG
702 Print Disk I/O related messages.
704 Note: This option will increase the size of the coreboot image.
708 config X86EMU_DEBUG_PMM
711 depends on X86EMU_DEBUG
713 Print messages related to POST Memory Manager (PMM).
715 Note: This option will increase the size of the coreboot image.
720 config X86EMU_DEBUG_VBE
721 bool "Debug VESA BIOS Extensions"
723 depends on X86EMU_DEBUG
725 Print messages related to VESA BIOS Extension (VBE) functions.
727 Note: This option will increase the size of the coreboot image.
731 config X86EMU_DEBUG_INT10
732 bool "Redirect INT10 output to console"
734 depends on X86EMU_DEBUG
736 Let INT10 (i.e. character output) calls print messages to debug output.
738 Note: This option will increase the size of the coreboot image.
742 config X86EMU_DEBUG_INTERRUPTS
743 bool "Log intXX calls"
745 depends on X86EMU_DEBUG
747 Print messages related to interrupt handling.
749 Note: This option will increase the size of the coreboot image.
753 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
754 bool "Log special memory accesses"
756 depends on X86EMU_DEBUG
758 Print messages related to accesses to certain areas of the virtual
759 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
761 Note: This option will increase the size of the coreboot image.
765 config X86EMU_DEBUG_MEM
766 bool "Log all memory accesses"
768 depends on X86EMU_DEBUG
770 Print memory accesses made by option ROM.
771 Note: This also includes accesses to fetch instructions.
773 Note: This option will increase the size of the coreboot image.
777 config X86EMU_DEBUG_IO
778 bool "Log IO accesses"
780 depends on X86EMU_DEBUG
782 Print I/O accesses made by option ROM.
784 Note: This option will increase the size of the coreboot image.
789 bool "Built-in low-level shell"
792 If enabled, you will have a low level shell to examine your machine.
793 Put llshell() in your (romstage) code to start the shell.
794 See src/arch/i386/llshell/llshell.inc for details.
798 config LIFT_BSP_APIC_ID
802 # These probably belong somewhere else, but they are needed somewhere.
803 config AP_CODE_IN_CAR
811 config ENABLE_APIC_EXT_ID
815 config WARNINGS_ARE_ERRORS
819 config ID_SECTION_OFFSET
823 source src/Kconfig.deprecated_options