2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
83 config USE_OPTION_TABLE
84 bool "Use CMOS for configuration values"
87 Enable this option if coreboot shall read options from the "CMOS"
88 NVRAM instead of using hard coded values.
92 source src/mainboard/Kconfig
93 source src/arch/i386/Kconfig
98 source src/cpu/Kconfig
100 source src/northbridge/Kconfig
101 comment "Southbridge"
102 source src/southbridge/Kconfig
104 source src/superio/Kconfig
106 source src/devices/Kconfig
110 menu "Generic Drivers"
111 source src/drivers/Kconfig
114 config PCI_BUS_SEGN_BITS
118 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
122 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
142 config USE_PRINTK_IN_CAR
150 config MMCONF_SUPPORT_DEFAULT
154 config MMCONF_SUPPORT
161 source src/console/Kconfig
163 config HAVE_ACPI_RESUME
167 config HAVE_ACPI_SLIC
171 config ACPI_SSDTX_NUM
175 config HAVE_HARD_RESET
177 default y if BOARD_HAS_HARD_RESET
180 This variable specifies whether a given board has a hard_reset
181 function, no matter if it's provided by board code or chipset code.
183 config HAVE_INIT_TIMER
185 default n if UDELAY_IO
188 config HAVE_MAINBOARD_RESOURCES
192 config HAVE_OPTION_TABLE
196 This variable specifies whether a given board has a cmos.layout
197 file containing NVRAM/CMOS bit definitions.
198 It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
204 config HAVE_SMI_HANDLER
208 config PCI_IO_CFG_EXT
216 # TODO: Can probably be removed once all chipsets have kconfig options for it.
221 config USE_WATCHDOG_ON_BOOT
229 Build board-specific VGA code.
235 Enable Unified Memory Architecture for graphics.
242 #TODO Remove this option or make it useful.
243 config HAVE_LOW_TABLES
247 This Option is unused in the code. Since two boards try to set it to
248 'n', they may be broken. We either need to make the option useful or
249 get rid of it. The broken boards are:
253 config HAVE_HIGH_TABLES
257 This variable specifies whether a given northbridge has high table
259 It is set in northbridge/*/Kconfig.
260 Whether or not the high tables are actually written by coreboot is
261 configurable by the user via WRITE_HIGH_TABLES.
263 config HAVE_ACPI_TABLES
266 This variable specifies whether a given board has ACPI table support.
267 It is usually set in mainboard/*/Kconfig.
268 Whether or not the ACPI tables are actually generated by coreboot
269 is configurable by the user via GENERATE_ACPI_TABLES.
274 This variable specifies whether a given board has MP table support.
275 It is usually set in mainboard/*/Kconfig.
276 Whether or not the MP table is actually generated by coreboot
277 is configurable by the user via GENERATE_MP_TABLE.
279 config HAVE_PIRQ_TABLE
282 This variable specifies whether a given board has PIRQ table support.
283 It is usually set in mainboard/*/Kconfig.
284 Whether or not the PIRQ table is actually generated by coreboot
285 is configurable by the user via GENERATE_PIRQ_TABLE.
287 #These Options are here to avoid "undefined" warnings.
288 #The actual selection and help texts are in the following menu.
290 config GENERATE_ACPI_TABLES
292 default HAVE_ACPI_TABLES
294 config GENERATE_MP_TABLE
296 default HAVE_MP_TABLE
298 config GENERATE_PIRQ_TABLE
300 default HAVE_PIRQ_TABLE
302 config WRITE_HIGH_TABLES
304 default HAVE_HIGH_TABLES
308 config WRITE_HIGH_TABLES
309 bool "Write 'high' tables to avoid being overwritten in F segment"
310 depends on HAVE_HIGH_TABLES
314 bool "Generate Multiboot tables (for GRUB2)"
317 config GENERATE_ACPI_TABLES
318 depends on HAVE_ACPI_TABLES
319 bool "Generate ACPI tables"
322 Generate ACPI tables for this board.
326 config GENERATE_MP_TABLE
327 depends on HAVE_MP_TABLE
328 bool "Generate an MP table"
331 Generate an MP table (conforming to the Intel MultiProcessor
332 specification 1.4) for this board.
336 config GENERATE_PIRQ_TABLE
337 depends on HAVE_PIRQ_TABLE
338 bool "Generate a PIRQ table"
341 Generate a PIRQ table for this board.
350 prompt "Add a payload"
356 Select this option if you want to create an "empty" coreboot
357 ROM image for a certain mainboard, i.e. a coreboot ROM image
358 which does not yet contain a payload.
360 For such an image to be useful, you have to use 'cbfstool'
361 to add a payload to the ROM image later.
364 bool "An ELF executable payload"
366 Select this option if you have a payload image (an ELF file)
367 which coreboot should run as soon as the basic hardware
368 initialization is completed.
370 You will be able to specify the location and file name of the
375 config FALLBACK_PAYLOAD_FILE
376 string "Payload path and filename"
377 depends on PAYLOAD_ELF
378 default "payload.elf"
380 The path and filename of the ELF executable file to use as payload.
382 # TODO: Defined if no payload? Breaks build?
383 config COMPRESSED_PAYLOAD_LZMA
384 bool "Use LZMA compression for payloads"
386 depends on PAYLOAD_ELF
388 In order to reduce the size payloads take up in the ROM chip
389 coreboot can compress them using the LZMA algorithm.
391 config COMPRESSED_PAYLOAD_NRV2B
400 bool "Add a VGA BIOS image"
402 Select this option if you have a VGA BIOS image that you would
403 like to add to your ROM.
405 You will be able to specify the location and file name of the
408 config FALLBACK_VGA_BIOS_FILE
409 string "VGA BIOS path and filename"
411 default "vgabios.bin"
413 The path and filename of the file to use as VGA BIOS.
415 config FALLBACK_VGA_BIOS_ID
416 string "VGA device PCI IDs"
420 The comma-separated PCI vendor and device ID that would associate
421 your VGA BIOS to your video card.
425 In the above example 1106 is the PCI vendor ID (in hex, but without
426 the "0x" prefix) and 3230 specifies the PCI device ID of the
427 video card (also in hex, without "0x" prefix).
430 bool "Add an MBI image"
431 depends on NORTHBRIDGE_INTEL_I82830
433 Select this option if you have an Intel MBI image that you would
434 like to add to your ROM.
436 You will be able to specify the location and file name of the
439 config FALLBACK_MBI_FILE
440 string "Intel MBI path and filename"
444 The path and filename of the file to use as VGA BIOS.
449 depends on PCI_OPTION_ROM_RUN_YABEL
452 prompt "Show graphical bootsplash"
454 depends on PCI_OPTION_ROM_RUN_YABEL
456 This option shows a graphical bootsplash screen. The grapics are
457 loaded from the CBFS file bootsplash.jpg.
459 config FALLBACK_BOOTSPLASH_FILE
460 string "Bootsplash path and filename"
461 depends on BOOTSPLASH
462 default "bootsplash.jpg"
464 The path and filename of the file to use as graphical bootsplash
465 screen. The file format has to be jpg.
467 # TODO: Turn this into a "choice".
468 config FRAMEBUFFER_VESA_MODE
469 prompt "VESA framebuffer video mode"
472 depends on BOOTSPLASH
474 This option sets the resolution used for the coreboot framebuffer and
475 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
476 some day make this a "choice".
478 config COREBOOT_KEEP_FRAMEBUFFER
479 prompt "Keep VESA framebuffer"
481 depends on BOOTSPLASH
483 This option keeps the framebuffer mode set after coreboot finishes
484 execution. If this option is enabled, coreboot will pass a
485 framebuffer entry in its coreboot table and the payload will need a
486 framebuffer driver. If this option is disabled, coreboot will switch
487 back to text mode before handing control to a payload.
493 # TODO: Better help text and detailed instructions.
495 bool "GDB debugging support"
498 If enabled, you will be able to set breakpoints for gdb debugging.
499 See src/arch/i386/lib/c_start.S for details.
501 config DEBUG_RAM_SETUP
502 bool "Output verbose RAM init debug messages"
504 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
505 || NORTHBRIDGE_AMD_AMDK8 \
506 || NORTHBRIDGE_VIA_CN700 \
507 || NORTHBRIDGE_VIA_CX700 \
508 || NORTHBRIDGE_VIA_VX800 \
509 || NORTHBRIDGE_INTEL_E7501 \
510 || NORTHBRIDGE_INTEL_I440BX \
511 || NORTHBRIDGE_INTEL_I82810 \
512 || NORTHBRIDGE_INTEL_I82830 \
513 || NORTHBRIDGE_INTEL_I945)
515 This option enables additional RAM init related debug messages.
516 It is recommended to enable this when debugging issues on your
517 board which might be RAM init related.
519 Note: This option will increase the size of the coreboot image.
524 bool "Check PIRQ table consistency"
526 depends on GENERATE_PIRQ_TABLE
531 bool "Output verbose SMBus debug messages"
533 depends on (SOUTHBRIDGE_VIA_VT8237R \
534 || NORTHBRIDGE_VIA_VX800 \
535 || NORTHBRIDGE_VIA_CX700 \
536 || NORTHBRIDGE_AMD_AMDK8 \
537 || NORTHBRIDGE_AMD_AMDFAM10 \
538 || BOARD_LIPPERT_SPACERUNNER_LX \
539 || SOUTHBRIDGE_VIA_VT8231)
541 This option enables additional SMBus (and SPD) debug messages.
543 Note: This option will increase the size of the coreboot image.
548 bool "Output verbose SMI debug messages"
550 depends on HAVE_SMI_HANDLER
552 This option enables additional SMI related debug messages.
554 Note: This option will increase the size of the coreboot image.
559 bool "Output verbose x86emu debug messages"
561 depends on PCI_OPTION_ROM_RUN_YABEL
563 This option enables additional x86emu related debug messages.
565 Note: This option will increase the size of the coreboot image.
569 config X86EMU_DEBUG_JMP
570 bool "Trace JMP/RETF"
572 depends on X86EMU_DEBUG
574 Print information about JMP and RETF opcodes from x86emu.
576 Note: This option will increase the size of the coreboot image.
580 config X86EMU_DEBUG_TRACE
581 bool "Trace all opcodes"
583 depends on X86EMU_DEBUG
585 Print _all_ opcodes that are executed by x86emu.
587 WARNING: This will produce a LOT of output and take a long time.
589 Note: This option will increase the size of the coreboot image.
593 config X86EMU_DEBUG_PNP
594 bool "Log Plug&Play accesses"
596 depends on X86EMU_DEBUG
598 Print Plug And Play accesses made by option ROMs.
600 Note: This option will increase the size of the coreboot image.
604 config X86EMU_DEBUG_DISK
607 depends on X86EMU_DEBUG
609 Print Disk I/O related messages.
611 Note: This option will increase the size of the coreboot image.
615 config X86EMU_DEBUG_PMM
618 depends on X86EMU_DEBUG
620 Print messages related to POST Memory Manager (PMM).
622 Note: This option will increase the size of the coreboot image.
627 config X86EMU_DEBUG_VBE
628 bool "Debug VESA BIOS Extensions"
630 depends on X86EMU_DEBUG
632 Print messages related to VESA BIOS Extension (VBE) functions.
634 Note: This option will increase the size of the coreboot image.
638 config X86EMU_DEBUG_INT10
639 bool "Redirect INT10 output to console"
641 depends on X86EMU_DEBUG
643 Let INT10 (i.e. character output) calls print messages to debug output.
645 Note: This option will increase the size of the coreboot image.
649 config X86EMU_DEBUG_INTERRUPTS
650 bool "Log intXX calls"
652 depends on X86EMU_DEBUG
654 Print messages related to interrupt handling.
656 Note: This option will increase the size of the coreboot image.
660 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
661 bool "Log special memory accesses"
663 depends on X86EMU_DEBUG
665 Print messages related to accesses to certain areas of the virtual
666 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
668 Note: This option will increase the size of the coreboot image.
672 config X86EMU_DEBUG_MEM
673 bool "Log all memory accesses"
675 depends on X86EMU_DEBUG
677 Print memory accesses made by option ROM.
678 Note: This also includes accesses to fetch instructions.
680 Note: This option will increase the size of the coreboot image.
684 config X86EMU_DEBUG_IO
685 bool "Log IO accesses"
687 depends on X86EMU_DEBUG
689 Print I/O accesses made by option ROM.
691 Note: This option will increase the size of the coreboot image.
696 bool "Built-in low-level shell"
699 If enabled, you will have a low level shell to examine your machine.
700 Put llshell() in your (romstage) code to start the shell.
701 See src/arch/i386/llshell/llshell.inc for details.
705 config LIFT_BSP_APIC_ID
709 # These probably belong somewhere else, but they are needed somewhere.
710 config AP_CODE_IN_CAR
714 config ENABLE_APIC_EXT_ID
718 config WARNINGS_ARE_ERRORS
722 config ID_SECTION_OFFSET
726 source src/Kconfig.deprecated_options