2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
83 config SCONFIG_GENPARSER
84 bool "Generate SCONFIG parser using flex and bison"
88 Enable this option if you are working on the sconfig
89 device tree parser and made changes to sconfig.l and
93 config USE_OPTION_TABLE
94 bool "Use CMOS for configuration values"
96 depends on HAVE_OPTION_TABLE
98 Enable this option if coreboot shall read options from the "CMOS"
99 NVRAM instead of using hard coded values.
101 config COMPRESS_RAMSTAGE
102 bool "Compress ramstage with LZMA"
105 Compress ramstage to save memory in the flash image. Note
106 that decompression might slow down booting if the boot flash
107 is connected through a slow Link (i.e. SPI)
111 source src/mainboard/Kconfig
113 # This option is used to set the architecture of a mainboard to X86.
114 # It is usually set in mainboard/*/Kconfig.
120 source src/arch/x86/Kconfig
126 source src/cpu/Kconfig
127 comment "Northbridge"
128 source src/northbridge/Kconfig
129 comment "Southbridge"
130 source src/southbridge/Kconfig
132 source src/superio/Kconfig
134 source src/devices/Kconfig
135 comment "Embedded Controllers"
136 source src/ec/Kconfig
140 menu "Generic Drivers"
141 source src/drivers/Kconfig
144 config PCI_BUS_SEGN_BITS
160 config MMCONF_SUPPORT_DEFAULT
164 config MMCONF_SUPPORT
168 source src/console/Kconfig
170 # This should default to N and be set by SuperI/O drivers that have an UART
171 config HAVE_UART_IO_MAPPED
175 config HAVE_UART_MEMORY_MAPPED
179 config HAVE_ACPI_RESUME
183 config HAVE_ACPI_SLIC
187 config ACPI_SSDTX_NUM
191 config HAVE_HARD_RESET
193 default y if BOARD_HAS_HARD_RESET
196 This variable specifies whether a given board has a hard_reset
197 function, no matter if it's provided by board code or chipset code.
199 config HAVE_INIT_TIMER
201 default n if UDELAY_IO
204 config HAVE_MAINBOARD_RESOURCES
208 config USE_OPTION_TABLE
212 config HAVE_OPTION_TABLE
216 This variable specifies whether a given board has a cmos.layout
217 file containing NVRAM/CMOS bit definitions.
218 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
224 config HAVE_SMI_HANDLER
228 config PCI_IO_CFG_EXT
236 # TODO: Can probably be removed once all chipsets have kconfig options for it.
241 config USE_WATCHDOG_ON_BOOT
249 Build board-specific VGA code.
255 Enable Unified Memory Architecture for graphics.
262 config HAVE_ACPI_TABLES
265 This variable specifies whether a given board has ACPI table support.
266 It is usually set in mainboard/*/Kconfig.
267 Whether or not the ACPI tables are actually generated by coreboot
268 is configurable by the user via GENERATE_ACPI_TABLES.
273 This variable specifies whether a given board has MP table support.
274 It is usually set in mainboard/*/Kconfig.
275 Whether or not the MP table is actually generated by coreboot
276 is configurable by the user via GENERATE_MP_TABLE.
278 config HAVE_PIRQ_TABLE
281 This variable specifies whether a given board has PIRQ table support.
282 It is usually set in mainboard/*/Kconfig.
283 Whether or not the PIRQ table is actually generated by coreboot
284 is configurable by the user via GENERATE_PIRQ_TABLE.
286 #These Options are here to avoid "undefined" warnings.
287 #The actual selection and help texts are in the following menu.
289 config GENERATE_ACPI_TABLES
291 default HAVE_ACPI_TABLES
293 config GENERATE_MP_TABLE
295 default HAVE_MP_TABLE
297 config GENERATE_PIRQ_TABLE
299 default HAVE_PIRQ_TABLE
303 config WRITE_HIGH_TABLES
304 bool "Write 'high' tables to avoid being overwritten in F segment"
308 bool "Generate Multiboot tables (for GRUB2)"
311 config GENERATE_ACPI_TABLES
312 depends on HAVE_ACPI_TABLES
313 bool "Generate ACPI tables"
316 Generate ACPI tables for this board.
320 config GENERATE_MP_TABLE
321 depends on HAVE_MP_TABLE
322 bool "Generate an MP table"
325 Generate an MP table (conforming to the Intel MultiProcessor
326 specification 1.4) for this board.
330 config GENERATE_PIRQ_TABLE
331 depends on HAVE_PIRQ_TABLE
332 bool "Generate a PIRQ table"
335 Generate a PIRQ table for this board.
344 prompt "Add a payload"
345 default PAYLOAD_NONE if !ARCH_X86
346 default PAYLOAD_SEABIOS if ARCH_X86
351 Select this option if you want to create an "empty" coreboot
352 ROM image for a certain mainboard, i.e. a coreboot ROM image
353 which does not yet contain a payload.
355 For such an image to be useful, you have to use 'cbfstool'
356 to add a payload to the ROM image later.
359 bool "An ELF executable payload"
361 Select this option if you have a payload image (an ELF file)
362 which coreboot should run as soon as the basic hardware
363 initialization is completed.
365 You will be able to specify the location and file name of the
368 config PAYLOAD_SEABIOS
372 Select this option if you want to build a coreboot image
373 with a SeaBIOS payload. If you don't know what this is
374 about, just leave it enabled.
376 See http://coreboot.org/Payloads for more information.
381 Select this option if you want to build a coreboot image
382 with a FILO payload. If you don't know what this is
383 about, just leave it enabled.
385 See http://coreboot.org/Payloads for more information.
390 prompt "SeaBIOS version"
391 default SEABIOS_STABLE
392 depends on PAYLOAD_SEABIOS
394 config SEABIOS_STABLE
397 Stable SeaBIOS version
398 config SEABIOS_MASTER
401 Newest SeaBIOS version
405 prompt "FILO version"
407 depends on PAYLOAD_FILO
420 string "Payload path and filename"
421 depends on PAYLOAD_ELF
422 default "payload.elf"
424 The path and filename of the ELF executable file to use as payload.
427 depends on PAYLOAD_SEABIOS
428 default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
431 depends on PAYLOAD_FILO
432 default "payloads/external/FILO/filo/build/filo.elf"
434 # TODO: Defined if no payload? Breaks build?
435 config COMPRESSED_PAYLOAD_LZMA
436 bool "Use LZMA compression for payloads"
438 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO
440 In order to reduce the size payloads take up in the ROM chip
441 coreboot can compress them using the LZMA algorithm.
443 config COMPRESSED_PAYLOAD_NRV2B
452 bool "Add a VGA BIOS image"
454 Select this option if you have a VGA BIOS image that you would
455 like to add to your ROM.
457 You will be able to specify the location and file name of the
461 string "VGA BIOS path and filename"
463 default "vgabios.bin"
465 The path and filename of the file to use as VGA BIOS.
468 string "VGA device PCI IDs"
472 The comma-separated PCI vendor and device ID that would associate
473 your VGA BIOS to your video card.
477 In the above example 1106 is the PCI vendor ID (in hex, but without
478 the "0x" prefix) and 3230 specifies the PCI device ID of the
479 video card (also in hex, without "0x" prefix).
482 bool "Add an MBI image"
483 depends on NORTHBRIDGE_INTEL_I82830
485 Select this option if you have an Intel MBI image that you would
486 like to add to your ROM.
488 You will be able to specify the location and file name of the
492 string "Intel MBI path and filename"
496 The path and filename of the file to use as VGA BIOS.
501 depends on PCI_OPTION_ROM_RUN_YABEL
504 prompt "Show graphical bootsplash"
506 depends on PCI_OPTION_ROM_RUN_YABEL
508 This option shows a graphical bootsplash screen. The grapics are
509 loaded from the CBFS file bootsplash.jpg.
511 config BOOTSPLASH_FILE
512 string "Bootsplash path and filename"
513 depends on BOOTSPLASH
514 default "bootsplash.jpg"
516 The path and filename of the file to use as graphical bootsplash
517 screen. The file format has to be jpg.
519 # TODO: Turn this into a "choice".
520 config FRAMEBUFFER_VESA_MODE
521 prompt "VESA framebuffer video mode"
524 depends on BOOTSPLASH
526 This option sets the resolution used for the coreboot framebuffer and
527 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
528 some day make this a "choice".
530 config COREBOOT_KEEP_FRAMEBUFFER
531 prompt "Keep VESA framebuffer"
533 depends on BOOTSPLASH
535 This option keeps the framebuffer mode set after coreboot finishes
536 execution. If this option is enabled, coreboot will pass a
537 framebuffer entry in its coreboot table and the payload will need a
538 framebuffer driver. If this option is disabled, coreboot will switch
539 back to text mode before handing control to a payload.
545 # TODO: Better help text and detailed instructions.
547 bool "GDB debugging support"
550 If enabled, you will be able to set breakpoints for gdb debugging.
551 See src/arch/x86/lib/c_start.S for details.
553 config HAVE_DEBUG_RAM_SETUP
556 config DEBUG_RAM_SETUP
557 bool "Output verbose RAM init debug messages"
559 depends on HAVE_DEBUG_RAM_SETUP
561 This option enables additional RAM init related debug messages.
562 It is recommended to enable this when debugging issues on your
563 board which might be RAM init related.
565 Note: This option will increase the size of the coreboot image.
569 config HAVE_DEBUG_CAR
574 depends on HAVE_DEBUG_CAR
576 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
577 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
578 # printk(BIOS_DEBUG, ...) calls.
580 bool "Output verbose Cache-as-RAM debug messages"
582 depends on HAVE_DEBUG_CAR
584 This option enables additional CAR related debug messages.
588 bool "Check PIRQ table consistency"
590 depends on GENERATE_PIRQ_TABLE
594 config HAVE_DEBUG_SMBUS
598 bool "Output verbose SMBus debug messages"
600 depends on HAVE_DEBUG_SMBUS
602 This option enables additional SMBus (and SPD) debug messages.
604 Note: This option will increase the size of the coreboot image.
609 bool "Output verbose SMI debug messages"
611 depends on HAVE_SMI_HANDLER
613 This option enables additional SMI related debug messages.
615 Note: This option will increase the size of the coreboot image.
619 config DEBUG_SMM_RELOCATION
620 bool "Debug SMM relocation code"
622 depends on HAVE_SMI_HANDLER
624 This option enables additional SMM handler relocation related
627 Note: This option will increase the size of the coreboot image.
634 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
635 # printk(BIOS_DEBUG, ...) calls.
636 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
638 bool "Output verbose malloc debug messages"
641 This option enables additional malloc related debug messages.
643 Note: This option will increase the size of the coreboot image.
648 config REALMODE_DEBUG
650 depends on PCI_OPTION_ROM_RUN_REALMODE
652 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
653 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
654 # printk(BIOS_DEBUG, ...) calls.
655 config REALMODE_DEBUG
656 bool "Enable debug messages for option ROM execution"
658 depends on PCI_OPTION_ROM_RUN_REALMODE
660 This option enables additional x86emu related debug messages.
662 Note: This option will increase the time to emulate a ROM.
668 bool "Output verbose x86emu debug messages"
670 depends on PCI_OPTION_ROM_RUN_YABEL
672 This option enables additional x86emu related debug messages.
674 Note: This option will increase the size of the coreboot image.
678 config X86EMU_DEBUG_JMP
679 bool "Trace JMP/RETF"
681 depends on X86EMU_DEBUG
683 Print information about JMP and RETF opcodes from x86emu.
685 Note: This option will increase the size of the coreboot image.
689 config X86EMU_DEBUG_TRACE
690 bool "Trace all opcodes"
692 depends on X86EMU_DEBUG
694 Print _all_ opcodes that are executed by x86emu.
696 WARNING: This will produce a LOT of output and take a long time.
698 Note: This option will increase the size of the coreboot image.
702 config X86EMU_DEBUG_PNP
703 bool "Log Plug&Play accesses"
705 depends on X86EMU_DEBUG
707 Print Plug And Play accesses made by option ROMs.
709 Note: This option will increase the size of the coreboot image.
713 config X86EMU_DEBUG_DISK
716 depends on X86EMU_DEBUG
718 Print Disk I/O related messages.
720 Note: This option will increase the size of the coreboot image.
724 config X86EMU_DEBUG_PMM
727 depends on X86EMU_DEBUG
729 Print messages related to POST Memory Manager (PMM).
731 Note: This option will increase the size of the coreboot image.
736 config X86EMU_DEBUG_VBE
737 bool "Debug VESA BIOS Extensions"
739 depends on X86EMU_DEBUG
741 Print messages related to VESA BIOS Extension (VBE) functions.
743 Note: This option will increase the size of the coreboot image.
747 config X86EMU_DEBUG_INT10
748 bool "Redirect INT10 output to console"
750 depends on X86EMU_DEBUG
752 Let INT10 (i.e. character output) calls print messages to debug output.
754 Note: This option will increase the size of the coreboot image.
758 config X86EMU_DEBUG_INTERRUPTS
759 bool "Log intXX calls"
761 depends on X86EMU_DEBUG
763 Print messages related to interrupt handling.
765 Note: This option will increase the size of the coreboot image.
769 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
770 bool "Log special memory accesses"
772 depends on X86EMU_DEBUG
774 Print messages related to accesses to certain areas of the virtual
775 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
777 Note: This option will increase the size of the coreboot image.
781 config X86EMU_DEBUG_MEM
782 bool "Log all memory accesses"
784 depends on X86EMU_DEBUG
786 Print memory accesses made by option ROM.
787 Note: This also includes accesses to fetch instructions.
789 Note: This option will increase the size of the coreboot image.
793 config X86EMU_DEBUG_IO
794 bool "Log IO accesses"
796 depends on X86EMU_DEBUG
798 Print I/O accesses made by option ROM.
800 Note: This option will increase the size of the coreboot image.
805 bool "Built-in low-level shell"
808 If enabled, you will have a low level shell to examine your machine.
809 Put llshell() in your (romstage) code to start the shell.
810 See src/arch/x86/llshell/llshell.inc for details.
814 config LIFT_BSP_APIC_ID
818 # These probably belong somewhere else, but they are needed somewhere.
819 config AP_CODE_IN_CAR
823 config RAMINIT_SYSINFO
827 config ENABLE_APIC_EXT_ID
831 config WARNINGS_ARE_ERRORS
835 config ID_SECTION_OFFSET
839 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
840 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
841 # mutually exclusive. One of these options must be selected in the
842 # mainboard Kconfig if the chipset supports enabling and disabling of
843 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
844 # in mainboard/Kconfig to know if the button should be enabled or not.
846 config POWER_BUTTON_DEFAULT_ENABLE
849 Select when the board has a power button which can optionally be
850 disabled by the user.
852 config POWER_BUTTON_DEFAULT_DISABLE
855 Select when the board has a power button which can optionally be
856 enabled by the user, e.g. when the board ships with a jumper over
857 the power switch contacts.
859 config POWER_BUTTON_FORCE_ENABLE
862 Select when the board requires that the power button is always
865 config POWER_BUTTON_FORCE_DISABLE
868 Select when the board requires that the power button is always
869 disabled, e.g. when it has been hardwired to ground.
871 config POWER_BUTTON_IS_OPTIONAL
873 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
874 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
876 Internal option that controls ENABLE_POWER_BUTTON visibility.
878 source src/Kconfig.deprecated_options