2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
83 config USE_OPTION_TABLE
84 bool "Use CMOS for configuration values"
87 Enable this option if coreboot shall read options from the "CMOS"
88 NVRAM instead of using hard coded values.
92 source src/mainboard/Kconfig
93 source src/arch/i386/Kconfig
98 source src/cpu/Kconfig
100 source src/northbridge/Kconfig
101 comment "Southbridge"
102 source src/southbridge/Kconfig
104 source src/superio/Kconfig
106 source src/devices/Kconfig
110 menu "Generic Drivers"
111 source src/drivers/Kconfig
114 config PCI_BUS_SEGN_BITS
118 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
122 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
142 config USE_PRINTK_IN_CAR
150 config MMCONF_SUPPORT_DEFAULT
154 config MMCONF_SUPPORT
161 source src/console/Kconfig
163 config HAVE_ACPI_RESUME
167 config ACPI_SSDTX_NUM
171 config HAVE_HARD_RESET
173 default y if BOARD_HAS_HARD_RESET
176 This variable specifies whether a given board has a hard_reset
177 function, no matter if it's provided by board code or chipset code.
179 config HAVE_INIT_TIMER
181 default n if UDELAY_IO
184 config HAVE_MAINBOARD_RESOURCES
188 config HAVE_OPTION_TABLE
192 This variable specifies whether a given board has a cmos.layout
193 file containing NVRAM/CMOS bit definitions.
194 It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
200 config HAVE_SMI_HANDLER
204 config PCI_IO_CFG_EXT
212 # TODO: Can probably be removed once all chipsets have kconfig options for it.
217 config USE_WATCHDOG_ON_BOOT
225 Build board-specific VGA code.
231 Enable Unified Memory Architecture for graphics.
238 #TODO Remove this option or make it useful.
239 config HAVE_LOW_TABLES
243 This Option is unused in the code. Since two boards try to set it to
244 'n', they may be broken. We either need to make the option useful or
245 get rid of it. The broken boards are:
249 config HAVE_HIGH_TABLES
253 This variable specifies whether a given northbridge has high table
255 It is set in northbridge/*/Kconfig.
256 Whether or not the high tables are actually written by coreboot is
257 configurable by the user via WRITE_HIGH_TABLES.
259 config HAVE_ACPI_TABLES
262 This variable specifies whether a given board has ACPI table support.
263 It is usually set in mainboard/*/Kconfig.
264 Whether or not the ACPI tables are actually generated by coreboot
265 is configurable by the user via GENERATE_ACPI_TABLES.
270 This variable specifies whether a given board has MP table support.
271 It is usually set in mainboard/*/Kconfig.
272 Whether or not the MP table is actually generated by coreboot
273 is configurable by the user via GENERATE_MP_TABLE.
275 config HAVE_PIRQ_TABLE
278 This variable specifies whether a given board has PIRQ table support.
279 It is usually set in mainboard/*/Kconfig.
280 Whether or not the PIRQ table is actually generated by coreboot
281 is configurable by the user via GENERATE_PIRQ_TABLE.
283 #These Options are here to avoid "undefined" warnings.
284 #The actual selection and help texts are in the following menu.
286 config GENERATE_ACPI_TABLES
288 default HAVE_ACPI_TABLES
290 config GENERATE_MP_TABLE
292 default HAVE_MP_TABLE
294 config GENERATE_PIRQ_TABLE
296 default HAVE_PIRQ_TABLE
298 config WRITE_HIGH_TABLES
300 default HAVE_HIGH_TABLES
304 config WRITE_HIGH_TABLES
305 bool "Write 'high' tables to avoid being overwritten in F segment"
306 depends on HAVE_HIGH_TABLES
310 bool "Generate Multiboot tables (for GRUB2)"
313 config GENERATE_ACPI_TABLES
314 depends on HAVE_ACPI_TABLES
315 bool "Generate ACPI tables"
318 Generate ACPI tables for this board.
322 config GENERATE_MP_TABLE
323 depends on HAVE_MP_TABLE
324 bool "Generate an MP table"
327 Generate an MP table (conforming to the Intel MultiProcessor
328 specification 1.4) for this board.
332 config GENERATE_PIRQ_TABLE
333 depends on HAVE_PIRQ_TABLE
334 bool "Generate a PIRQ table"
337 Generate a PIRQ table for this board.
346 prompt "Add a payload"
352 Select this option if you want to create an "empty" coreboot
353 ROM image for a certain mainboard, i.e. a coreboot ROM image
354 which does not yet contain a payload.
356 For such an image to be useful, you have to use 'cbfstool'
357 to add a payload to the ROM image later.
360 bool "An ELF executable payload"
362 Select this option if you have a payload image (an ELF file)
363 which coreboot should run as soon as the basic hardware
364 initialization is completed.
366 You will be able to specify the location and file name of the
371 config FALLBACK_PAYLOAD_FILE
372 string "Payload path and filename"
373 depends on PAYLOAD_ELF
374 default "payload.elf"
376 The path and filename of the ELF executable file to use as payload.
378 # TODO: Defined if no payload? Breaks build?
379 config COMPRESSED_PAYLOAD_LZMA
380 bool "Use LZMA compression for payloads"
382 depends on PAYLOAD_ELF
384 In order to reduce the size payloads take up in the ROM chip
385 coreboot can compress them using the LZMA algorithm.
387 config COMPRESSED_PAYLOAD_NRV2B
396 bool "Add a VGA BIOS image"
398 Select this option if you have a VGA BIOS image that you would
399 like to add to your ROM.
401 You will be able to specify the location and file name of the
404 config FALLBACK_VGA_BIOS_FILE
405 string "VGA BIOS path and filename"
407 default "vgabios.bin"
409 The path and filename of the file to use as VGA BIOS.
411 config FALLBACK_VGA_BIOS_ID
412 string "VGA device PCI IDs"
416 The comma-separated PCI vendor and device ID that would associate
417 your VGA BIOS to your video card.
421 In the above example 1106 is the PCI vendor ID (in hex, but without
422 the "0x" prefix) and 3230 specifies the PCI device ID of the
423 video card (also in hex, without "0x" prefix).
426 bool "Add an MBI image"
427 depends on NORTHBRIDGE_INTEL_I82830
429 Select this option if you have an Intel MBI image that you would
430 like to add to your ROM.
432 You will be able to specify the location and file name of the
435 config FALLBACK_MBI_FILE
436 string "Intel MBI path and filename"
440 The path and filename of the file to use as VGA BIOS.
445 depends on PCI_OPTION_ROM_RUN_YABEL
448 prompt "Show graphical bootsplash"
450 depends on PCI_OPTION_ROM_RUN_YABEL
452 This option shows a graphical bootsplash screen. The grapics are
453 loaded from the CBFS file bootsplash.jpg.
455 config FALLBACK_BOOTSPLASH_FILE
456 string "Bootsplash path and filename"
457 depends on BOOTSPLASH
458 default "bootsplash.jpg"
460 The path and filename of the file to use as graphical bootsplash
461 screen. The file format has to be jpg.
463 # TODO: Turn this into a "choice".
464 config FRAMEBUFFER_VESA_MODE
465 prompt "VESA framebuffer video mode"
468 depends on BOOTSPLASH
470 This option sets the resolution used for the coreboot framebuffer and
471 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
472 some day make this a "choice".
474 config COREBOOT_KEEP_FRAMEBUFFER
475 prompt "Keep VESA framebuffer"
477 depends on BOOTSPLASH
479 This option keeps the framebuffer mode set after coreboot finishes
480 execution. If this option is enabled, coreboot will pass a
481 framebuffer entry in its coreboot table and the payload will need a
482 framebuffer driver. If this option is disabled, coreboot will switch
483 back to text mode before handing control to a payload.
489 # TODO: Better help text and detailed instructions.
491 bool "GDB debugging support"
494 If enabled, you will be able to set breakpoints for gdb debugging.
495 See src/arch/i386/lib/c_start.S for details.
497 config DEBUG_RAM_SETUP
498 bool "Output verbose RAM init debug messages"
500 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
501 || NORTHBRIDGE_AMD_AMDK8 \
502 || NORTHBRIDGE_VIA_CN700 \
503 || NORTHBRIDGE_VIA_CX700 \
504 || NORTHBRIDGE_VIA_VX800 \
505 || NORTHBRIDGE_INTEL_E7501 \
506 || NORTHBRIDGE_INTEL_I440BX \
507 || NORTHBRIDGE_INTEL_I82810 \
508 || NORTHBRIDGE_INTEL_I82830 \
509 || NORTHBRIDGE_INTEL_I945)
511 This option enables additional RAM init related debug messages.
512 It is recommended to enable this when debugging issues on your
513 board which might be RAM init related.
515 Note: This option will increase the size of the coreboot image.
520 bool "Check PIRQ table consistency"
522 depends on GENERATE_PIRQ_TABLE
527 bool "Output verbose SMBus debug messages"
529 depends on (SOUTHBRIDGE_VIA_VT8237R \
530 || NORTHBRIDGE_VIA_VX800 \
531 || NORTHBRIDGE_VIA_CX700 \
532 || NORTHBRIDGE_AMD_AMDK8 \
533 || NORTHBRIDGE_AMD_AMDFAM10 \
534 || BOARD_LIPPERT_SPACERUNNER_LX \
535 || SOUTHBRIDGE_VIA_VT8231)
537 This option enables additional SMBus (and SPD) debug messages.
539 Note: This option will increase the size of the coreboot image.
544 bool "Output verbose SMI debug messages"
546 depends on HAVE_SMI_HANDLER
548 This option enables additional SMI related debug messages.
550 Note: This option will increase the size of the coreboot image.
555 bool "Output verbose x86emu debug messages"
557 depends on PCI_OPTION_ROM_RUN_YABEL
559 This option enables additional x86emu related debug messages.
561 Note: This option will increase the size of the coreboot image.
565 config X86EMU_DEBUG_JMP
566 bool "Trace JMP/RETF"
568 depends on X86EMU_DEBUG
570 Print information about JMP and RETF opcodes from x86emu.
572 Note: This option will increase the size of the coreboot image.
576 config X86EMU_DEBUG_TRACE
577 bool "Trace all opcodes"
579 depends on X86EMU_DEBUG
581 Print _all_ opcodes that are executed by x86emu.
583 WARNING: This will produce a LOT of output and take a long time.
585 Note: This option will increase the size of the coreboot image.
589 config X86EMU_DEBUG_PNP
590 bool "Log Plug&Play accesses"
592 depends on X86EMU_DEBUG
594 Print Plug And Play accesses made by option ROMs.
596 Note: This option will increase the size of the coreboot image.
600 config X86EMU_DEBUG_DISK
603 depends on X86EMU_DEBUG
605 Print Disk I/O related messages.
607 Note: This option will increase the size of the coreboot image.
611 config X86EMU_DEBUG_PMM
614 depends on X86EMU_DEBUG
616 Print messages related to POST Memory Manager (PMM).
618 Note: This option will increase the size of the coreboot image.
623 config X86EMU_DEBUG_VBE
624 bool "Debug VESA BIOS Extensions"
626 depends on X86EMU_DEBUG
628 Print messages related to VESA BIOS Extension (VBE) functions.
630 Note: This option will increase the size of the coreboot image.
634 config X86EMU_DEBUG_INT10
635 bool "Redirect INT10 output to console"
637 depends on X86EMU_DEBUG
639 Let INT10 (i.e. character output) calls print messages to debug output.
641 Note: This option will increase the size of the coreboot image.
645 config X86EMU_DEBUG_INTERRUPTS
646 bool "Log intXX calls"
648 depends on X86EMU_DEBUG
650 Print messages related to interrupt handling.
652 Note: This option will increase the size of the coreboot image.
656 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
657 bool "Log special memory accesses"
659 depends on X86EMU_DEBUG
661 Print messages related to accesses to certain areas of the virtual
662 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
664 Note: This option will increase the size of the coreboot image.
668 config X86EMU_DEBUG_MEM
669 bool "Log all memory accesses"
671 depends on X86EMU_DEBUG
673 Print memory accesses made by option ROM.
674 Note: This also includes accesses to fetch instructions.
676 Note: This option will increase the size of the coreboot image.
680 config X86EMU_DEBUG_IO
681 bool "Log IO accesses"
683 depends on X86EMU_DEBUG
685 Print I/O accesses made by option ROM.
687 Note: This option will increase the size of the coreboot image.
692 bool "Built-in low-level shell"
695 If enabled, you will have a low level shell to examine your machine.
696 Put llshell() in your (romstage) code to start the shell.
697 See src/arch/i386/llshell/llshell.inc for details.
701 config LIFT_BSP_APIC_ID
705 # These probably belong somewhere else, but they are needed somewhere.
706 config AP_CODE_IN_CAR
710 config ENABLE_APIC_EXT_ID
714 config WARNINGS_ARE_ERRORS
718 config ID_SECTION_OFFSET
722 source src/Kconfig.deprecated_options