2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
83 config SCONFIG_GENPARSER
84 bool "Generate SCONFIG parser using flex and bison"
88 Enable this option if you are working on the sconfig
89 device tree parser and made changes to sconfig.l and
93 config USE_OPTION_TABLE
94 bool "Use CMOS for configuration values"
96 depends on HAVE_OPTION_TABLE
98 Enable this option if coreboot shall read options from the "CMOS"
99 NVRAM instead of using hard coded values.
103 source src/mainboard/Kconfig
105 # This option is used to set the architecture of a mainboard to X86.
106 # It is usually set in mainboard/*/Kconfig.
112 source src/arch/x86/Kconfig
118 source src/cpu/Kconfig
119 comment "Northbridge"
120 source src/northbridge/Kconfig
121 comment "Southbridge"
122 source src/southbridge/Kconfig
124 source src/superio/Kconfig
126 source src/devices/Kconfig
127 comment "Embedded Controllers"
128 source src/ec/Kconfig
132 menu "Generic Drivers"
133 source src/drivers/Kconfig
136 config PCI_BUS_SEGN_BITS
140 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
144 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
159 config MMCONF_SUPPORT_DEFAULT
163 config MMCONF_SUPPORT
170 source src/console/Kconfig
172 config HAVE_ACPI_RESUME
176 config HAVE_ACPI_SLIC
180 config ACPI_SSDTX_NUM
184 config HAVE_HARD_RESET
186 default y if BOARD_HAS_HARD_RESET
189 This variable specifies whether a given board has a hard_reset
190 function, no matter if it's provided by board code or chipset code.
192 config HAVE_INIT_TIMER
194 default n if UDELAY_IO
197 config HAVE_MAINBOARD_RESOURCES
201 config USE_OPTION_TABLE
205 config HAVE_OPTION_TABLE
209 This variable specifies whether a given board has a cmos.layout
210 file containing NVRAM/CMOS bit definitions.
211 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
217 config HAVE_SMI_HANDLER
221 config PCI_IO_CFG_EXT
229 # TODO: Can probably be removed once all chipsets have kconfig options for it.
234 config USE_WATCHDOG_ON_BOOT
242 Build board-specific VGA code.
248 Enable Unified Memory Architecture for graphics.
255 config HAVE_ACPI_TABLES
258 This variable specifies whether a given board has ACPI table support.
259 It is usually set in mainboard/*/Kconfig.
260 Whether or not the ACPI tables are actually generated by coreboot
261 is configurable by the user via GENERATE_ACPI_TABLES.
266 This variable specifies whether a given board has MP table support.
267 It is usually set in mainboard/*/Kconfig.
268 Whether or not the MP table is actually generated by coreboot
269 is configurable by the user via GENERATE_MP_TABLE.
271 config HAVE_PIRQ_TABLE
274 This variable specifies whether a given board has PIRQ table support.
275 It is usually set in mainboard/*/Kconfig.
276 Whether or not the PIRQ table is actually generated by coreboot
277 is configurable by the user via GENERATE_PIRQ_TABLE.
279 #These Options are here to avoid "undefined" warnings.
280 #The actual selection and help texts are in the following menu.
282 config GENERATE_ACPI_TABLES
284 default HAVE_ACPI_TABLES
286 config GENERATE_MP_TABLE
288 default HAVE_MP_TABLE
290 config GENERATE_PIRQ_TABLE
292 default HAVE_PIRQ_TABLE
296 config WRITE_HIGH_TABLES
297 bool "Write 'high' tables to avoid being overwritten in F segment"
301 bool "Generate Multiboot tables (for GRUB2)"
304 config GENERATE_ACPI_TABLES
305 depends on HAVE_ACPI_TABLES
306 bool "Generate ACPI tables"
309 Generate ACPI tables for this board.
313 config GENERATE_MP_TABLE
314 depends on HAVE_MP_TABLE
315 bool "Generate an MP table"
318 Generate an MP table (conforming to the Intel MultiProcessor
319 specification 1.4) for this board.
323 config GENERATE_PIRQ_TABLE
324 depends on HAVE_PIRQ_TABLE
325 bool "Generate a PIRQ table"
328 Generate a PIRQ table for this board.
337 prompt "Add a payload"
338 default PAYLOAD_NONE if !ARCH_X86
339 default PAYLOAD_SEABIOS if ARCH_X86
344 Select this option if you want to create an "empty" coreboot
345 ROM image for a certain mainboard, i.e. a coreboot ROM image
346 which does not yet contain a payload.
348 For such an image to be useful, you have to use 'cbfstool'
349 to add a payload to the ROM image later.
352 bool "An ELF executable payload"
354 Select this option if you have a payload image (an ELF file)
355 which coreboot should run as soon as the basic hardware
356 initialization is completed.
358 You will be able to specify the location and file name of the
361 config PAYLOAD_SEABIOS
365 Select this option if you want to build a coreboot image
366 with a SeaBIOS payload. If you don't know what this is
367 about, just leave it enabled.
369 See http://coreboot.org/Payloads for more information.
374 prompt "SeaBIOS version"
375 default SEABIOS_STABLE
376 depends on PAYLOAD_SEABIOS
378 config SEABIOS_STABLE
381 Stable SeaBIOS version
382 config SEABIOS_MASTER
385 Newest SeaBIOS version
389 string "Payload path and filename"
390 depends on PAYLOAD_ELF
391 default "payload.elf"
393 The path and filename of the ELF executable file to use as payload.
396 depends on PAYLOAD_SEABIOS
397 default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
399 # TODO: Defined if no payload? Breaks build?
400 config COMPRESSED_PAYLOAD_LZMA
401 bool "Use LZMA compression for payloads"
403 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS
405 In order to reduce the size payloads take up in the ROM chip
406 coreboot can compress them using the LZMA algorithm.
408 config COMPRESSED_PAYLOAD_NRV2B
417 bool "Add a VGA BIOS image"
419 Select this option if you have a VGA BIOS image that you would
420 like to add to your ROM.
422 You will be able to specify the location and file name of the
426 string "VGA BIOS path and filename"
428 default "vgabios.bin"
430 The path and filename of the file to use as VGA BIOS.
433 string "VGA device PCI IDs"
437 The comma-separated PCI vendor and device ID that would associate
438 your VGA BIOS to your video card.
442 In the above example 1106 is the PCI vendor ID (in hex, but without
443 the "0x" prefix) and 3230 specifies the PCI device ID of the
444 video card (also in hex, without "0x" prefix).
447 bool "Add an MBI image"
448 depends on NORTHBRIDGE_INTEL_I82830
450 Select this option if you have an Intel MBI image that you would
451 like to add to your ROM.
453 You will be able to specify the location and file name of the
457 string "Intel MBI path and filename"
461 The path and filename of the file to use as VGA BIOS.
466 depends on PCI_OPTION_ROM_RUN_YABEL
469 prompt "Show graphical bootsplash"
471 depends on PCI_OPTION_ROM_RUN_YABEL
473 This option shows a graphical bootsplash screen. The grapics are
474 loaded from the CBFS file bootsplash.jpg.
476 config BOOTSPLASH_FILE
477 string "Bootsplash path and filename"
478 depends on BOOTSPLASH
479 default "bootsplash.jpg"
481 The path and filename of the file to use as graphical bootsplash
482 screen. The file format has to be jpg.
484 # TODO: Turn this into a "choice".
485 config FRAMEBUFFER_VESA_MODE
486 prompt "VESA framebuffer video mode"
489 depends on BOOTSPLASH
491 This option sets the resolution used for the coreboot framebuffer and
492 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
493 some day make this a "choice".
495 config COREBOOT_KEEP_FRAMEBUFFER
496 prompt "Keep VESA framebuffer"
498 depends on BOOTSPLASH
500 This option keeps the framebuffer mode set after coreboot finishes
501 execution. If this option is enabled, coreboot will pass a
502 framebuffer entry in its coreboot table and the payload will need a
503 framebuffer driver. If this option is disabled, coreboot will switch
504 back to text mode before handing control to a payload.
510 # TODO: Better help text and detailed instructions.
512 bool "GDB debugging support"
515 If enabled, you will be able to set breakpoints for gdb debugging.
516 See src/arch/x86/lib/c_start.S for details.
518 config HAVE_DEBUG_RAM_SETUP
521 config DEBUG_RAM_SETUP
522 bool "Output verbose RAM init debug messages"
524 depends on HAVE_DEBUG_RAM_SETUP
526 This option enables additional RAM init related debug messages.
527 It is recommended to enable this when debugging issues on your
528 board which might be RAM init related.
530 Note: This option will increase the size of the coreboot image.
534 config HAVE_DEBUG_CAR
539 depends on HAVE_DEBUG_CAR
541 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
542 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
543 # printk(BIOS_DEBUG, ...) calls.
545 bool "Output verbose Cache-as-RAM debug messages"
547 depends on HAVE_DEBUG_CAR
549 This option enables additional CAR related debug messages.
553 bool "Check PIRQ table consistency"
555 depends on GENERATE_PIRQ_TABLE
559 config HAVE_DEBUG_SMBUS
563 bool "Output verbose SMBus debug messages"
565 depends on HAVE_DEBUG_SMBUS
567 This option enables additional SMBus (and SPD) debug messages.
569 Note: This option will increase the size of the coreboot image.
574 bool "Output verbose SMI debug messages"
576 depends on HAVE_SMI_HANDLER
578 This option enables additional SMI related debug messages.
580 Note: This option will increase the size of the coreboot image.
584 config DEBUG_SMM_RELOCATION
585 bool "Debug SMM relocation code"
587 depends on HAVE_SMI_HANDLER
589 This option enables additional SMM handler relocation related
592 Note: This option will increase the size of the coreboot image.
599 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
600 # printk(BIOS_DEBUG, ...) calls.
601 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
603 bool "Output verbose malloc debug messages"
606 This option enables additional malloc related debug messages.
608 Note: This option will increase the size of the coreboot image.
613 config REALMODE_DEBUG
615 depends on PCI_OPTION_ROM_RUN_REALMODE
617 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
618 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
619 # printk(BIOS_DEBUG, ...) calls.
620 config REALMODE_DEBUG
621 bool "Enable debug messages for option ROM execution"
623 depends on PCI_OPTION_ROM_RUN_REALMODE
625 This option enables additional x86emu related debug messages.
627 Note: This option will increase the time to emulate a ROM.
633 bool "Output verbose x86emu debug messages"
635 depends on PCI_OPTION_ROM_RUN_YABEL
637 This option enables additional x86emu related debug messages.
639 Note: This option will increase the size of the coreboot image.
643 config X86EMU_DEBUG_JMP
644 bool "Trace JMP/RETF"
646 depends on X86EMU_DEBUG
648 Print information about JMP and RETF opcodes from x86emu.
650 Note: This option will increase the size of the coreboot image.
654 config X86EMU_DEBUG_TRACE
655 bool "Trace all opcodes"
657 depends on X86EMU_DEBUG
659 Print _all_ opcodes that are executed by x86emu.
661 WARNING: This will produce a LOT of output and take a long time.
663 Note: This option will increase the size of the coreboot image.
667 config X86EMU_DEBUG_PNP
668 bool "Log Plug&Play accesses"
670 depends on X86EMU_DEBUG
672 Print Plug And Play accesses made by option ROMs.
674 Note: This option will increase the size of the coreboot image.
678 config X86EMU_DEBUG_DISK
681 depends on X86EMU_DEBUG
683 Print Disk I/O related messages.
685 Note: This option will increase the size of the coreboot image.
689 config X86EMU_DEBUG_PMM
692 depends on X86EMU_DEBUG
694 Print messages related to POST Memory Manager (PMM).
696 Note: This option will increase the size of the coreboot image.
701 config X86EMU_DEBUG_VBE
702 bool "Debug VESA BIOS Extensions"
704 depends on X86EMU_DEBUG
706 Print messages related to VESA BIOS Extension (VBE) functions.
708 Note: This option will increase the size of the coreboot image.
712 config X86EMU_DEBUG_INT10
713 bool "Redirect INT10 output to console"
715 depends on X86EMU_DEBUG
717 Let INT10 (i.e. character output) calls print messages to debug output.
719 Note: This option will increase the size of the coreboot image.
723 config X86EMU_DEBUG_INTERRUPTS
724 bool "Log intXX calls"
726 depends on X86EMU_DEBUG
728 Print messages related to interrupt handling.
730 Note: This option will increase the size of the coreboot image.
734 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
735 bool "Log special memory accesses"
737 depends on X86EMU_DEBUG
739 Print messages related to accesses to certain areas of the virtual
740 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
742 Note: This option will increase the size of the coreboot image.
746 config X86EMU_DEBUG_MEM
747 bool "Log all memory accesses"
749 depends on X86EMU_DEBUG
751 Print memory accesses made by option ROM.
752 Note: This also includes accesses to fetch instructions.
754 Note: This option will increase the size of the coreboot image.
758 config X86EMU_DEBUG_IO
759 bool "Log IO accesses"
761 depends on X86EMU_DEBUG
763 Print I/O accesses made by option ROM.
765 Note: This option will increase the size of the coreboot image.
770 bool "Built-in low-level shell"
773 If enabled, you will have a low level shell to examine your machine.
774 Put llshell() in your (romstage) code to start the shell.
775 See src/arch/x86/llshell/llshell.inc for details.
779 config LIFT_BSP_APIC_ID
783 # These probably belong somewhere else, but they are needed somewhere.
784 config AP_CODE_IN_CAR
788 config RAMINIT_SYSINFO
792 config ENABLE_APIC_EXT_ID
796 config WARNINGS_ARE_ERRORS
800 config ID_SECTION_OFFSET
804 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
805 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
806 # mutually exclusive. One of these options must be selected in the
807 # mainboard Kconfig if the chipset supports enabling and disabling of
808 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
809 # in mainboard/Kconfig to know if the button should be enabled or not.
811 config POWER_BUTTON_DEFAULT_ENABLE
814 Select when the board has a power button which can optionally be
815 disabled by the user.
817 config POWER_BUTTON_DEFAULT_DISABLE
820 Select when the board has a power button which can optionally be
821 enabled by the user, e.g. when the board ships with a jumper over
822 the power switch contacts.
824 config POWER_BUTTON_FORCE_ENABLE
827 Select when the board requires that the power button is always
830 config POWER_BUTTON_FORCE_DISABLE
833 Select when the board requires that the power button is always
834 disabled, e.g. when it has been hardwired to ground.
836 config POWER_BUTTON_IS_OPTIONAL
838 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
839 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
841 Internal option that controls ENABLE_POWER_BUTTON visibility.
843 source src/Kconfig.deprecated_options