2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
85 source src/mainboard/Kconfig
86 source src/arch/i386/Kconfig
91 source src/cpu/Kconfig
93 source src/northbridge/Kconfig
95 source src/southbridge/Kconfig
97 source src/superio/Kconfig
99 source src/devices/Kconfig
103 config PCI_BUS_SEGN_BITS
107 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
111 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
143 config USE_PRINTK_IN_CAR
147 config USE_OPTION_TABLE
155 config MMCONF_SUPPORT_DEFAULT
159 config MMCONF_SUPPORT
170 source src/console/Kconfig
172 config HAVE_ACPI_RESUME
176 config ACPI_SSDTX_NUM
180 config HAVE_HARD_RESET
182 default y if BOARD_HAS_HARD_RESET
185 This variable specifies whether a given board has a hard_reset
186 function, no matter if it's provided by board code or chipset code.
188 config HAVE_INIT_TIMER
190 default n if UDELAY_IO
193 config HAVE_MAINBOARD_RESOURCES
197 config HAVE_OPTION_TABLE
201 This variable specifies whether a given board has a cmos.layout
202 file containing NVRAM/CMOS bit definitions.
203 It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
209 config HAVE_SMI_HANDLER
213 config PCI_IO_CFG_EXT
221 # TODO: Can probably be removed once all chipsets have kconfig options for it.
226 config USE_WATCHDOG_ON_BOOT
234 Build board-specific VGA code.
240 Enable Unified Memory Architecture for graphics.
247 #TODO Remove this option or make it useful.
248 config HAVE_LOW_TABLES
252 This Option is unused in the code. Since two boards try to set it to
253 'n', they may be broken. We either need to make the option useful or
254 get rid of it. The broken boards are:
258 config HAVE_HIGH_TABLES
262 This variable specifies whether a given northbridge has high table
264 It is set in northbridge/*/Kconfig.
265 Whether or not the high tables are actually written by coreboot is
266 configurable by the user via WRITE_HIGH_TABLES.
268 config HAVE_ACPI_TABLES
271 This variable specifies whether a given board has ACPI table support.
272 It is usually set in mainboard/*/Kconfig.
273 Whether or not the ACPI tables are actually generated by coreboot
274 is configurable by the user via GENERATE_ACPI_TABLES.
279 This variable specifies whether a given board has MP table support.
280 It is usually set in mainboard/*/Kconfig.
281 Whether or not the MP table is actually generated by coreboot
282 is configurable by the user via GENERATE_MP_TABLE.
284 config HAVE_PIRQ_TABLE
287 This variable specifies whether a given board has PIRQ table support.
288 It is usually set in mainboard/*/Kconfig.
289 Whether or not the PIRQ table is actually generated by coreboot
290 is configurable by the user via GENERATE_PIRQ_TABLE.
292 #These Options are here to avoid "undefined" warnings.
293 #The actual selection and help texts are in the following menu.
295 config GENERATE_ACPI_TABLES
297 default HAVE_ACPI_TABLES
299 config GENERATE_MP_TABLE
301 default HAVE_MP_TABLE
303 config GENERATE_PIRQ_TABLE
305 default HAVE_PIRQ_TABLE
307 config WRITE_HIGH_TABLES
309 default HAVE_HIGH_TABLES
313 config WRITE_HIGH_TABLES
314 bool "Write 'high' tables to avoid being overwritten in F segment"
315 depends on HAVE_HIGH_TABLES
319 bool "Generate Multiboot tables (for GRUB2)"
322 config GENERATE_ACPI_TABLES
323 depends on HAVE_ACPI_TABLES
324 bool "Generate ACPI tables"
327 Generate ACPI tables for this board.
331 config GENERATE_MP_TABLE
332 depends on HAVE_MP_TABLE
333 bool "Generate an MP table"
336 Generate an MP table (conforming to the Intel MultiProcessor
337 specification 1.4) for this board.
341 config GENERATE_PIRQ_TABLE
342 depends on HAVE_PIRQ_TABLE
343 bool "Generate a PIRQ table"
346 Generate a PIRQ table for this board.
355 prompt "Add a payload"
361 Select this option if you want to create an "empty" coreboot
362 ROM image for a certain mainboard, i.e. a coreboot ROM image
363 which does not yet contain a payload.
365 For such an image to be useful, you have to use 'cbfstool'
366 to add a payload to the ROM image later.
369 bool "An ELF executable payload"
371 Select this option if you have a payload image (an ELF file)
372 which coreboot should run as soon as the basic hardware
373 initialization is completed.
375 You will be able to specify the location and file name of the
380 config FALLBACK_PAYLOAD_FILE
381 string "Payload path and filename"
382 depends on PAYLOAD_ELF
383 default "payload.elf"
385 The path and filename of the ELF executable file to use as payload.
387 # TODO: Defined if no payload? Breaks build?
388 config COMPRESSED_PAYLOAD_LZMA
389 bool "Use LZMA compression for payloads"
391 depends on PAYLOAD_ELF
393 In order to reduce the size payloads take up in the ROM chip
394 coreboot can compress them using the LZMA algorithm.
396 config COMPRESSED_PAYLOAD_NRV2B
405 bool "Add a VGA BIOS image"
407 Select this option if you have a VGA BIOS image that you would
408 like to add to your ROM.
410 You will be able to specify the location and file name of the
413 config FALLBACK_VGA_BIOS_FILE
414 string "VGA BIOS path and filename"
416 default "vgabios.bin"
418 The path and filename of the file to use as VGA BIOS.
420 config FALLBACK_VGA_BIOS_ID
421 string "VGA device PCI IDs"
425 The comma-separated PCI vendor and device ID that would associate
426 your VGA BIOS to your video card.
430 In the above example 1106 is the PCI vendor ID (in hex, but without
431 the "0x" prefix) and 3230 specifies the PCI device ID of the
432 video card (also in hex, without "0x" prefix).
435 bool "Add an MBI image"
436 depends on NORTHBRIDGE_INTEL_I82830
438 Select this option if you have an Intel MBI image that you would
439 like to add to your ROM.
441 You will be able to specify the location and file name of the
444 config FALLBACK_MBI_FILE
445 string "Intel MBI path and filename"
449 The path and filename of the file to use as VGA BIOS.
454 depends on PCI_OPTION_ROM_RUN_YABEL
457 prompt "Show graphical bootsplash"
459 depends on PCI_OPTION_ROM_RUN_YABEL
461 This option shows a graphical bootsplash screen. The grapics are
462 loaded from the CBFS file bootsplash.jpg.
464 config FALLBACK_BOOTSPLASH_FILE
465 string "Bootsplash path and filename"
466 depends on BOOTSPLASH
467 default "bootsplash.jpg"
469 The path and filename of the file to use as graphical bootsplash
470 screen. The file format has to be jpg.
472 # TODO: Turn this into a "choice".
473 config FRAMEBUFFER_VESA_MODE
474 prompt "VESA framebuffer video mode"
477 depends on BOOTSPLASH
479 This option sets the resolution used for the coreboot framebuffer and
480 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
481 some day make this a "choice".
483 config COREBOOT_KEEP_FRAMEBUFFER
484 prompt "Keep VESA framebuffer"
486 depends on BOOTSPLASH
488 This option keeps the framebuffer mode set after coreboot finishes
489 execution. If this option is enabled, coreboot will pass a
490 framebuffer entry in its coreboot table and the payload will need a
491 framebuffer driver. If this option is disabled, coreboot will switch
492 back to text mode before handing control to a payload.
498 # TODO: Better help text and detailed instructions.
500 bool "GDB debugging support"
503 If enabled, you will be able to set breakpoints for gdb debugging.
504 See src/arch/i386/lib/c_start.S for details.
506 config DEBUG_RAM_SETUP
507 bool "Output verbose RAM init debug messages"
509 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
510 || NORTHBRIDGE_AMD_AMDK8 \
511 || NORTHBRIDGE_VIA_CN700 \
512 || NORTHBRIDGE_VIA_CX700 \
513 || NORTHBRIDGE_VIA_VX800 \
514 || NORTHBRIDGE_INTEL_E7501 \
515 || NORTHBRIDGE_INTEL_I440BX \
516 || NORTHBRIDGE_INTEL_I82810 \
517 || NORTHBRIDGE_INTEL_I82830 \
518 || NORTHBRIDGE_INTEL_I945)
520 This option enables additional RAM init related debug messages.
521 It is recommended to enable this when debugging issues on your
522 board which might be RAM init related.
524 Note: This option will increase the size of the coreboot image.
529 bool "Output verbose SMBus debug messages"
531 depends on (SOUTHBRIDGE_VIA_VT8237R \
532 || NORTHBRIDGE_VIA_VX800 \
533 || NORTHBRIDGE_VIA_CX700 \
534 || NORTHBRIDGE_AMD_AMDK8 \
535 || NORTHBRIDGE_AMD_AMDFAM10 \
536 || SOUTHBRIDGE_VIA_VT8231)
538 This option enables additional SMBus (and SPD) debug messages.
540 Note: This option will increase the size of the coreboot image.
545 bool "Output verbose SMI debug messages"
547 depends on HAVE_SMI_HANDLER
549 This option enables additional SMI related debug messages.
551 Note: This option will increase the size of the coreboot image.
556 bool "Output verbose x86emu debug messages"
558 depends on PCI_OPTION_ROM_RUN_YABEL
560 This option enables additional x86emu related debug messages.
562 Note: This option will increase the size of the coreboot image.
566 config X86EMU_DEBUG_JMP
567 bool "Trace JMP/RETF"
569 depends on X86EMU_DEBUG
571 Print information about JMP and RETF opcodes from x86emu.
573 Note: This option will increase the size of the coreboot image.
577 config X86EMU_DEBUG_TRACE
578 bool "Trace all opcodes"
580 depends on X86EMU_DEBUG
582 Print _all_ opcodes that are executed by x86emu.
584 WARNING: This will produce a LOT of output and take a long time.
586 Note: This option will increase the size of the coreboot image.
590 config X86EMU_DEBUG_PNP
591 bool "Log Plug&Play accesses"
593 depends on X86EMU_DEBUG
595 Print Plug And Play accesses made by option ROMs.
597 Note: This option will increase the size of the coreboot image.
601 config X86EMU_DEBUG_DISK
604 depends on X86EMU_DEBUG
606 Print Disk I/O related messages.
608 Note: This option will increase the size of the coreboot image.
612 config X86EMU_DEBUG_PMM
615 depends on X86EMU_DEBUG
617 Print messages related to POST Memory Manager (PMM).
619 Note: This option will increase the size of the coreboot image.
624 config X86EMU_DEBUG_VBE
625 bool "Debug VESA BIOS Extensions"
627 depends on X86EMU_DEBUG
629 Print messages related to VESA BIOS Extension (VBE) functions.
631 Note: This option will increase the size of the coreboot image.
635 config X86EMU_DEBUG_INT10
636 bool "Redirect INT10 output to console"
638 depends on X86EMU_DEBUG
640 Let INT10 (i.e. character output) calls print messages to debug output.
642 Note: This option will increase the size of the coreboot image.
646 config X86EMU_DEBUG_INTERRUPTS
647 bool "Log intXX calls"
649 depends on X86EMU_DEBUG
651 Print messages related to interrupt handling.
653 Note: This option will increase the size of the coreboot image.
657 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
658 bool "Log special memory accesses"
660 depends on X86EMU_DEBUG
662 Print messages related to accesses to certain areas of the virtual
663 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
665 Note: This option will increase the size of the coreboot image.
669 config X86EMU_DEBUG_MEM
670 bool "Log all memory accesses"
672 depends on X86EMU_DEBUG
674 Print memory accesses made by option ROM.
675 Note: This also includes accesses to fetch instructions.
677 Note: This option will increase the size of the coreboot image.
681 config X86EMU_DEBUG_IO
682 bool "Log IO accesses"
684 depends on X86EMU_DEBUG
686 Print I/O accesses made by option ROM.
688 Note: This option will increase the size of the coreboot image.
693 bool "Built-in low-level shell"
696 If enabled, you will have a low level shell to examine your machine.
697 Put llshell() in your (romstage) code to start the shell.
698 See src/arch/i386/llshell/llshell.inc for details.
702 config LIFT_BSP_APIC_ID
706 # These probably belong somewhere else, but they are needed somewhere.
707 config AP_CODE_IN_CAR
711 config ENABLE_APIC_EXT_ID
715 config WARNINGS_ARE_ERRORS
719 config ID_SECTION_OFFSET
723 source src/Kconfig.deprecated_options