2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
51 source src/mainboard/Kconfig
52 source src/arch/i386/Kconfig
57 source src/cpu/Kconfig
60 menu "HyperTransport setup"
61 depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
64 prompt "HyperTransport frequency"
65 default LIMIT_HT_SPEED_AUTO
67 This option sets the maximum permissible HyperTransport link
70 Use of this option will only limit the autodetected HT frequency.
71 It will not (and cannot) increase the frequency beyond the
74 This is primarily used to work around poorly designed or laid out
75 HT traces on certain motherboards.
77 config LIMIT_HT_SPEED_200
78 bool "Limit HT frequency to 200MHz"
79 config LIMIT_HT_SPEED_400
80 bool "Limit HT frequency to 400MHz"
81 config LIMIT_HT_SPEED_600
82 bool "Limit HT frequency to 600MHz"
83 config LIMIT_HT_SPEED_800
84 bool "Limit HT frequency to 800MHz"
85 config LIMIT_HT_SPEED_1000
86 bool "Limit HT frequency to 1.0GHz"
87 config LIMIT_HT_SPEED_1200
88 bool "Limit HT frequency to 1.2GHz"
89 config LIMIT_HT_SPEED_1400
90 bool "Limit HT frequency to 1.4GHz"
91 config LIMIT_HT_SPEED_1600
92 bool "Limit HT frequency to 1.6GHz"
93 config LIMIT_HT_SPEED_1800
94 bool "Limit HT frequency to 1.8GHz"
95 config LIMIT_HT_SPEED_2000
96 bool "Limit HT frequency to 2.0GHz"
97 config LIMIT_HT_SPEED_2200
98 bool "Limit HT frequency to 2.2GHz"
99 config LIMIT_HT_SPEED_2400
100 bool "Limit HT frequency to 2.4GHz"
101 config LIMIT_HT_SPEED_2600
102 bool "Limit HT frequency to 2.6GHz"
103 config LIMIT_HT_SPEED_AUTO
104 bool "Autodetect HT frequency"
108 prompt "HyperTransport downlink width"
109 default LIMIT_HT_DOWN_WIDTH_16
111 This option sets the maximum permissible HyperTransport
114 Use of this option will only limit the autodetected HT width.
115 It will not (and cannot) increase the width beyond the autodetected
118 This is primarily used to work around poorly designed or laid out HT
119 traces on certain motherboards.
121 config LIMIT_HT_DOWN_WIDTH_8
123 config LIMIT_HT_DOWN_WIDTH_16
128 prompt "HyperTransport uplink width"
129 default LIMIT_HT_UP_WIDTH_16
131 This option sets the maximum permissible HyperTransport
134 Use of this option will only limit the autodetected HT width.
135 It will not (and cannot) increase the width beyond the autodetected
138 This is primarily used to work around poorly designed or laid out HT
139 traces on certain motherboards.
141 config LIMIT_HT_UP_WIDTH_8
143 config LIMIT_HT_UP_WIDTH_16
149 source src/northbridge/Kconfig
150 comment "Southbridge"
151 source src/southbridge/Kconfig
153 source src/superio/Kconfig
155 source src/devices/Kconfig
159 config PCI_BUS_SEGN_BITS
163 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
167 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
183 config LB_CKS_RANGE_START
187 config LB_CKS_RANGE_END
211 config USE_PRINTK_IN_CAR
215 config USE_OPTION_TABLE
223 config MMCONF_SUPPORT_DEFAULT
227 config MMCONF_SUPPORT
238 source src/console/Kconfig
240 config HAVE_ACPI_RESUME
244 config ACPI_SSDTX_NUM
248 config HAVE_FALLBACK_BOOT
252 config USE_FALLBACK_IMAGE
256 config HAVE_FAILOVER_BOOT
260 config USE_FAILOVER_IMAGE
264 config HAVE_HARD_RESET
266 default y if BOARD_HAS_HARD_RESET
269 This variable specifies whether a given board has a hard_reset
270 function, no matter if it's provided by board code or chipset code.
272 config BOARD_HAS_HARD_RESET
276 This variable specifies whether a given board has a reset.c
277 file containing a hard_reset() function.
279 config BOARD_HAS_FADT
283 This variable specifies whether a given board has a board-local
284 FADT in fadt.c. Long-term, those should be moved to appropriate
285 chipset components (eg. southbridge)
287 config HAVE_BUS_CONFIG
291 This variable specifies whether a given board has a get_bus_conf.c
292 file containing bus configuration data.
294 config HAVE_INIT_TIMER
296 default n if UDELAY_IO
299 config HAVE_MAINBOARD_RESOURCES
303 config HAVE_OPTION_TABLE
307 This variable specifies whether a given board has a cmos.layout
308 file containing NVRAM/CMOS bit definitions.
309 It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
315 config HAVE_SMI_HANDLER
319 config PCI_IO_CFG_EXT
327 # TODO: Can probably be removed once all chipsets have kconfig options for it.
332 config USE_WATCHDOG_ON_BOOT
340 Build board-specific VGA code.
346 Enable Unified Memory Architecture for graphics.
353 #TODO Remove this option or make it useful.
354 config HAVE_LOW_TABLES
358 This Option is unused in the code. Since two boards try to set it to
359 'n', they may be broken. We either need to make the option useful or
360 get rid of it. The broken boards are:
364 config HAVE_HIGH_TABLES
368 This variable specifies whether a given northbridge has high table
370 It is set in northbridge/*/Kconfig.
371 Whether or not the high tables are actually written by coreboot is
372 configurable by the user via WRITE_HIGH_TABLES.
374 config HAVE_ACPI_TABLES
377 This variable specifies whether a given board has ACPI table support.
378 It is usually set in mainboard/*/Kconfig.
379 Whether or not the ACPI tables are actually generated by coreboot
380 is configurable by the user via GENERATE_ACPI_TABLES.
385 This variable specifies whether a given board has MP table support.
386 It is usually set in mainboard/*/Kconfig.
387 Whether or not the MP table is actually generated by coreboot
388 is configurable by the user via GENERATE_MP_TABLE.
390 config HAVE_PIRQ_TABLE
393 This variable specifies whether a given board has PIRQ table support.
394 It is usually set in mainboard/*/Kconfig.
395 Whether or not the PIRQ table is actually generated by coreboot
396 is configurable by the user via GENERATE_PIRQ_TABLE.
398 #These Options are here to avoid "undefined" warnings.
399 #The actual selection and help texts are in the following menu.
401 config GENERATE_ACPI_TABLES
403 default HAVE_ACPI_TABLES
405 config GENERATE_MP_TABLE
407 default HAVE_MP_TABLE
409 config GENERATE_PIRQ_TABLE
411 default HAVE_PIRQ_TABLE
413 config WRITE_HIGH_TABLES
415 default HAVE_HIGH_TABLES
419 config WRITE_HIGH_TABLES
420 bool "Write 'high' tables to avoid being overwritten in F segment"
421 depends on HAVE_HIGH_TABLES
425 bool "Generate Multiboot tables (for GRUB2)"
428 config GENERATE_ACPI_TABLES
429 depends on HAVE_ACPI_TABLES
430 bool "Generate ACPI tables"
433 Generate ACPI tables for this board.
437 config GENERATE_MP_TABLE
438 depends on HAVE_MP_TABLE
439 bool "Generate an MP table"
442 Generate an MP table (conforming to the Intel MultiProcessor
443 specification 1.4) for this board.
447 config GENERATE_PIRQ_TABLE
448 depends on HAVE_PIRQ_TABLE
449 bool "Generate a PIRQ table"
452 Generate a PIRQ table for this board.
461 prompt "Add a payload"
467 Select this option if you want to create an "empty" coreboot
468 ROM image for a certain mainboard, i.e. a coreboot ROM image
469 which does not yet contain a payload.
471 For such an image to be useful, you have to use 'cbfstool'
472 to add a payload to the ROM image later.
475 bool "An ELF executable payload"
477 Select this option if you have a payload image (an ELF file)
478 which coreboot should run as soon as the basic hardware
479 initialization is completed.
481 You will be able to specify the location and file name of the
486 config FALLBACK_PAYLOAD_FILE
487 string "Payload path and filename"
488 depends on PAYLOAD_ELF
489 default "payload.elf"
491 The path and filename of the ELF executable file to use as payload.
493 # TODO: Defined if no payload? Breaks build?
494 config COMPRESSED_PAYLOAD_LZMA
495 bool "Use LZMA compression for payloads"
497 depends on PAYLOAD_ELF
499 In order to reduce the size payloads take up in the ROM chip
500 coreboot can compress them using the LZMA algorithm.
502 config COMPRESSED_PAYLOAD_NRV2B
511 bool "Add a VGA BIOS image"
513 Select this option if you have a VGA BIOS image that you would
514 like to add to your ROM.
516 You will be able to specify the location and file name of the
519 config FALLBACK_VGA_BIOS_FILE
520 string "VGA BIOS path and filename"
522 default "vgabios.bin"
524 The path and filename of the file to use as VGA BIOS.
526 config FALLBACK_VGA_BIOS_ID
527 string "VGA device PCI IDs"
531 The comma-separated PCI vendor and device ID that would associate
532 your VGA BIOS to your video card.
536 In the above example 1106 is the PCI vendor ID (in hex, but without
537 the "0x" prefix) and 3230 specifies the PCI device ID of the
538 video card (also in hex, without "0x" prefix).
541 bool "Add an MBI image"
542 depends on NORTHBRIDGE_INTEL_I82830
544 Select this option if you have an Intel MBI image that you would
545 like to add to your ROM.
547 You will be able to specify the location and file name of the
550 config FALLBACK_MBI_FILE
551 string "Intel MBI path and filename"
555 The path and filename of the file to use as VGA BIOS.
560 depends on PCI_OPTION_ROM_RUN_YABEL
563 prompt "Show graphical bootsplash"
565 depends on PCI_OPTION_ROM_RUN_YABEL
567 This option shows a graphical bootsplash screen. The grapics are
568 loaded from the CBFS file bootsplash.jpg.
570 config FALLBACK_BOOTSPLASH_FILE
571 string "Bootsplash path and filename"
572 depends on BOOTSPLASH
573 default "bootsplash.jpg"
575 The path and filename of the file to use as graphical bootsplash
576 screen. The file format has to be jpg.
578 # TODO: Turn this into a "choice".
579 config FRAMEBUFFER_VESA_MODE
580 prompt "VESA framebuffer video mode"
583 depends on BOOTSPLASH
585 This option sets the resolution used for the coreboot framebuffer and
586 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
587 some day make this a "choice".
589 config COREBOOT_KEEP_FRAMEBUFFER
590 prompt "Keep VESA framebuffer"
592 depends on BOOTSPLASH
594 This option keeps the framebuffer mode set after coreboot finishes
595 execution. If this option is enabled, coreboot will pass a
596 framebuffer entry in its coreboot table and the payload will need a
597 framebuffer driver. If this option is disabled, coreboot will switch
598 back to text mode before handing control to a payload.
604 # TODO: Better help text and detailed instructions.
606 bool "GDB debugging support"
609 If enabled, you will be able to set breakpoints for gdb debugging.
610 See src/arch/i386/lib/c_start.S for details.
612 config DEBUG_RAM_SETUP
613 bool "Output verbose RAM init debug messages"
615 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
616 || NORTHBRIDGE_AMD_AMDK8 \
617 || NORTHBRIDGE_VIA_CN700 \
618 || NORTHBRIDGE_VIA_CX700 \
619 || NORTHBRIDGE_VIA_VX800 \
620 || NORTHBRIDGE_INTEL_E7501 \
621 || NORTHBRIDGE_INTEL_I440BX \
622 || NORTHBRIDGE_INTEL_I82810 \
623 || NORTHBRIDGE_INTEL_I82830 \
624 || NORTHBRIDGE_INTEL_I945)
626 This option enables additional RAM init related debug messages.
627 It is recommended to enable this when debugging issues on your
628 board which might be RAM init related.
630 Note: This option will increase the size of the coreboot image.
635 bool "Output verbose SMBus debug messages"
637 depends on (SOUTHBRIDGE_VIA_VT8237R \
638 || NORTHBRIDGE_VIA_VX800 \
639 || NORTHBRIDGE_VIA_CX700 \
640 || NORTHBRIDGE_AMD_AMDK8)
642 This option enables additional SMBus (and SPD) debug messages.
644 Note: This option will increase the size of the coreboot image.
649 bool "Output verbose SMI debug messages"
651 depends on HAVE_SMI_HANDLER
653 This option enables additional SMI related debug messages.
655 Note: This option will increase the size of the coreboot image.
660 bool "Output verbose x86emu debug messages"
662 depends on PCI_OPTION_ROM_RUN_YABEL
664 This option enables additional x86emu related debug messages.
666 Note: This option will increase the size of the coreboot image.
670 config X86EMU_DEBUG_JMP
671 bool "Trace JMP/RETF"
673 depends on X86EMU_DEBUG
675 Print information about JMP and RETF opcodes from x86emu.
677 Note: This option will increase the size of the coreboot image.
681 config X86EMU_DEBUG_TRACE
682 bool "Trace all opcodes"
684 depends on X86EMU_DEBUG
686 Print _all_ opcodes that are executed by x86emu.
688 WARNING: This will produce a LOT of output and take a long time.
690 Note: This option will increase the size of the coreboot image.
694 config X86EMU_DEBUG_PNP
695 bool "Log Plug&Play accesses"
697 depends on X86EMU_DEBUG
699 Print Plug And Play accesses made by option ROMs.
701 Note: This option will increase the size of the coreboot image.
705 config X86EMU_DEBUG_DISK
708 depends on X86EMU_DEBUG
710 Print Disk I/O related messages.
712 Note: This option will increase the size of the coreboot image.
716 config X86EMU_DEBUG_PMM
719 depends on X86EMU_DEBUG
721 Print messages related to POST Memory Manager (PMM).
723 Note: This option will increase the size of the coreboot image.
728 config X86EMU_DEBUG_VBE
729 bool "Debug VESA BIOS Extensions"
731 depends on X86EMU_DEBUG
733 Print messages related to VESA BIOS Extension (VBE) functions.
735 Note: This option will increase the size of the coreboot image.
739 config X86EMU_DEBUG_INT10
740 bool "Redirect INT10 output to console"
742 depends on X86EMU_DEBUG
744 Let INT10 (i.e. character output) calls print messages to debug output.
746 Note: This option will increase the size of the coreboot image.
750 config X86EMU_DEBUG_INTERRUPTS
751 bool "Log intXX calls"
753 depends on X86EMU_DEBUG
755 Print messages related to interrupt handling.
757 Note: This option will increase the size of the coreboot image.
761 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
762 bool "Log special memory accesses"
764 depends on X86EMU_DEBUG
766 Print messages related to accesses to certain areas of the virtual
767 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
769 Note: This option will increase the size of the coreboot image.
773 config X86EMU_DEBUG_MEM
774 bool "Log all memory accesses"
776 depends on X86EMU_DEBUG
778 Print memory accesses made by option ROM.
779 Note: This also includes accesses to fetch instructions.
781 Note: This option will increase the size of the coreboot image.
785 config X86EMU_DEBUG_IO
786 bool "Log IO accesses"
788 depends on X86EMU_DEBUG
790 Print I/O accesses made by option ROM.
792 Note: This option will increase the size of the coreboot image.
797 bool "Built-in low-level shell"
800 If enabled, you will have a low level shell to examine your machine.
801 Put llshell() in your (romstage) code to start the shell.
802 See src/arch/i386/llshell/llshell.inc for details.
806 config LIFT_BSP_APIC_ID
810 # These probably belong somewhere else, but they are needed somewhere.
811 config AP_CODE_IN_CAR
819 config ENABLE_APIC_EXT_ID
823 config WARNINGS_ARE_ERRORS
827 config ID_SECTION_OFFSET