2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
67 Changes the build process to scan-build is used.
68 Requires scan-build in path.
70 config SCANBUILD_REPORT_LOCATION
71 string "Directory to put scan-build report in"
73 depends on SCANBUILD_ENABLE
75 Where the scan-build report should be stored
81 Enables the use of ccache for faster builds.
82 Requires ccache in path.
86 source src/mainboard/Kconfig
87 source src/arch/i386/Kconfig
92 source src/cpu/Kconfig
95 menu "HyperTransport setup"
96 depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
99 prompt "HyperTransport frequency"
100 default LIMIT_HT_SPEED_AUTO
102 This option sets the maximum permissible HyperTransport link
105 Use of this option will only limit the autodetected HT frequency.
106 It will not (and cannot) increase the frequency beyond the
109 This is primarily used to work around poorly designed or laid out
110 HT traces on certain motherboards.
112 config LIMIT_HT_SPEED_200
113 bool "Limit HT frequency to 200MHz"
114 config LIMIT_HT_SPEED_400
115 bool "Limit HT frequency to 400MHz"
116 config LIMIT_HT_SPEED_600
117 bool "Limit HT frequency to 600MHz"
118 config LIMIT_HT_SPEED_800
119 bool "Limit HT frequency to 800MHz"
120 config LIMIT_HT_SPEED_1000
121 bool "Limit HT frequency to 1.0GHz"
122 config LIMIT_HT_SPEED_1200
123 bool "Limit HT frequency to 1.2GHz"
124 config LIMIT_HT_SPEED_1400
125 bool "Limit HT frequency to 1.4GHz"
126 config LIMIT_HT_SPEED_1600
127 bool "Limit HT frequency to 1.6GHz"
128 config LIMIT_HT_SPEED_1800
129 bool "Limit HT frequency to 1.8GHz"
130 config LIMIT_HT_SPEED_2000
131 bool "Limit HT frequency to 2.0GHz"
132 config LIMIT_HT_SPEED_2200
133 bool "Limit HT frequency to 2.2GHz"
134 config LIMIT_HT_SPEED_2400
135 bool "Limit HT frequency to 2.4GHz"
136 config LIMIT_HT_SPEED_2600
137 bool "Limit HT frequency to 2.6GHz"
138 config LIMIT_HT_SPEED_AUTO
139 bool "Autodetect HT frequency"
143 prompt "HyperTransport downlink width"
144 default LIMIT_HT_DOWN_WIDTH_16
146 This option sets the maximum permissible HyperTransport
149 Use of this option will only limit the autodetected HT width.
150 It will not (and cannot) increase the width beyond the autodetected
153 This is primarily used to work around poorly designed or laid out HT
154 traces on certain motherboards.
156 config LIMIT_HT_DOWN_WIDTH_8
158 config LIMIT_HT_DOWN_WIDTH_16
163 prompt "HyperTransport uplink width"
164 default LIMIT_HT_UP_WIDTH_16
166 This option sets the maximum permissible HyperTransport
169 Use of this option will only limit the autodetected HT width.
170 It will not (and cannot) increase the width beyond the autodetected
173 This is primarily used to work around poorly designed or laid out HT
174 traces on certain motherboards.
176 config LIMIT_HT_UP_WIDTH_8
178 config LIMIT_HT_UP_WIDTH_16
184 source src/northbridge/Kconfig
185 comment "Southbridge"
186 source src/southbridge/Kconfig
188 source src/superio/Kconfig
190 source src/devices/Kconfig
194 config PCI_BUS_SEGN_BITS
198 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
202 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
218 config LB_CKS_RANGE_START
222 config LB_CKS_RANGE_END
246 config USE_PRINTK_IN_CAR
250 config USE_OPTION_TABLE
258 config MMCONF_SUPPORT_DEFAULT
262 config MMCONF_SUPPORT
273 source src/console/Kconfig
275 config HAVE_ACPI_RESUME
279 config ACPI_SSDTX_NUM
283 config HAVE_HARD_RESET
285 default y if BOARD_HAS_HARD_RESET
288 This variable specifies whether a given board has a hard_reset
289 function, no matter if it's provided by board code or chipset code.
291 config HAVE_INIT_TIMER
293 default n if UDELAY_IO
296 config HAVE_MAINBOARD_RESOURCES
300 config HAVE_OPTION_TABLE
304 This variable specifies whether a given board has a cmos.layout
305 file containing NVRAM/CMOS bit definitions.
306 It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
312 config HAVE_SMI_HANDLER
316 config PCI_IO_CFG_EXT
324 # TODO: Can probably be removed once all chipsets have kconfig options for it.
329 config USE_WATCHDOG_ON_BOOT
337 Build board-specific VGA code.
343 Enable Unified Memory Architecture for graphics.
350 #TODO Remove this option or make it useful.
351 config HAVE_LOW_TABLES
355 This Option is unused in the code. Since two boards try to set it to
356 'n', they may be broken. We either need to make the option useful or
357 get rid of it. The broken boards are:
361 config HAVE_HIGH_TABLES
365 This variable specifies whether a given northbridge has high table
367 It is set in northbridge/*/Kconfig.
368 Whether or not the high tables are actually written by coreboot is
369 configurable by the user via WRITE_HIGH_TABLES.
371 config HAVE_ACPI_TABLES
374 This variable specifies whether a given board has ACPI table support.
375 It is usually set in mainboard/*/Kconfig.
376 Whether or not the ACPI tables are actually generated by coreboot
377 is configurable by the user via GENERATE_ACPI_TABLES.
382 This variable specifies whether a given board has MP table support.
383 It is usually set in mainboard/*/Kconfig.
384 Whether or not the MP table is actually generated by coreboot
385 is configurable by the user via GENERATE_MP_TABLE.
387 config HAVE_PIRQ_TABLE
390 This variable specifies whether a given board has PIRQ table support.
391 It is usually set in mainboard/*/Kconfig.
392 Whether or not the PIRQ table is actually generated by coreboot
393 is configurable by the user via GENERATE_PIRQ_TABLE.
395 #These Options are here to avoid "undefined" warnings.
396 #The actual selection and help texts are in the following menu.
398 config GENERATE_ACPI_TABLES
400 default HAVE_ACPI_TABLES
402 config GENERATE_MP_TABLE
404 default HAVE_MP_TABLE
406 config GENERATE_PIRQ_TABLE
408 default HAVE_PIRQ_TABLE
410 config WRITE_HIGH_TABLES
412 default HAVE_HIGH_TABLES
416 config WRITE_HIGH_TABLES
417 bool "Write 'high' tables to avoid being overwritten in F segment"
418 depends on HAVE_HIGH_TABLES
422 bool "Generate Multiboot tables (for GRUB2)"
425 config GENERATE_ACPI_TABLES
426 depends on HAVE_ACPI_TABLES
427 bool "Generate ACPI tables"
430 Generate ACPI tables for this board.
434 config GENERATE_MP_TABLE
435 depends on HAVE_MP_TABLE
436 bool "Generate an MP table"
439 Generate an MP table (conforming to the Intel MultiProcessor
440 specification 1.4) for this board.
444 config GENERATE_PIRQ_TABLE
445 depends on HAVE_PIRQ_TABLE
446 bool "Generate a PIRQ table"
449 Generate a PIRQ table for this board.
458 prompt "Add a payload"
464 Select this option if you want to create an "empty" coreboot
465 ROM image for a certain mainboard, i.e. a coreboot ROM image
466 which does not yet contain a payload.
468 For such an image to be useful, you have to use 'cbfstool'
469 to add a payload to the ROM image later.
472 bool "An ELF executable payload"
474 Select this option if you have a payload image (an ELF file)
475 which coreboot should run as soon as the basic hardware
476 initialization is completed.
478 You will be able to specify the location and file name of the
483 config FALLBACK_PAYLOAD_FILE
484 string "Payload path and filename"
485 depends on PAYLOAD_ELF
486 default "payload.elf"
488 The path and filename of the ELF executable file to use as payload.
490 # TODO: Defined if no payload? Breaks build?
491 config COMPRESSED_PAYLOAD_LZMA
492 bool "Use LZMA compression for payloads"
494 depends on PAYLOAD_ELF
496 In order to reduce the size payloads take up in the ROM chip
497 coreboot can compress them using the LZMA algorithm.
499 config COMPRESSED_PAYLOAD_NRV2B
508 bool "Add a VGA BIOS image"
510 Select this option if you have a VGA BIOS image that you would
511 like to add to your ROM.
513 You will be able to specify the location and file name of the
516 config FALLBACK_VGA_BIOS_FILE
517 string "VGA BIOS path and filename"
519 default "vgabios.bin"
521 The path and filename of the file to use as VGA BIOS.
523 config FALLBACK_VGA_BIOS_ID
524 string "VGA device PCI IDs"
528 The comma-separated PCI vendor and device ID that would associate
529 your VGA BIOS to your video card.
533 In the above example 1106 is the PCI vendor ID (in hex, but without
534 the "0x" prefix) and 3230 specifies the PCI device ID of the
535 video card (also in hex, without "0x" prefix).
538 bool "Add an MBI image"
539 depends on NORTHBRIDGE_INTEL_I82830
541 Select this option if you have an Intel MBI image that you would
542 like to add to your ROM.
544 You will be able to specify the location and file name of the
547 config FALLBACK_MBI_FILE
548 string "Intel MBI path and filename"
552 The path and filename of the file to use as VGA BIOS.
557 depends on PCI_OPTION_ROM_RUN_YABEL
560 prompt "Show graphical bootsplash"
562 depends on PCI_OPTION_ROM_RUN_YABEL
564 This option shows a graphical bootsplash screen. The grapics are
565 loaded from the CBFS file bootsplash.jpg.
567 config FALLBACK_BOOTSPLASH_FILE
568 string "Bootsplash path and filename"
569 depends on BOOTSPLASH
570 default "bootsplash.jpg"
572 The path and filename of the file to use as graphical bootsplash
573 screen. The file format has to be jpg.
575 # TODO: Turn this into a "choice".
576 config FRAMEBUFFER_VESA_MODE
577 prompt "VESA framebuffer video mode"
580 depends on BOOTSPLASH
582 This option sets the resolution used for the coreboot framebuffer and
583 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
584 some day make this a "choice".
586 config COREBOOT_KEEP_FRAMEBUFFER
587 prompt "Keep VESA framebuffer"
589 depends on BOOTSPLASH
591 This option keeps the framebuffer mode set after coreboot finishes
592 execution. If this option is enabled, coreboot will pass a
593 framebuffer entry in its coreboot table and the payload will need a
594 framebuffer driver. If this option is disabled, coreboot will switch
595 back to text mode before handing control to a payload.
601 # TODO: Better help text and detailed instructions.
603 bool "GDB debugging support"
606 If enabled, you will be able to set breakpoints for gdb debugging.
607 See src/arch/i386/lib/c_start.S for details.
609 config DEBUG_RAM_SETUP
610 bool "Output verbose RAM init debug messages"
612 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
613 || NORTHBRIDGE_AMD_AMDK8 \
614 || NORTHBRIDGE_VIA_CN700 \
615 || NORTHBRIDGE_VIA_CX700 \
616 || NORTHBRIDGE_VIA_VX800 \
617 || NORTHBRIDGE_INTEL_E7501 \
618 || NORTHBRIDGE_INTEL_I440BX \
619 || NORTHBRIDGE_INTEL_I82810 \
620 || NORTHBRIDGE_INTEL_I82830 \
621 || NORTHBRIDGE_INTEL_I945)
623 This option enables additional RAM init related debug messages.
624 It is recommended to enable this when debugging issues on your
625 board which might be RAM init related.
627 Note: This option will increase the size of the coreboot image.
632 bool "Output verbose SMBus debug messages"
634 depends on (SOUTHBRIDGE_VIA_VT8237R \
635 || NORTHBRIDGE_VIA_VX800 \
636 || NORTHBRIDGE_VIA_CX700 \
637 || NORTHBRIDGE_AMD_AMDK8)
639 This option enables additional SMBus (and SPD) debug messages.
641 Note: This option will increase the size of the coreboot image.
646 bool "Output verbose SMI debug messages"
648 depends on HAVE_SMI_HANDLER
650 This option enables additional SMI related debug messages.
652 Note: This option will increase the size of the coreboot image.
657 bool "Output verbose x86emu debug messages"
659 depends on PCI_OPTION_ROM_RUN_YABEL
661 This option enables additional x86emu related debug messages.
663 Note: This option will increase the size of the coreboot image.
667 config X86EMU_DEBUG_JMP
668 bool "Trace JMP/RETF"
670 depends on X86EMU_DEBUG
672 Print information about JMP and RETF opcodes from x86emu.
674 Note: This option will increase the size of the coreboot image.
678 config X86EMU_DEBUG_TRACE
679 bool "Trace all opcodes"
681 depends on X86EMU_DEBUG
683 Print _all_ opcodes that are executed by x86emu.
685 WARNING: This will produce a LOT of output and take a long time.
687 Note: This option will increase the size of the coreboot image.
691 config X86EMU_DEBUG_PNP
692 bool "Log Plug&Play accesses"
694 depends on X86EMU_DEBUG
696 Print Plug And Play accesses made by option ROMs.
698 Note: This option will increase the size of the coreboot image.
702 config X86EMU_DEBUG_DISK
705 depends on X86EMU_DEBUG
707 Print Disk I/O related messages.
709 Note: This option will increase the size of the coreboot image.
713 config X86EMU_DEBUG_PMM
716 depends on X86EMU_DEBUG
718 Print messages related to POST Memory Manager (PMM).
720 Note: This option will increase the size of the coreboot image.
725 config X86EMU_DEBUG_VBE
726 bool "Debug VESA BIOS Extensions"
728 depends on X86EMU_DEBUG
730 Print messages related to VESA BIOS Extension (VBE) functions.
732 Note: This option will increase the size of the coreboot image.
736 config X86EMU_DEBUG_INT10
737 bool "Redirect INT10 output to console"
739 depends on X86EMU_DEBUG
741 Let INT10 (i.e. character output) calls print messages to debug output.
743 Note: This option will increase the size of the coreboot image.
747 config X86EMU_DEBUG_INTERRUPTS
748 bool "Log intXX calls"
750 depends on X86EMU_DEBUG
752 Print messages related to interrupt handling.
754 Note: This option will increase the size of the coreboot image.
758 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
759 bool "Log special memory accesses"
761 depends on X86EMU_DEBUG
763 Print messages related to accesses to certain areas of the virtual
764 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
766 Note: This option will increase the size of the coreboot image.
770 config X86EMU_DEBUG_MEM
771 bool "Log all memory accesses"
773 depends on X86EMU_DEBUG
775 Print memory accesses made by option ROM.
776 Note: This also includes accesses to fetch instructions.
778 Note: This option will increase the size of the coreboot image.
782 config X86EMU_DEBUG_IO
783 bool "Log IO accesses"
785 depends on X86EMU_DEBUG
787 Print I/O accesses made by option ROM.
789 Note: This option will increase the size of the coreboot image.
794 bool "Built-in low-level shell"
797 If enabled, you will have a low level shell to examine your machine.
798 Put llshell() in your (romstage) code to start the shell.
799 See src/arch/i386/llshell/llshell.inc for details.
803 config LIFT_BSP_APIC_ID
807 # These probably belong somewhere else, but they are needed somewhere.
808 config AP_CODE_IN_CAR
816 config ENABLE_APIC_EXT_ID
820 config WARNINGS_ARE_ERRORS
824 config ID_SECTION_OFFSET
828 source src/Kconfig.deprecated_options