2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
83 config SCONFIG_GENPARSER
84 bool "Generate SCONFIG parser using flex and bison"
88 Enable this option if you are working on the sconfig
89 device tree parser and made changes to sconfig.l and
93 config USE_OPTION_TABLE
94 bool "Use CMOS for configuration values"
96 depends on HAVE_OPTION_TABLE
98 Enable this option if coreboot shall read options from the "CMOS"
99 NVRAM instead of using hard coded values.
103 source src/mainboard/Kconfig
105 # This option is used to set the architecture of a mainboard to X86.
106 # It is usually set in mainboard/*/Kconfig.
112 source src/arch/x86/Kconfig
118 source src/cpu/Kconfig
119 comment "Northbridge"
120 source src/northbridge/Kconfig
121 comment "Southbridge"
122 source src/southbridge/Kconfig
124 source src/superio/Kconfig
126 source src/devices/Kconfig
127 comment "Embedded Controllers"
128 source src/ec/Kconfig
132 menu "Generic Drivers"
133 source src/drivers/Kconfig
136 config PCI_BUS_SEGN_BITS
152 config MMCONF_SUPPORT_DEFAULT
156 config MMCONF_SUPPORT
160 source src/console/Kconfig
162 # This should default to N and be set by SuperI/O drivers that have an UART
163 config HAVE_UART_IO_MAPPED
167 config HAVE_UART_MEMORY_MAPPED
171 config HAVE_ACPI_RESUME
175 config HAVE_ACPI_SLIC
179 config ACPI_SSDTX_NUM
183 config HAVE_HARD_RESET
185 default y if BOARD_HAS_HARD_RESET
188 This variable specifies whether a given board has a hard_reset
189 function, no matter if it's provided by board code or chipset code.
191 config HAVE_INIT_TIMER
193 default n if UDELAY_IO
196 config HAVE_MAINBOARD_RESOURCES
200 config USE_OPTION_TABLE
204 config HAVE_OPTION_TABLE
208 This variable specifies whether a given board has a cmos.layout
209 file containing NVRAM/CMOS bit definitions.
210 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
216 config HAVE_SMI_HANDLER
220 config PCI_IO_CFG_EXT
228 # TODO: Can probably be removed once all chipsets have kconfig options for it.
233 config USE_WATCHDOG_ON_BOOT
241 Build board-specific VGA code.
247 Enable Unified Memory Architecture for graphics.
254 config HAVE_ACPI_TABLES
257 This variable specifies whether a given board has ACPI table support.
258 It is usually set in mainboard/*/Kconfig.
259 Whether or not the ACPI tables are actually generated by coreboot
260 is configurable by the user via GENERATE_ACPI_TABLES.
265 This variable specifies whether a given board has MP table support.
266 It is usually set in mainboard/*/Kconfig.
267 Whether or not the MP table is actually generated by coreboot
268 is configurable by the user via GENERATE_MP_TABLE.
270 config HAVE_PIRQ_TABLE
273 This variable specifies whether a given board has PIRQ table support.
274 It is usually set in mainboard/*/Kconfig.
275 Whether or not the PIRQ table is actually generated by coreboot
276 is configurable by the user via GENERATE_PIRQ_TABLE.
278 #These Options are here to avoid "undefined" warnings.
279 #The actual selection and help texts are in the following menu.
281 config GENERATE_ACPI_TABLES
283 default HAVE_ACPI_TABLES
285 config GENERATE_MP_TABLE
287 default HAVE_MP_TABLE
289 config GENERATE_PIRQ_TABLE
291 default HAVE_PIRQ_TABLE
295 config WRITE_HIGH_TABLES
296 bool "Write 'high' tables to avoid being overwritten in F segment"
300 bool "Generate Multiboot tables (for GRUB2)"
303 config GENERATE_ACPI_TABLES
304 depends on HAVE_ACPI_TABLES
305 bool "Generate ACPI tables"
308 Generate ACPI tables for this board.
312 config GENERATE_MP_TABLE
313 depends on HAVE_MP_TABLE
314 bool "Generate an MP table"
317 Generate an MP table (conforming to the Intel MultiProcessor
318 specification 1.4) for this board.
322 config GENERATE_PIRQ_TABLE
323 depends on HAVE_PIRQ_TABLE
324 bool "Generate a PIRQ table"
327 Generate a PIRQ table for this board.
336 prompt "Add a payload"
337 default PAYLOAD_NONE if !ARCH_X86
338 default PAYLOAD_SEABIOS if ARCH_X86
343 Select this option if you want to create an "empty" coreboot
344 ROM image for a certain mainboard, i.e. a coreboot ROM image
345 which does not yet contain a payload.
347 For such an image to be useful, you have to use 'cbfstool'
348 to add a payload to the ROM image later.
351 bool "An ELF executable payload"
353 Select this option if you have a payload image (an ELF file)
354 which coreboot should run as soon as the basic hardware
355 initialization is completed.
357 You will be able to specify the location and file name of the
360 config PAYLOAD_SEABIOS
364 Select this option if you want to build a coreboot image
365 with a SeaBIOS payload. If you don't know what this is
366 about, just leave it enabled.
368 See http://coreboot.org/Payloads for more information.
373 Select this option if you want to build a coreboot image
374 with a FILO payload. If you don't know what this is
375 about, just leave it enabled.
377 See http://coreboot.org/Payloads for more information.
382 prompt "SeaBIOS version"
383 default SEABIOS_STABLE
384 depends on PAYLOAD_SEABIOS
386 config SEABIOS_STABLE
389 Stable SeaBIOS version
390 config SEABIOS_MASTER
393 Newest SeaBIOS version
397 prompt "FILO version"
399 depends on PAYLOAD_FILO
412 string "Payload path and filename"
413 depends on PAYLOAD_ELF
414 default "payload.elf"
416 The path and filename of the ELF executable file to use as payload.
419 depends on PAYLOAD_SEABIOS
420 default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
423 depends on PAYLOAD_FILO
424 default "payloads/external/FILO/filo/build/filo.elf"
426 # TODO: Defined if no payload? Breaks build?
427 config COMPRESSED_PAYLOAD_LZMA
428 bool "Use LZMA compression for payloads"
430 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO
432 In order to reduce the size payloads take up in the ROM chip
433 coreboot can compress them using the LZMA algorithm.
435 config COMPRESSED_PAYLOAD_NRV2B
444 bool "Add a VGA BIOS image"
446 Select this option if you have a VGA BIOS image that you would
447 like to add to your ROM.
449 You will be able to specify the location and file name of the
453 string "VGA BIOS path and filename"
455 default "vgabios.bin"
457 The path and filename of the file to use as VGA BIOS.
460 string "VGA device PCI IDs"
464 The comma-separated PCI vendor and device ID that would associate
465 your VGA BIOS to your video card.
469 In the above example 1106 is the PCI vendor ID (in hex, but without
470 the "0x" prefix) and 3230 specifies the PCI device ID of the
471 video card (also in hex, without "0x" prefix).
474 bool "Add an MBI image"
475 depends on NORTHBRIDGE_INTEL_I82830
477 Select this option if you have an Intel MBI image that you would
478 like to add to your ROM.
480 You will be able to specify the location and file name of the
484 string "Intel MBI path and filename"
488 The path and filename of the file to use as VGA BIOS.
493 depends on PCI_OPTION_ROM_RUN_YABEL
496 prompt "Show graphical bootsplash"
498 depends on PCI_OPTION_ROM_RUN_YABEL
500 This option shows a graphical bootsplash screen. The grapics are
501 loaded from the CBFS file bootsplash.jpg.
503 config BOOTSPLASH_FILE
504 string "Bootsplash path and filename"
505 depends on BOOTSPLASH
506 default "bootsplash.jpg"
508 The path and filename of the file to use as graphical bootsplash
509 screen. The file format has to be jpg.
511 # TODO: Turn this into a "choice".
512 config FRAMEBUFFER_VESA_MODE
513 prompt "VESA framebuffer video mode"
516 depends on BOOTSPLASH
518 This option sets the resolution used for the coreboot framebuffer and
519 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
520 some day make this a "choice".
522 config COREBOOT_KEEP_FRAMEBUFFER
523 prompt "Keep VESA framebuffer"
525 depends on BOOTSPLASH
527 This option keeps the framebuffer mode set after coreboot finishes
528 execution. If this option is enabled, coreboot will pass a
529 framebuffer entry in its coreboot table and the payload will need a
530 framebuffer driver. If this option is disabled, coreboot will switch
531 back to text mode before handing control to a payload.
537 # TODO: Better help text and detailed instructions.
539 bool "GDB debugging support"
542 If enabled, you will be able to set breakpoints for gdb debugging.
543 See src/arch/x86/lib/c_start.S for details.
545 config HAVE_DEBUG_RAM_SETUP
548 config DEBUG_RAM_SETUP
549 bool "Output verbose RAM init debug messages"
551 depends on HAVE_DEBUG_RAM_SETUP
553 This option enables additional RAM init related debug messages.
554 It is recommended to enable this when debugging issues on your
555 board which might be RAM init related.
557 Note: This option will increase the size of the coreboot image.
561 config HAVE_DEBUG_CAR
566 depends on HAVE_DEBUG_CAR
568 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
569 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
570 # printk(BIOS_DEBUG, ...) calls.
572 bool "Output verbose Cache-as-RAM debug messages"
574 depends on HAVE_DEBUG_CAR
576 This option enables additional CAR related debug messages.
580 bool "Check PIRQ table consistency"
582 depends on GENERATE_PIRQ_TABLE
586 config HAVE_DEBUG_SMBUS
590 bool "Output verbose SMBus debug messages"
592 depends on HAVE_DEBUG_SMBUS
594 This option enables additional SMBus (and SPD) debug messages.
596 Note: This option will increase the size of the coreboot image.
601 bool "Output verbose SMI debug messages"
603 depends on HAVE_SMI_HANDLER
605 This option enables additional SMI related debug messages.
607 Note: This option will increase the size of the coreboot image.
611 config DEBUG_SMM_RELOCATION
612 bool "Debug SMM relocation code"
614 depends on HAVE_SMI_HANDLER
616 This option enables additional SMM handler relocation related
619 Note: This option will increase the size of the coreboot image.
626 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
627 # printk(BIOS_DEBUG, ...) calls.
628 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
630 bool "Output verbose malloc debug messages"
633 This option enables additional malloc related debug messages.
635 Note: This option will increase the size of the coreboot image.
640 config REALMODE_DEBUG
642 depends on PCI_OPTION_ROM_RUN_REALMODE
644 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
645 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
646 # printk(BIOS_DEBUG, ...) calls.
647 config REALMODE_DEBUG
648 bool "Enable debug messages for option ROM execution"
650 depends on PCI_OPTION_ROM_RUN_REALMODE
652 This option enables additional x86emu related debug messages.
654 Note: This option will increase the time to emulate a ROM.
660 bool "Output verbose x86emu debug messages"
662 depends on PCI_OPTION_ROM_RUN_YABEL
664 This option enables additional x86emu related debug messages.
666 Note: This option will increase the size of the coreboot image.
670 config X86EMU_DEBUG_JMP
671 bool "Trace JMP/RETF"
673 depends on X86EMU_DEBUG
675 Print information about JMP and RETF opcodes from x86emu.
677 Note: This option will increase the size of the coreboot image.
681 config X86EMU_DEBUG_TRACE
682 bool "Trace all opcodes"
684 depends on X86EMU_DEBUG
686 Print _all_ opcodes that are executed by x86emu.
688 WARNING: This will produce a LOT of output and take a long time.
690 Note: This option will increase the size of the coreboot image.
694 config X86EMU_DEBUG_PNP
695 bool "Log Plug&Play accesses"
697 depends on X86EMU_DEBUG
699 Print Plug And Play accesses made by option ROMs.
701 Note: This option will increase the size of the coreboot image.
705 config X86EMU_DEBUG_DISK
708 depends on X86EMU_DEBUG
710 Print Disk I/O related messages.
712 Note: This option will increase the size of the coreboot image.
716 config X86EMU_DEBUG_PMM
719 depends on X86EMU_DEBUG
721 Print messages related to POST Memory Manager (PMM).
723 Note: This option will increase the size of the coreboot image.
728 config X86EMU_DEBUG_VBE
729 bool "Debug VESA BIOS Extensions"
731 depends on X86EMU_DEBUG
733 Print messages related to VESA BIOS Extension (VBE) functions.
735 Note: This option will increase the size of the coreboot image.
739 config X86EMU_DEBUG_INT10
740 bool "Redirect INT10 output to console"
742 depends on X86EMU_DEBUG
744 Let INT10 (i.e. character output) calls print messages to debug output.
746 Note: This option will increase the size of the coreboot image.
750 config X86EMU_DEBUG_INTERRUPTS
751 bool "Log intXX calls"
753 depends on X86EMU_DEBUG
755 Print messages related to interrupt handling.
757 Note: This option will increase the size of the coreboot image.
761 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
762 bool "Log special memory accesses"
764 depends on X86EMU_DEBUG
766 Print messages related to accesses to certain areas of the virtual
767 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
769 Note: This option will increase the size of the coreboot image.
773 config X86EMU_DEBUG_MEM
774 bool "Log all memory accesses"
776 depends on X86EMU_DEBUG
778 Print memory accesses made by option ROM.
779 Note: This also includes accesses to fetch instructions.
781 Note: This option will increase the size of the coreboot image.
785 config X86EMU_DEBUG_IO
786 bool "Log IO accesses"
788 depends on X86EMU_DEBUG
790 Print I/O accesses made by option ROM.
792 Note: This option will increase the size of the coreboot image.
797 bool "Built-in low-level shell"
800 If enabled, you will have a low level shell to examine your machine.
801 Put llshell() in your (romstage) code to start the shell.
802 See src/arch/x86/llshell/llshell.inc for details.
806 config LIFT_BSP_APIC_ID
810 # These probably belong somewhere else, but they are needed somewhere.
811 config AP_CODE_IN_CAR
815 config RAMINIT_SYSINFO
819 config ENABLE_APIC_EXT_ID
823 config WARNINGS_ARE_ERRORS
827 config ID_SECTION_OFFSET
831 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
832 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
833 # mutually exclusive. One of these options must be selected in the
834 # mainboard Kconfig if the chipset supports enabling and disabling of
835 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
836 # in mainboard/Kconfig to know if the button should be enabled or not.
838 config POWER_BUTTON_DEFAULT_ENABLE
841 Select when the board has a power button which can optionally be
842 disabled by the user.
844 config POWER_BUTTON_DEFAULT_DISABLE
847 Select when the board has a power button which can optionally be
848 enabled by the user, e.g. when the board ships with a jumper over
849 the power switch contacts.
851 config POWER_BUTTON_FORCE_ENABLE
854 Select when the board requires that the power button is always
857 config POWER_BUTTON_FORCE_DISABLE
860 Select when the board requires that the power button is always
861 disabled, e.g. when it has been hardwired to ground.
863 config POWER_BUTTON_IS_OPTIONAL
865 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
866 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
868 Internal option that controls ENABLE_POWER_BUTTON visibility.
870 source src/Kconfig.deprecated_options