2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
78 source src/mainboard/Kconfig
79 source src/arch/i386/Kconfig
84 source src/cpu/Kconfig
87 menu "HyperTransport setup"
88 depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
91 prompt "HyperTransport frequency"
92 default LIMIT_HT_SPEED_AUTO
94 This option sets the maximum permissible HyperTransport link
97 Use of this option will only limit the autodetected HT frequency.
98 It will not (and cannot) increase the frequency beyond the
101 This is primarily used to work around poorly designed or laid out
102 HT traces on certain motherboards.
104 config LIMIT_HT_SPEED_200
105 bool "Limit HT frequency to 200MHz"
106 config LIMIT_HT_SPEED_400
107 bool "Limit HT frequency to 400MHz"
108 config LIMIT_HT_SPEED_600
109 bool "Limit HT frequency to 600MHz"
110 config LIMIT_HT_SPEED_800
111 bool "Limit HT frequency to 800MHz"
112 config LIMIT_HT_SPEED_1000
113 bool "Limit HT frequency to 1.0GHz"
114 config LIMIT_HT_SPEED_1200
115 bool "Limit HT frequency to 1.2GHz"
116 config LIMIT_HT_SPEED_1400
117 bool "Limit HT frequency to 1.4GHz"
118 config LIMIT_HT_SPEED_1600
119 bool "Limit HT frequency to 1.6GHz"
120 config LIMIT_HT_SPEED_1800
121 bool "Limit HT frequency to 1.8GHz"
122 config LIMIT_HT_SPEED_2000
123 bool "Limit HT frequency to 2.0GHz"
124 config LIMIT_HT_SPEED_2200
125 bool "Limit HT frequency to 2.2GHz"
126 config LIMIT_HT_SPEED_2400
127 bool "Limit HT frequency to 2.4GHz"
128 config LIMIT_HT_SPEED_2600
129 bool "Limit HT frequency to 2.6GHz"
130 config LIMIT_HT_SPEED_AUTO
131 bool "Autodetect HT frequency"
135 prompt "HyperTransport downlink width"
136 default LIMIT_HT_DOWN_WIDTH_16
138 This option sets the maximum permissible HyperTransport
141 Use of this option will only limit the autodetected HT width.
142 It will not (and cannot) increase the width beyond the autodetected
145 This is primarily used to work around poorly designed or laid out HT
146 traces on certain motherboards.
148 config LIMIT_HT_DOWN_WIDTH_8
150 config LIMIT_HT_DOWN_WIDTH_16
155 prompt "HyperTransport uplink width"
156 default LIMIT_HT_UP_WIDTH_16
158 This option sets the maximum permissible HyperTransport
161 Use of this option will only limit the autodetected HT width.
162 It will not (and cannot) increase the width beyond the autodetected
165 This is primarily used to work around poorly designed or laid out HT
166 traces on certain motherboards.
168 config LIMIT_HT_UP_WIDTH_8
170 config LIMIT_HT_UP_WIDTH_16
176 source src/northbridge/Kconfig
177 comment "Southbridge"
178 source src/southbridge/Kconfig
180 source src/superio/Kconfig
182 source src/devices/Kconfig
186 config PCI_BUS_SEGN_BITS
190 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
194 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
210 config LB_CKS_RANGE_START
214 config LB_CKS_RANGE_END
238 config USE_PRINTK_IN_CAR
242 config USE_OPTION_TABLE
250 config MMCONF_SUPPORT_DEFAULT
254 config MMCONF_SUPPORT
265 source src/console/Kconfig
267 config HAVE_ACPI_RESUME
271 config ACPI_SSDTX_NUM
275 config HAVE_FALLBACK_BOOT
279 config USE_FALLBACK_IMAGE
283 config HAVE_FAILOVER_BOOT
287 config USE_FAILOVER_IMAGE
291 config HAVE_HARD_RESET
293 default y if BOARD_HAS_HARD_RESET
296 This variable specifies whether a given board has a hard_reset
297 function, no matter if it's provided by board code or chipset code.
299 config HAVE_INIT_TIMER
301 default n if UDELAY_IO
304 config HAVE_MAINBOARD_RESOURCES
308 config HAVE_OPTION_TABLE
312 This variable specifies whether a given board has a cmos.layout
313 file containing NVRAM/CMOS bit definitions.
314 It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
320 config HAVE_SMI_HANDLER
324 config PCI_IO_CFG_EXT
332 # TODO: Can probably be removed once all chipsets have kconfig options for it.
337 config USE_WATCHDOG_ON_BOOT
345 Build board-specific VGA code.
351 Enable Unified Memory Architecture for graphics.
358 #TODO Remove this option or make it useful.
359 config HAVE_LOW_TABLES
363 This Option is unused in the code. Since two boards try to set it to
364 'n', they may be broken. We either need to make the option useful or
365 get rid of it. The broken boards are:
369 config HAVE_HIGH_TABLES
373 This variable specifies whether a given northbridge has high table
375 It is set in northbridge/*/Kconfig.
376 Whether or not the high tables are actually written by coreboot is
377 configurable by the user via WRITE_HIGH_TABLES.
379 config HAVE_ACPI_TABLES
382 This variable specifies whether a given board has ACPI table support.
383 It is usually set in mainboard/*/Kconfig.
384 Whether or not the ACPI tables are actually generated by coreboot
385 is configurable by the user via GENERATE_ACPI_TABLES.
390 This variable specifies whether a given board has MP table support.
391 It is usually set in mainboard/*/Kconfig.
392 Whether or not the MP table is actually generated by coreboot
393 is configurable by the user via GENERATE_MP_TABLE.
395 config HAVE_PIRQ_TABLE
398 This variable specifies whether a given board has PIRQ table support.
399 It is usually set in mainboard/*/Kconfig.
400 Whether or not the PIRQ table is actually generated by coreboot
401 is configurable by the user via GENERATE_PIRQ_TABLE.
403 #These Options are here to avoid "undefined" warnings.
404 #The actual selection and help texts are in the following menu.
406 config GENERATE_ACPI_TABLES
408 default HAVE_ACPI_TABLES
410 config GENERATE_MP_TABLE
412 default HAVE_MP_TABLE
414 config GENERATE_PIRQ_TABLE
416 default HAVE_PIRQ_TABLE
418 config WRITE_HIGH_TABLES
420 default HAVE_HIGH_TABLES
424 config WRITE_HIGH_TABLES
425 bool "Write 'high' tables to avoid being overwritten in F segment"
426 depends on HAVE_HIGH_TABLES
430 bool "Generate Multiboot tables (for GRUB2)"
433 config GENERATE_ACPI_TABLES
434 depends on HAVE_ACPI_TABLES
435 bool "Generate ACPI tables"
438 Generate ACPI tables for this board.
442 config GENERATE_MP_TABLE
443 depends on HAVE_MP_TABLE
444 bool "Generate an MP table"
447 Generate an MP table (conforming to the Intel MultiProcessor
448 specification 1.4) for this board.
452 config GENERATE_PIRQ_TABLE
453 depends on HAVE_PIRQ_TABLE
454 bool "Generate a PIRQ table"
457 Generate a PIRQ table for this board.
466 prompt "Add a payload"
472 Select this option if you want to create an "empty" coreboot
473 ROM image for a certain mainboard, i.e. a coreboot ROM image
474 which does not yet contain a payload.
476 For such an image to be useful, you have to use 'cbfstool'
477 to add a payload to the ROM image later.
480 bool "An ELF executable payload"
482 Select this option if you have a payload image (an ELF file)
483 which coreboot should run as soon as the basic hardware
484 initialization is completed.
486 You will be able to specify the location and file name of the
491 config FALLBACK_PAYLOAD_FILE
492 string "Payload path and filename"
493 depends on PAYLOAD_ELF
494 default "payload.elf"
496 The path and filename of the ELF executable file to use as payload.
498 # TODO: Defined if no payload? Breaks build?
499 config COMPRESSED_PAYLOAD_LZMA
500 bool "Use LZMA compression for payloads"
502 depends on PAYLOAD_ELF
504 In order to reduce the size payloads take up in the ROM chip
505 coreboot can compress them using the LZMA algorithm.
507 config COMPRESSED_PAYLOAD_NRV2B
516 bool "Add a VGA BIOS image"
518 Select this option if you have a VGA BIOS image that you would
519 like to add to your ROM.
521 You will be able to specify the location and file name of the
524 config FALLBACK_VGA_BIOS_FILE
525 string "VGA BIOS path and filename"
527 default "vgabios.bin"
529 The path and filename of the file to use as VGA BIOS.
531 config FALLBACK_VGA_BIOS_ID
532 string "VGA device PCI IDs"
536 The comma-separated PCI vendor and device ID that would associate
537 your VGA BIOS to your video card.
541 In the above example 1106 is the PCI vendor ID (in hex, but without
542 the "0x" prefix) and 3230 specifies the PCI device ID of the
543 video card (also in hex, without "0x" prefix).
546 bool "Add an MBI image"
547 depends on NORTHBRIDGE_INTEL_I82830
549 Select this option if you have an Intel MBI image that you would
550 like to add to your ROM.
552 You will be able to specify the location and file name of the
555 config FALLBACK_MBI_FILE
556 string "Intel MBI path and filename"
560 The path and filename of the file to use as VGA BIOS.
565 depends on PCI_OPTION_ROM_RUN_YABEL
568 prompt "Show graphical bootsplash"
570 depends on PCI_OPTION_ROM_RUN_YABEL
572 This option shows a graphical bootsplash screen. The grapics are
573 loaded from the CBFS file bootsplash.jpg.
575 config FALLBACK_BOOTSPLASH_FILE
576 string "Bootsplash path and filename"
577 depends on BOOTSPLASH
578 default "bootsplash.jpg"
580 The path and filename of the file to use as graphical bootsplash
581 screen. The file format has to be jpg.
583 # TODO: Turn this into a "choice".
584 config FRAMEBUFFER_VESA_MODE
585 prompt "VESA framebuffer video mode"
588 depends on BOOTSPLASH
590 This option sets the resolution used for the coreboot framebuffer and
591 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
592 some day make this a "choice".
594 config COREBOOT_KEEP_FRAMEBUFFER
595 prompt "Keep VESA framebuffer"
597 depends on BOOTSPLASH
599 This option keeps the framebuffer mode set after coreboot finishes
600 execution. If this option is enabled, coreboot will pass a
601 framebuffer entry in its coreboot table and the payload will need a
602 framebuffer driver. If this option is disabled, coreboot will switch
603 back to text mode before handing control to a payload.
609 # TODO: Better help text and detailed instructions.
611 bool "GDB debugging support"
614 If enabled, you will be able to set breakpoints for gdb debugging.
615 See src/arch/i386/lib/c_start.S for details.
617 config DEBUG_RAM_SETUP
618 bool "Output verbose RAM init debug messages"
620 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
621 || NORTHBRIDGE_AMD_AMDK8 \
622 || NORTHBRIDGE_VIA_CN700 \
623 || NORTHBRIDGE_VIA_CX700 \
624 || NORTHBRIDGE_VIA_VX800 \
625 || NORTHBRIDGE_INTEL_E7501 \
626 || NORTHBRIDGE_INTEL_I440BX \
627 || NORTHBRIDGE_INTEL_I82810 \
628 || NORTHBRIDGE_INTEL_I82830 \
629 || NORTHBRIDGE_INTEL_I945)
631 This option enables additional RAM init related debug messages.
632 It is recommended to enable this when debugging issues on your
633 board which might be RAM init related.
635 Note: This option will increase the size of the coreboot image.
640 bool "Output verbose SMBus debug messages"
642 depends on (SOUTHBRIDGE_VIA_VT8237R \
643 || NORTHBRIDGE_VIA_VX800 \
644 || NORTHBRIDGE_VIA_CX700 \
645 || NORTHBRIDGE_AMD_AMDK8)
647 This option enables additional SMBus (and SPD) debug messages.
649 Note: This option will increase the size of the coreboot image.
654 bool "Output verbose SMI debug messages"
656 depends on HAVE_SMI_HANDLER
658 This option enables additional SMI related debug messages.
660 Note: This option will increase the size of the coreboot image.
665 bool "Output verbose x86emu debug messages"
667 depends on PCI_OPTION_ROM_RUN_YABEL
669 This option enables additional x86emu related debug messages.
671 Note: This option will increase the size of the coreboot image.
675 config X86EMU_DEBUG_JMP
676 bool "Trace JMP/RETF"
678 depends on X86EMU_DEBUG
680 Print information about JMP and RETF opcodes from x86emu.
682 Note: This option will increase the size of the coreboot image.
686 config X86EMU_DEBUG_TRACE
687 bool "Trace all opcodes"
689 depends on X86EMU_DEBUG
691 Print _all_ opcodes that are executed by x86emu.
693 WARNING: This will produce a LOT of output and take a long time.
695 Note: This option will increase the size of the coreboot image.
699 config X86EMU_DEBUG_PNP
700 bool "Log Plug&Play accesses"
702 depends on X86EMU_DEBUG
704 Print Plug And Play accesses made by option ROMs.
706 Note: This option will increase the size of the coreboot image.
710 config X86EMU_DEBUG_DISK
713 depends on X86EMU_DEBUG
715 Print Disk I/O related messages.
717 Note: This option will increase the size of the coreboot image.
721 config X86EMU_DEBUG_PMM
724 depends on X86EMU_DEBUG
726 Print messages related to POST Memory Manager (PMM).
728 Note: This option will increase the size of the coreboot image.
733 config X86EMU_DEBUG_VBE
734 bool "Debug VESA BIOS Extensions"
736 depends on X86EMU_DEBUG
738 Print messages related to VESA BIOS Extension (VBE) functions.
740 Note: This option will increase the size of the coreboot image.
744 config X86EMU_DEBUG_INT10
745 bool "Redirect INT10 output to console"
747 depends on X86EMU_DEBUG
749 Let INT10 (i.e. character output) calls print messages to debug output.
751 Note: This option will increase the size of the coreboot image.
755 config X86EMU_DEBUG_INTERRUPTS
756 bool "Log intXX calls"
758 depends on X86EMU_DEBUG
760 Print messages related to interrupt handling.
762 Note: This option will increase the size of the coreboot image.
766 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
767 bool "Log special memory accesses"
769 depends on X86EMU_DEBUG
771 Print messages related to accesses to certain areas of the virtual
772 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
774 Note: This option will increase the size of the coreboot image.
778 config X86EMU_DEBUG_MEM
779 bool "Log all memory accesses"
781 depends on X86EMU_DEBUG
783 Print memory accesses made by option ROM.
784 Note: This also includes accesses to fetch instructions.
786 Note: This option will increase the size of the coreboot image.
790 config X86EMU_DEBUG_IO
791 bool "Log IO accesses"
793 depends on X86EMU_DEBUG
795 Print I/O accesses made by option ROM.
797 Note: This option will increase the size of the coreboot image.
802 bool "Built-in low-level shell"
805 If enabled, you will have a low level shell to examine your machine.
806 Put llshell() in your (romstage) code to start the shell.
807 See src/arch/i386/llshell/llshell.inc for details.
811 config LIFT_BSP_APIC_ID
815 # These probably belong somewhere else, but they are needed somewhere.
816 config AP_CODE_IN_CAR
824 config ENABLE_APIC_EXT_ID
828 config WARNINGS_ARE_ERRORS
832 config ID_SECTION_OFFSET
836 source src/Kconfig.deprecated_options