2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
83 config SCONFIG_GENPARSER
84 bool "Generate SCONFIG parser using flex and bison"
88 Enable this option if you are working on the sconfig
89 device tree parser and made changes to sconfig.l and
93 config USE_OPTION_TABLE
94 bool "Use CMOS for configuration values"
96 depends on HAVE_OPTION_TABLE
98 Enable this option if coreboot shall read options from the "CMOS"
99 NVRAM instead of using hard coded values.
103 source src/mainboard/Kconfig
104 source src/arch/i386/Kconfig
109 source src/cpu/Kconfig
110 comment "Northbridge"
111 source src/northbridge/Kconfig
112 comment "Southbridge"
113 source src/southbridge/Kconfig
115 source src/superio/Kconfig
117 source src/devices/Kconfig
121 menu "Generic Drivers"
122 source src/drivers/Kconfig
125 config PCI_BUS_SEGN_BITS
129 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
133 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
157 config MMCONF_SUPPORT_DEFAULT
161 config MMCONF_SUPPORT
168 source src/console/Kconfig
170 config HAVE_ACPI_RESUME
174 config HAVE_ACPI_SLIC
178 config ACPI_SSDTX_NUM
182 config HAVE_HARD_RESET
184 default y if BOARD_HAS_HARD_RESET
187 This variable specifies whether a given board has a hard_reset
188 function, no matter if it's provided by board code or chipset code.
190 config HAVE_INIT_TIMER
192 default n if UDELAY_IO
195 config HAVE_MAINBOARD_RESOURCES
199 config USE_OPTION_TABLE
203 config HAVE_OPTION_TABLE
207 This variable specifies whether a given board has a cmos.layout
208 file containing NVRAM/CMOS bit definitions.
209 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
215 config HAVE_SMI_HANDLER
219 config PCI_IO_CFG_EXT
227 # TODO: Can probably be removed once all chipsets have kconfig options for it.
232 config USE_WATCHDOG_ON_BOOT
240 Build board-specific VGA code.
246 Enable Unified Memory Architecture for graphics.
253 #TODO Remove this option or make it useful.
254 config HAVE_LOW_TABLES
258 This Option is unused in the code. Since two boards try to set it to
259 'n', they may be broken. We either need to make the option useful or
260 get rid of it. The broken boards are:
264 config HAVE_HIGH_TABLES
268 This variable specifies whether a given northbridge has high table
270 It is set in northbridge/*/Kconfig.
271 Whether or not the high tables are actually written by coreboot is
272 configurable by the user via WRITE_HIGH_TABLES.
274 config HAVE_ACPI_TABLES
277 This variable specifies whether a given board has ACPI table support.
278 It is usually set in mainboard/*/Kconfig.
279 Whether or not the ACPI tables are actually generated by coreboot
280 is configurable by the user via GENERATE_ACPI_TABLES.
285 This variable specifies whether a given board has MP table support.
286 It is usually set in mainboard/*/Kconfig.
287 Whether or not the MP table is actually generated by coreboot
288 is configurable by the user via GENERATE_MP_TABLE.
290 config HAVE_PIRQ_TABLE
293 This variable specifies whether a given board has PIRQ table support.
294 It is usually set in mainboard/*/Kconfig.
295 Whether or not the PIRQ table is actually generated by coreboot
296 is configurable by the user via GENERATE_PIRQ_TABLE.
298 #These Options are here to avoid "undefined" warnings.
299 #The actual selection and help texts are in the following menu.
301 config GENERATE_ACPI_TABLES
303 default HAVE_ACPI_TABLES
305 config GENERATE_MP_TABLE
307 default HAVE_MP_TABLE
309 config GENERATE_PIRQ_TABLE
311 default HAVE_PIRQ_TABLE
313 config WRITE_HIGH_TABLES
315 default HAVE_HIGH_TABLES
319 config WRITE_HIGH_TABLES
320 bool "Write 'high' tables to avoid being overwritten in F segment"
321 depends on HAVE_HIGH_TABLES
325 bool "Generate Multiboot tables (for GRUB2)"
328 config GENERATE_ACPI_TABLES
329 depends on HAVE_ACPI_TABLES
330 bool "Generate ACPI tables"
333 Generate ACPI tables for this board.
337 config GENERATE_MP_TABLE
338 depends on HAVE_MP_TABLE
339 bool "Generate an MP table"
342 Generate an MP table (conforming to the Intel MultiProcessor
343 specification 1.4) for this board.
347 config GENERATE_PIRQ_TABLE
348 depends on HAVE_PIRQ_TABLE
349 bool "Generate a PIRQ table"
352 Generate a PIRQ table for this board.
361 prompt "Add a payload"
367 Select this option if you want to create an "empty" coreboot
368 ROM image for a certain mainboard, i.e. a coreboot ROM image
369 which does not yet contain a payload.
371 For such an image to be useful, you have to use 'cbfstool'
372 to add a payload to the ROM image later.
375 bool "An ELF executable payload"
377 Select this option if you have a payload image (an ELF file)
378 which coreboot should run as soon as the basic hardware
379 initialization is completed.
381 You will be able to specify the location and file name of the
386 config FALLBACK_PAYLOAD_FILE
387 string "Payload path and filename"
388 depends on PAYLOAD_ELF
389 default "payload.elf"
391 The path and filename of the ELF executable file to use as payload.
393 # TODO: Defined if no payload? Breaks build?
394 config COMPRESSED_PAYLOAD_LZMA
395 bool "Use LZMA compression for payloads"
397 depends on PAYLOAD_ELF
399 In order to reduce the size payloads take up in the ROM chip
400 coreboot can compress them using the LZMA algorithm.
402 config COMPRESSED_PAYLOAD_NRV2B
411 bool "Add a VGA BIOS image"
413 Select this option if you have a VGA BIOS image that you would
414 like to add to your ROM.
416 You will be able to specify the location and file name of the
419 config FALLBACK_VGA_BIOS_FILE
420 string "VGA BIOS path and filename"
422 default "vgabios.bin"
424 The path and filename of the file to use as VGA BIOS.
426 config FALLBACK_VGA_BIOS_ID
427 string "VGA device PCI IDs"
431 The comma-separated PCI vendor and device ID that would associate
432 your VGA BIOS to your video card.
436 In the above example 1106 is the PCI vendor ID (in hex, but without
437 the "0x" prefix) and 3230 specifies the PCI device ID of the
438 video card (also in hex, without "0x" prefix).
441 bool "Add an MBI image"
442 depends on NORTHBRIDGE_INTEL_I82830
444 Select this option if you have an Intel MBI image that you would
445 like to add to your ROM.
447 You will be able to specify the location and file name of the
450 config FALLBACK_MBI_FILE
451 string "Intel MBI path and filename"
455 The path and filename of the file to use as VGA BIOS.
460 depends on PCI_OPTION_ROM_RUN_YABEL
463 prompt "Show graphical bootsplash"
465 depends on PCI_OPTION_ROM_RUN_YABEL
467 This option shows a graphical bootsplash screen. The grapics are
468 loaded from the CBFS file bootsplash.jpg.
470 config FALLBACK_BOOTSPLASH_FILE
471 string "Bootsplash path and filename"
472 depends on BOOTSPLASH
473 default "bootsplash.jpg"
475 The path and filename of the file to use as graphical bootsplash
476 screen. The file format has to be jpg.
478 # TODO: Turn this into a "choice".
479 config FRAMEBUFFER_VESA_MODE
480 prompt "VESA framebuffer video mode"
483 depends on BOOTSPLASH
485 This option sets the resolution used for the coreboot framebuffer and
486 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
487 some day make this a "choice".
489 config COREBOOT_KEEP_FRAMEBUFFER
490 prompt "Keep VESA framebuffer"
492 depends on BOOTSPLASH
494 This option keeps the framebuffer mode set after coreboot finishes
495 execution. If this option is enabled, coreboot will pass a
496 framebuffer entry in its coreboot table and the payload will need a
497 framebuffer driver. If this option is disabled, coreboot will switch
498 back to text mode before handing control to a payload.
504 # TODO: Better help text and detailed instructions.
506 bool "GDB debugging support"
509 If enabled, you will be able to set breakpoints for gdb debugging.
510 See src/arch/i386/lib/c_start.S for details.
512 config HAVE_DEBUG_RAM_SETUP
515 config DEBUG_RAM_SETUP
516 bool "Output verbose RAM init debug messages"
518 depends on HAVE_DEBUG_RAM_SETUP
520 This option enables additional RAM init related debug messages.
521 It is recommended to enable this when debugging issues on your
522 board which might be RAM init related.
524 Note: This option will increase the size of the coreboot image.
529 bool "Check PIRQ table consistency"
531 depends on GENERATE_PIRQ_TABLE
535 config HAVE_DEBUG_SMBUS
539 bool "Output verbose SMBus debug messages"
541 depends on HAVE_DEBUG_SMBUS
543 This option enables additional SMBus (and SPD) debug messages.
545 Note: This option will increase the size of the coreboot image.
550 bool "Output verbose SMI debug messages"
552 depends on HAVE_SMI_HANDLER
554 This option enables additional SMI related debug messages.
556 Note: This option will increase the size of the coreboot image.
560 config DEBUG_SMM_RELOCATION
561 bool "Debug SMM relocation code"
563 depends on HAVE_SMI_HANDLER
565 This option enables additional SMM handler relocation related
568 Note: This option will increase the size of the coreboot image.
573 bool "Output verbose x86emu debug messages"
575 depends on PCI_OPTION_ROM_RUN_YABEL
577 This option enables additional x86emu related debug messages.
579 Note: This option will increase the size of the coreboot image.
583 config X86EMU_DEBUG_JMP
584 bool "Trace JMP/RETF"
586 depends on X86EMU_DEBUG
588 Print information about JMP and RETF opcodes from x86emu.
590 Note: This option will increase the size of the coreboot image.
594 config X86EMU_DEBUG_TRACE
595 bool "Trace all opcodes"
597 depends on X86EMU_DEBUG
599 Print _all_ opcodes that are executed by x86emu.
601 WARNING: This will produce a LOT of output and take a long time.
603 Note: This option will increase the size of the coreboot image.
607 config X86EMU_DEBUG_PNP
608 bool "Log Plug&Play accesses"
610 depends on X86EMU_DEBUG
612 Print Plug And Play accesses made by option ROMs.
614 Note: This option will increase the size of the coreboot image.
618 config X86EMU_DEBUG_DISK
621 depends on X86EMU_DEBUG
623 Print Disk I/O related messages.
625 Note: This option will increase the size of the coreboot image.
629 config X86EMU_DEBUG_PMM
632 depends on X86EMU_DEBUG
634 Print messages related to POST Memory Manager (PMM).
636 Note: This option will increase the size of the coreboot image.
641 config X86EMU_DEBUG_VBE
642 bool "Debug VESA BIOS Extensions"
644 depends on X86EMU_DEBUG
646 Print messages related to VESA BIOS Extension (VBE) functions.
648 Note: This option will increase the size of the coreboot image.
652 config X86EMU_DEBUG_INT10
653 bool "Redirect INT10 output to console"
655 depends on X86EMU_DEBUG
657 Let INT10 (i.e. character output) calls print messages to debug output.
659 Note: This option will increase the size of the coreboot image.
663 config X86EMU_DEBUG_INTERRUPTS
664 bool "Log intXX calls"
666 depends on X86EMU_DEBUG
668 Print messages related to interrupt handling.
670 Note: This option will increase the size of the coreboot image.
674 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
675 bool "Log special memory accesses"
677 depends on X86EMU_DEBUG
679 Print messages related to accesses to certain areas of the virtual
680 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
682 Note: This option will increase the size of the coreboot image.
686 config X86EMU_DEBUG_MEM
687 bool "Log all memory accesses"
689 depends on X86EMU_DEBUG
691 Print memory accesses made by option ROM.
692 Note: This also includes accesses to fetch instructions.
694 Note: This option will increase the size of the coreboot image.
698 config X86EMU_DEBUG_IO
699 bool "Log IO accesses"
701 depends on X86EMU_DEBUG
703 Print I/O accesses made by option ROM.
705 Note: This option will increase the size of the coreboot image.
710 bool "Built-in low-level shell"
713 If enabled, you will have a low level shell to examine your machine.
714 Put llshell() in your (romstage) code to start the shell.
715 See src/arch/i386/llshell/llshell.inc for details.
719 config LIFT_BSP_APIC_ID
723 # These probably belong somewhere else, but they are needed somewhere.
724 config AP_CODE_IN_CAR
728 config ENABLE_APIC_EXT_ID
732 config WARNINGS_ARE_ERRORS
736 config ID_SECTION_OFFSET
740 source src/Kconfig.deprecated_options