2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
49 config SCANBUILD_ENABLE
50 bool "build with scan-build for static analysis"
53 Changes the build process to scan-build is used.
54 Requires scan-build in path.
56 config SCANBUILD_REPORT_LOCATION
57 string "directory to put scan-build report in"
59 depends on SCANBUILD_ENABLE
61 Where the scan-build report should be stored
65 source src/mainboard/Kconfig
66 source src/arch/i386/Kconfig
71 source src/cpu/Kconfig
74 menu "HyperTransport setup"
75 depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
78 prompt "HyperTransport frequency"
79 default LIMIT_HT_SPEED_AUTO
81 This option sets the maximum permissible HyperTransport link
84 Use of this option will only limit the autodetected HT frequency.
85 It will not (and cannot) increase the frequency beyond the
88 This is primarily used to work around poorly designed or laid out
89 HT traces on certain motherboards.
91 config LIMIT_HT_SPEED_200
92 bool "Limit HT frequency to 200MHz"
93 config LIMIT_HT_SPEED_400
94 bool "Limit HT frequency to 400MHz"
95 config LIMIT_HT_SPEED_600
96 bool "Limit HT frequency to 600MHz"
97 config LIMIT_HT_SPEED_800
98 bool "Limit HT frequency to 800MHz"
99 config LIMIT_HT_SPEED_1000
100 bool "Limit HT frequency to 1.0GHz"
101 config LIMIT_HT_SPEED_1200
102 bool "Limit HT frequency to 1.2GHz"
103 config LIMIT_HT_SPEED_1400
104 bool "Limit HT frequency to 1.4GHz"
105 config LIMIT_HT_SPEED_1600
106 bool "Limit HT frequency to 1.6GHz"
107 config LIMIT_HT_SPEED_1800
108 bool "Limit HT frequency to 1.8GHz"
109 config LIMIT_HT_SPEED_2000
110 bool "Limit HT frequency to 2.0GHz"
111 config LIMIT_HT_SPEED_2200
112 bool "Limit HT frequency to 2.2GHz"
113 config LIMIT_HT_SPEED_2400
114 bool "Limit HT frequency to 2.4GHz"
115 config LIMIT_HT_SPEED_2600
116 bool "Limit HT frequency to 2.6GHz"
117 config LIMIT_HT_SPEED_AUTO
118 bool "Autodetect HT frequency"
122 prompt "HyperTransport downlink width"
123 default LIMIT_HT_DOWN_WIDTH_16
125 This option sets the maximum permissible HyperTransport
128 Use of this option will only limit the autodetected HT width.
129 It will not (and cannot) increase the width beyond the autodetected
132 This is primarily used to work around poorly designed or laid out HT
133 traces on certain motherboards.
135 config LIMIT_HT_DOWN_WIDTH_8
137 config LIMIT_HT_DOWN_WIDTH_16
142 prompt "HyperTransport uplink width"
143 default LIMIT_HT_UP_WIDTH_16
145 This option sets the maximum permissible HyperTransport
148 Use of this option will only limit the autodetected HT width.
149 It will not (and cannot) increase the width beyond the autodetected
152 This is primarily used to work around poorly designed or laid out HT
153 traces on certain motherboards.
155 config LIMIT_HT_UP_WIDTH_8
157 config LIMIT_HT_UP_WIDTH_16
163 source src/northbridge/Kconfig
164 comment "Southbridge"
165 source src/southbridge/Kconfig
167 source src/superio/Kconfig
169 source src/devices/Kconfig
173 config PCI_BUS_SEGN_BITS
177 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
181 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
197 config LB_CKS_RANGE_START
201 config LB_CKS_RANGE_END
225 config USE_PRINTK_IN_CAR
229 config USE_OPTION_TABLE
237 config MMCONF_SUPPORT_DEFAULT
241 config MMCONF_SUPPORT
252 source src/console/Kconfig
254 config HAVE_ACPI_RESUME
258 config ACPI_SSDTX_NUM
262 config HAVE_FALLBACK_BOOT
266 config USE_FALLBACK_IMAGE
270 config HAVE_FAILOVER_BOOT
274 config USE_FAILOVER_IMAGE
278 config HAVE_HARD_RESET
280 default y if BOARD_HAS_HARD_RESET
283 This variable specifies whether a given board has a hard_reset
284 function, no matter if it's provided by board code or chipset code.
286 config BOARD_HAS_HARD_RESET
290 This variable specifies whether a given board has a reset.c
291 file containing a hard_reset() function.
293 config BOARD_HAS_FADT
297 This variable specifies whether a given board has a board-local
298 FADT in fadt.c. Long-term, those should be moved to appropriate
299 chipset components (eg. southbridge)
301 config HAVE_BUS_CONFIG
305 This variable specifies whether a given board has a get_bus_conf.c
306 file containing bus configuration data.
308 config HAVE_INIT_TIMER
310 default n if UDELAY_IO
313 config HAVE_MAINBOARD_RESOURCES
317 config HAVE_OPTION_TABLE
321 This variable specifies whether a given board has a cmos.layout
322 file containing NVRAM/CMOS bit definitions.
323 It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
329 config HAVE_SMI_HANDLER
333 config PCI_IO_CFG_EXT
341 # TODO: Can probably be removed once all chipsets have kconfig options for it.
346 config USE_WATCHDOG_ON_BOOT
354 Build board-specific VGA code.
360 Enable Unified Memory Architecture for graphics.
367 #TODO Remove this option or make it useful.
368 config HAVE_LOW_TABLES
372 This Option is unused in the code. Since two boards try to set it to
373 'n', they may be broken. We either need to make the option useful or
374 get rid of it. The broken boards are:
378 config HAVE_HIGH_TABLES
382 This variable specifies whether a given northbridge has high table
384 It is set in northbridge/*/Kconfig.
385 Whether or not the high tables are actually written by coreboot is
386 configurable by the user via WRITE_HIGH_TABLES.
388 config HAVE_ACPI_TABLES
391 This variable specifies whether a given board has ACPI table support.
392 It is usually set in mainboard/*/Kconfig.
393 Whether or not the ACPI tables are actually generated by coreboot
394 is configurable by the user via GENERATE_ACPI_TABLES.
399 This variable specifies whether a given board has MP table support.
400 It is usually set in mainboard/*/Kconfig.
401 Whether or not the MP table is actually generated by coreboot
402 is configurable by the user via GENERATE_MP_TABLE.
404 config HAVE_PIRQ_TABLE
407 This variable specifies whether a given board has PIRQ table support.
408 It is usually set in mainboard/*/Kconfig.
409 Whether or not the PIRQ table is actually generated by coreboot
410 is configurable by the user via GENERATE_PIRQ_TABLE.
412 #These Options are here to avoid "undefined" warnings.
413 #The actual selection and help texts are in the following menu.
415 config GENERATE_ACPI_TABLES
417 default HAVE_ACPI_TABLES
419 config GENERATE_MP_TABLE
421 default HAVE_MP_TABLE
423 config GENERATE_PIRQ_TABLE
425 default HAVE_PIRQ_TABLE
427 config WRITE_HIGH_TABLES
429 default HAVE_HIGH_TABLES
433 config WRITE_HIGH_TABLES
434 bool "Write 'high' tables to avoid being overwritten in F segment"
435 depends on HAVE_HIGH_TABLES
439 bool "Generate Multiboot tables (for GRUB2)"
442 config GENERATE_ACPI_TABLES
443 depends on HAVE_ACPI_TABLES
444 bool "Generate ACPI tables"
447 Generate ACPI tables for this board.
451 config GENERATE_MP_TABLE
452 depends on HAVE_MP_TABLE
453 bool "Generate an MP table"
456 Generate an MP table (conforming to the Intel MultiProcessor
457 specification 1.4) for this board.
461 config GENERATE_PIRQ_TABLE
462 depends on HAVE_PIRQ_TABLE
463 bool "Generate a PIRQ table"
466 Generate a PIRQ table for this board.
475 prompt "Add a payload"
481 Select this option if you want to create an "empty" coreboot
482 ROM image for a certain mainboard, i.e. a coreboot ROM image
483 which does not yet contain a payload.
485 For such an image to be useful, you have to use 'cbfstool'
486 to add a payload to the ROM image later.
489 bool "An ELF executable payload"
491 Select this option if you have a payload image (an ELF file)
492 which coreboot should run as soon as the basic hardware
493 initialization is completed.
495 You will be able to specify the location and file name of the
500 config FALLBACK_PAYLOAD_FILE
501 string "Payload path and filename"
502 depends on PAYLOAD_ELF
503 default "payload.elf"
505 The path and filename of the ELF executable file to use as payload.
507 # TODO: Defined if no payload? Breaks build?
508 config COMPRESSED_PAYLOAD_LZMA
509 bool "Use LZMA compression for payloads"
511 depends on PAYLOAD_ELF
513 In order to reduce the size payloads take up in the ROM chip
514 coreboot can compress them using the LZMA algorithm.
516 config COMPRESSED_PAYLOAD_NRV2B
525 bool "Add a VGA BIOS image"
527 Select this option if you have a VGA BIOS image that you would
528 like to add to your ROM.
530 You will be able to specify the location and file name of the
533 config FALLBACK_VGA_BIOS_FILE
534 string "VGA BIOS path and filename"
536 default "vgabios.bin"
538 The path and filename of the file to use as VGA BIOS.
540 config FALLBACK_VGA_BIOS_ID
541 string "VGA device PCI IDs"
545 The comma-separated PCI vendor and device ID that would associate
546 your VGA BIOS to your video card.
550 In the above example 1106 is the PCI vendor ID (in hex, but without
551 the "0x" prefix) and 3230 specifies the PCI device ID of the
552 video card (also in hex, without "0x" prefix).
555 bool "Add an MBI image"
556 depends on NORTHBRIDGE_INTEL_I82830
558 Select this option if you have an Intel MBI image that you would
559 like to add to your ROM.
561 You will be able to specify the location and file name of the
564 config FALLBACK_MBI_FILE
565 string "Intel MBI path and filename"
569 The path and filename of the file to use as VGA BIOS.
574 depends on PCI_OPTION_ROM_RUN_YABEL
577 prompt "Show graphical bootsplash"
579 depends on PCI_OPTION_ROM_RUN_YABEL
581 This option shows a graphical bootsplash screen. The grapics are
582 loaded from the CBFS file bootsplash.jpg.
584 config FALLBACK_BOOTSPLASH_FILE
585 string "Bootsplash path and filename"
586 depends on BOOTSPLASH
587 default "bootsplash.jpg"
589 The path and filename of the file to use as graphical bootsplash
590 screen. The file format has to be jpg.
592 # TODO: Turn this into a "choice".
593 config FRAMEBUFFER_VESA_MODE
594 prompt "VESA framebuffer video mode"
597 depends on BOOTSPLASH
599 This option sets the resolution used for the coreboot framebuffer and
600 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
601 some day make this a "choice".
603 config COREBOOT_KEEP_FRAMEBUFFER
604 prompt "Keep VESA framebuffer"
606 depends on BOOTSPLASH
608 This option keeps the framebuffer mode set after coreboot finishes
609 execution. If this option is enabled, coreboot will pass a
610 framebuffer entry in its coreboot table and the payload will need a
611 framebuffer driver. If this option is disabled, coreboot will switch
612 back to text mode before handing control to a payload.
618 # TODO: Better help text and detailed instructions.
620 bool "GDB debugging support"
623 If enabled, you will be able to set breakpoints for gdb debugging.
624 See src/arch/i386/lib/c_start.S for details.
626 config DEBUG_RAM_SETUP
627 bool "Output verbose RAM init debug messages"
629 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
630 || NORTHBRIDGE_AMD_AMDK8 \
631 || NORTHBRIDGE_VIA_CN700 \
632 || NORTHBRIDGE_VIA_CX700 \
633 || NORTHBRIDGE_VIA_VX800 \
634 || NORTHBRIDGE_INTEL_E7501 \
635 || NORTHBRIDGE_INTEL_I440BX \
636 || NORTHBRIDGE_INTEL_I82810 \
637 || NORTHBRIDGE_INTEL_I82830 \
638 || NORTHBRIDGE_INTEL_I945)
640 This option enables additional RAM init related debug messages.
641 It is recommended to enable this when debugging issues on your
642 board which might be RAM init related.
644 Note: This option will increase the size of the coreboot image.
649 bool "Output verbose SMBus debug messages"
651 depends on (SOUTHBRIDGE_VIA_VT8237R \
652 || NORTHBRIDGE_VIA_VX800 \
653 || NORTHBRIDGE_VIA_CX700 \
654 || NORTHBRIDGE_AMD_AMDK8)
656 This option enables additional SMBus (and SPD) debug messages.
658 Note: This option will increase the size of the coreboot image.
663 bool "Output verbose SMI debug messages"
665 depends on HAVE_SMI_HANDLER
667 This option enables additional SMI related debug messages.
669 Note: This option will increase the size of the coreboot image.
674 bool "Output verbose x86emu debug messages"
676 depends on PCI_OPTION_ROM_RUN_YABEL
678 This option enables additional x86emu related debug messages.
680 Note: This option will increase the size of the coreboot image.
684 config X86EMU_DEBUG_JMP
685 bool "Trace JMP/RETF"
687 depends on X86EMU_DEBUG
689 Print information about JMP and RETF opcodes from x86emu.
691 Note: This option will increase the size of the coreboot image.
695 config X86EMU_DEBUG_TRACE
696 bool "Trace all opcodes"
698 depends on X86EMU_DEBUG
700 Print _all_ opcodes that are executed by x86emu.
702 WARNING: This will produce a LOT of output and take a long time.
704 Note: This option will increase the size of the coreboot image.
708 config X86EMU_DEBUG_PNP
709 bool "Log Plug&Play accesses"
711 depends on X86EMU_DEBUG
713 Print Plug And Play accesses made by option ROMs.
715 Note: This option will increase the size of the coreboot image.
719 config X86EMU_DEBUG_DISK
722 depends on X86EMU_DEBUG
724 Print Disk I/O related messages.
726 Note: This option will increase the size of the coreboot image.
730 config X86EMU_DEBUG_PMM
733 depends on X86EMU_DEBUG
735 Print messages related to POST Memory Manager (PMM).
737 Note: This option will increase the size of the coreboot image.
742 config X86EMU_DEBUG_VBE
743 bool "Debug VESA BIOS Extensions"
745 depends on X86EMU_DEBUG
747 Print messages related to VESA BIOS Extension (VBE) functions.
749 Note: This option will increase the size of the coreboot image.
753 config X86EMU_DEBUG_INT10
754 bool "Redirect INT10 output to console"
756 depends on X86EMU_DEBUG
758 Let INT10 (i.e. character output) calls print messages to debug output.
760 Note: This option will increase the size of the coreboot image.
764 config X86EMU_DEBUG_INTERRUPTS
765 bool "Log intXX calls"
767 depends on X86EMU_DEBUG
769 Print messages related to interrupt handling.
771 Note: This option will increase the size of the coreboot image.
775 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
776 bool "Log special memory accesses"
778 depends on X86EMU_DEBUG
780 Print messages related to accesses to certain areas of the virtual
781 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
783 Note: This option will increase the size of the coreboot image.
787 config X86EMU_DEBUG_MEM
788 bool "Log all memory accesses"
790 depends on X86EMU_DEBUG
792 Print memory accesses made by option ROM.
793 Note: This also includes accesses to fetch instructions.
795 Note: This option will increase the size of the coreboot image.
799 config X86EMU_DEBUG_IO
800 bool "Log IO accesses"
802 depends on X86EMU_DEBUG
804 Print I/O accesses made by option ROM.
806 Note: This option will increase the size of the coreboot image.
811 bool "Built-in low-level shell"
814 If enabled, you will have a low level shell to examine your machine.
815 Put llshell() in your (romstage) code to start the shell.
816 See src/arch/i386/llshell/llshell.inc for details.
820 config LIFT_BSP_APIC_ID
824 # These probably belong somewhere else, but they are needed somewhere.
825 config AP_CODE_IN_CAR
833 config ENABLE_APIC_EXT_ID
837 config WARNINGS_ARE_ERRORS
841 config ID_SECTION_OFFSET