2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
83 config SCONFIG_GENPARSER
84 bool "Generate SCONFIG parser using flex and bison"
88 Enable this option if you are working on the sconfig
89 device tree parser and made changes to sconfig.l and
93 config USE_OPTION_TABLE
94 bool "Use CMOS for configuration values"
96 depends on HAVE_OPTION_TABLE
98 Enable this option if coreboot shall read options from the "CMOS"
99 NVRAM instead of using hard coded values.
101 config COMPRESS_RAMSTAGE
102 bool "Compress ramstage with LZMA"
105 Compress ramstage to save memory in the flash image. Note
106 that decompression might slow down booting if the boot flash
107 is connected through a slow Link (i.e. SPI)
109 config INCLUDE_CONFIG_FILE
110 bool "Include the coreboot config file into the ROM image"
113 Include in CBFS the coreboot config file that was used to compile the ROM image
115 config EARLY_CBMEM_INIT
116 bool "Initialize CBMEM while in ROM stage"
119 Make coreboot initialize the cbmem structures while running in rom
120 stage. This could be useful when the rom stage wants to communicate
121 some, for instance, execution timestamps.
123 config COLLECT_TIMESTAMPS
124 bool "Create a table of timestamps collected during boot"
125 depends on EARLY_CBMEM_INIT
127 Make coreboot create a table of timer id/timer value pairs to
128 allow measuring time spent at different phases of the boot
132 source src/mainboard/Kconfig
134 # This option is used to set the architecture of a mainboard to X86.
135 # It is usually set in mainboard/*/Kconfig.
141 source src/arch/x86/Kconfig
147 source src/cpu/Kconfig
148 comment "Northbridge"
149 source src/northbridge/Kconfig
150 comment "Southbridge"
151 source src/southbridge/Kconfig
153 source src/superio/Kconfig
155 source src/devices/Kconfig
156 comment "Embedded Controllers"
157 source src/ec/Kconfig
161 menu "Generic Drivers"
162 source src/drivers/Kconfig
165 config PCI_BUS_SEGN_BITS
181 config MMCONF_SUPPORT_DEFAULT
185 config MMCONF_SUPPORT
189 source src/console/Kconfig
191 # This should default to N and be set by SuperI/O drivers that have an UART
192 config HAVE_UART_IO_MAPPED
196 config HAVE_UART_MEMORY_MAPPED
200 config HAVE_ACPI_RESUME
204 config HAVE_ACPI_SLIC
208 config ACPI_SSDTX_NUM
212 config HAVE_HARD_RESET
214 default y if BOARD_HAS_HARD_RESET
217 This variable specifies whether a given board has a hard_reset
218 function, no matter if it's provided by board code or chipset code.
220 config HAVE_INIT_TIMER
222 default n if UDELAY_IO
225 config HAVE_MAINBOARD_RESOURCES
229 config USE_OPTION_TABLE
233 config HAVE_OPTION_TABLE
237 This variable specifies whether a given board has a cmos.layout
238 file containing NVRAM/CMOS bit definitions.
239 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
245 config HAVE_SMI_HANDLER
249 config PCI_IO_CFG_EXT
257 # TODO: Can probably be removed once all chipsets have kconfig options for it.
262 config USE_WATCHDOG_ON_BOOT
270 Build board-specific VGA code.
276 Enable Unified Memory Architecture for graphics.
283 config HAVE_ACPI_TABLES
286 This variable specifies whether a given board has ACPI table support.
287 It is usually set in mainboard/*/Kconfig.
288 Whether or not the ACPI tables are actually generated by coreboot
289 is configurable by the user via GENERATE_ACPI_TABLES.
294 This variable specifies whether a given board has MP table support.
295 It is usually set in mainboard/*/Kconfig.
296 Whether or not the MP table is actually generated by coreboot
297 is configurable by the user via GENERATE_MP_TABLE.
299 config HAVE_PIRQ_TABLE
302 This variable specifies whether a given board has PIRQ table support.
303 It is usually set in mainboard/*/Kconfig.
304 Whether or not the PIRQ table is actually generated by coreboot
305 is configurable by the user via GENERATE_PIRQ_TABLE.
307 #These Options are here to avoid "undefined" warnings.
308 #The actual selection and help texts are in the following menu.
310 config GENERATE_ACPI_TABLES
312 default HAVE_ACPI_TABLES
314 config GENERATE_MP_TABLE
316 default HAVE_MP_TABLE
318 config GENERATE_PIRQ_TABLE
320 default HAVE_PIRQ_TABLE
322 config GENERATE_SMBIOS_TABLES
328 config WRITE_HIGH_TABLES
329 bool "Write 'high' tables to avoid being overwritten in F segment"
333 bool "Generate Multiboot tables (for GRUB2)"
336 config GENERATE_ACPI_TABLES
337 depends on HAVE_ACPI_TABLES
338 bool "Generate ACPI tables"
341 Generate ACPI tables for this board.
345 config GENERATE_MP_TABLE
346 depends on HAVE_MP_TABLE
347 bool "Generate an MP table"
350 Generate an MP table (conforming to the Intel MultiProcessor
351 specification 1.4) for this board.
355 config GENERATE_PIRQ_TABLE
356 depends on HAVE_PIRQ_TABLE
357 bool "Generate a PIRQ table"
360 Generate a PIRQ table for this board.
364 config GENERATE_SMBIOS_TABLES
366 bool "Generate SMBIOS tables"
369 Generate SMBIOS tables for this board.
378 prompt "Add a payload"
379 default PAYLOAD_NONE if !ARCH_X86
380 default PAYLOAD_SEABIOS if ARCH_X86
385 Select this option if you want to create an "empty" coreboot
386 ROM image for a certain mainboard, i.e. a coreboot ROM image
387 which does not yet contain a payload.
389 For such an image to be useful, you have to use 'cbfstool'
390 to add a payload to the ROM image later.
393 bool "An ELF executable payload"
395 Select this option if you have a payload image (an ELF file)
396 which coreboot should run as soon as the basic hardware
397 initialization is completed.
399 You will be able to specify the location and file name of the
402 config PAYLOAD_SEABIOS
406 Select this option if you want to build a coreboot image
407 with a SeaBIOS payload. If you don't know what this is
408 about, just leave it enabled.
410 See http://coreboot.org/Payloads for more information.
415 Select this option if you want to build a coreboot image
416 with a FILO payload. If you don't know what this is
417 about, just leave it enabled.
419 See http://coreboot.org/Payloads for more information.
424 prompt "SeaBIOS version"
425 default SEABIOS_STABLE
426 depends on PAYLOAD_SEABIOS
428 config SEABIOS_STABLE
431 Stable SeaBIOS version
432 config SEABIOS_MASTER
435 Newest SeaBIOS version
439 prompt "FILO version"
441 depends on PAYLOAD_FILO
454 string "Payload path and filename"
455 depends on PAYLOAD_ELF
456 default "payload.elf"
458 The path and filename of the ELF executable file to use as payload.
461 depends on PAYLOAD_SEABIOS
462 default "$(obj)/seabios/out/bios.bin.elf"
465 depends on PAYLOAD_FILO
466 default "payloads/external/FILO/filo/build/filo.elf"
468 # TODO: Defined if no payload? Breaks build?
469 config COMPRESSED_PAYLOAD_LZMA
470 bool "Use LZMA compression for payloads"
472 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO
474 In order to reduce the size payloads take up in the ROM chip
475 coreboot can compress them using the LZMA algorithm.
477 config COMPRESSED_PAYLOAD_NRV2B
486 bool "Add a VGA BIOS image"
488 Select this option if you have a VGA BIOS image that you would
489 like to add to your ROM.
491 You will be able to specify the location and file name of the
495 string "VGA BIOS path and filename"
497 default "vgabios.bin"
499 The path and filename of the file to use as VGA BIOS.
502 string "VGA device PCI IDs"
506 The comma-separated PCI vendor and device ID that would associate
507 your VGA BIOS to your video card.
511 In the above example 1106 is the PCI vendor ID (in hex, but without
512 the "0x" prefix) and 3230 specifies the PCI device ID of the
513 video card (also in hex, without "0x" prefix).
516 bool "Add an MBI image"
517 depends on NORTHBRIDGE_INTEL_I82830
519 Select this option if you have an Intel MBI image that you would
520 like to add to your ROM.
522 You will be able to specify the location and file name of the
526 string "Intel MBI path and filename"
530 The path and filename of the file to use as VGA BIOS.
535 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
537 config FRAMEBUFFER_SET_VESA_MODE
538 prompt "Set VESA framebuffer mode"
540 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
542 Set VESA framebuffer mode (needed for bootsplash)
544 # TODO: Turn this into a "choice".
545 config FRAMEBUFFER_VESA_MODE
546 prompt "VESA framebuffer video mode"
549 depends on FRAMEBUFFER_SET_VESA_MODE
551 This option sets the resolution used for the coreboot framebuffer (and
552 bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will
553 some day make this a "choice".
555 config FRAMEBUFFER_KEEP_VESA_MODE
556 prompt "Keep VESA framebuffer"
558 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
560 This option keeps the framebuffer mode set after coreboot finishes
561 execution. If this option is enabled, coreboot will pass a
562 framebuffer entry in its coreboot table and the payload will need a
563 framebuffer driver. If this option is disabled, coreboot will switch
564 back to text mode before handing control to a payload.
567 prompt "Show graphical bootsplash"
569 depends on FRAMEBUFFER_SET_VESA_MODE
571 This option shows a graphical bootsplash screen. The grapics are
572 loaded from the CBFS file bootsplash.jpg.
574 config BOOTSPLASH_FILE
575 string "Bootsplash path and filename"
576 depends on BOOTSPLASH
577 default "bootsplash.jpg"
579 The path and filename of the file to use as graphical bootsplash
580 screen. The file format has to be jpg.
585 # TODO: Better help text and detailed instructions.
587 bool "GDB debugging support"
590 If enabled, you will be able to set breakpoints for gdb debugging.
591 See src/arch/x86/lib/c_start.S for details.
593 config HAVE_DEBUG_RAM_SETUP
596 config DEBUG_RAM_SETUP
597 bool "Output verbose RAM init debug messages"
599 depends on HAVE_DEBUG_RAM_SETUP
601 This option enables additional RAM init related debug messages.
602 It is recommended to enable this when debugging issues on your
603 board which might be RAM init related.
605 Note: This option will increase the size of the coreboot image.
609 config HAVE_DEBUG_CAR
614 depends on HAVE_DEBUG_CAR
616 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
617 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
618 # printk(BIOS_DEBUG, ...) calls.
620 bool "Output verbose Cache-as-RAM debug messages"
622 depends on HAVE_DEBUG_CAR
624 This option enables additional CAR related debug messages.
628 bool "Check PIRQ table consistency"
630 depends on GENERATE_PIRQ_TABLE
634 config HAVE_DEBUG_SMBUS
638 bool "Output verbose SMBus debug messages"
640 depends on HAVE_DEBUG_SMBUS
642 This option enables additional SMBus (and SPD) debug messages.
644 Note: This option will increase the size of the coreboot image.
649 bool "Output verbose SMI debug messages"
651 depends on HAVE_SMI_HANDLER
653 This option enables additional SMI related debug messages.
655 Note: This option will increase the size of the coreboot image.
659 config DEBUG_SMM_RELOCATION
660 bool "Debug SMM relocation code"
662 depends on HAVE_SMI_HANDLER
664 This option enables additional SMM handler relocation related
667 Note: This option will increase the size of the coreboot image.
674 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
675 # printk(BIOS_DEBUG, ...) calls.
676 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
678 bool "Output verbose malloc debug messages"
681 This option enables additional malloc related debug messages.
683 Note: This option will increase the size of the coreboot image.
691 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
692 # printk(BIOS_DEBUG, ...) calls.
693 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
695 bool "Output verbose ACPI debug messages"
698 This option enables additional ACPI related debug messages.
700 Note: This option will slightly increase the size of the coreboot image.
705 config REALMODE_DEBUG
707 depends on PCI_OPTION_ROM_RUN_REALMODE
709 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
710 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
711 # printk(BIOS_DEBUG, ...) calls.
712 config REALMODE_DEBUG
713 bool "Enable debug messages for option ROM execution"
715 depends on PCI_OPTION_ROM_RUN_REALMODE
717 This option enables additional x86emu related debug messages.
719 Note: This option will increase the time to emulate a ROM.
725 bool "Output verbose x86emu debug messages"
727 depends on PCI_OPTION_ROM_RUN_YABEL
729 This option enables additional x86emu related debug messages.
731 Note: This option will increase the size of the coreboot image.
735 config X86EMU_DEBUG_JMP
736 bool "Trace JMP/RETF"
738 depends on X86EMU_DEBUG
740 Print information about JMP and RETF opcodes from x86emu.
742 Note: This option will increase the size of the coreboot image.
746 config X86EMU_DEBUG_TRACE
747 bool "Trace all opcodes"
749 depends on X86EMU_DEBUG
751 Print _all_ opcodes that are executed by x86emu.
753 WARNING: This will produce a LOT of output and take a long time.
755 Note: This option will increase the size of the coreboot image.
759 config X86EMU_DEBUG_PNP
760 bool "Log Plug&Play accesses"
762 depends on X86EMU_DEBUG
764 Print Plug And Play accesses made by option ROMs.
766 Note: This option will increase the size of the coreboot image.
770 config X86EMU_DEBUG_DISK
773 depends on X86EMU_DEBUG
775 Print Disk I/O related messages.
777 Note: This option will increase the size of the coreboot image.
781 config X86EMU_DEBUG_PMM
784 depends on X86EMU_DEBUG
786 Print messages related to POST Memory Manager (PMM).
788 Note: This option will increase the size of the coreboot image.
793 config X86EMU_DEBUG_VBE
794 bool "Debug VESA BIOS Extensions"
796 depends on X86EMU_DEBUG
798 Print messages related to VESA BIOS Extension (VBE) functions.
800 Note: This option will increase the size of the coreboot image.
804 config X86EMU_DEBUG_INT10
805 bool "Redirect INT10 output to console"
807 depends on X86EMU_DEBUG
809 Let INT10 (i.e. character output) calls print messages to debug output.
811 Note: This option will increase the size of the coreboot image.
815 config X86EMU_DEBUG_INTERRUPTS
816 bool "Log intXX calls"
818 depends on X86EMU_DEBUG
820 Print messages related to interrupt handling.
822 Note: This option will increase the size of the coreboot image.
826 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
827 bool "Log special memory accesses"
829 depends on X86EMU_DEBUG
831 Print messages related to accesses to certain areas of the virtual
832 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
834 Note: This option will increase the size of the coreboot image.
838 config X86EMU_DEBUG_MEM
839 bool "Log all memory accesses"
841 depends on X86EMU_DEBUG
843 Print memory accesses made by option ROM.
844 Note: This also includes accesses to fetch instructions.
846 Note: This option will increase the size of the coreboot image.
850 config X86EMU_DEBUG_IO
851 bool "Log IO accesses"
853 depends on X86EMU_DEBUG
855 Print I/O accesses made by option ROM.
857 Note: This option will increase the size of the coreboot image.
862 bool "Built-in low-level shell"
865 If enabled, you will have a low level shell to examine your machine.
866 Put llshell() in your (romstage) code to start the shell.
867 See src/arch/x86/llshell/llshell.inc for details.
870 bool "Trace function calls"
873 If enabled, every function will print information to console once
874 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
875 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
876 of calling function. Please note some printk releated functions
877 are omitted from trace to have good looking console dumps.
880 config LIFT_BSP_APIC_ID
884 # These probably belong somewhere else, but they are needed somewhere.
885 config AP_CODE_IN_CAR
889 config RAMINIT_SYSINFO
893 config ENABLE_APIC_EXT_ID
897 config WARNINGS_ARE_ERRORS
901 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
902 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
903 # mutually exclusive. One of these options must be selected in the
904 # mainboard Kconfig if the chipset supports enabling and disabling of
905 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
906 # in mainboard/Kconfig to know if the button should be enabled or not.
908 config POWER_BUTTON_DEFAULT_ENABLE
911 Select when the board has a power button which can optionally be
912 disabled by the user.
914 config POWER_BUTTON_DEFAULT_DISABLE
917 Select when the board has a power button which can optionally be
918 enabled by the user, e.g. when the board ships with a jumper over
919 the power switch contacts.
921 config POWER_BUTTON_FORCE_ENABLE
924 Select when the board requires that the power button is always
927 config POWER_BUTTON_FORCE_DISABLE
930 Select when the board requires that the power button is always
931 disabled, e.g. when it has been hardwired to ground.
933 config POWER_BUTTON_IS_OPTIONAL
935 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
936 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
938 Internal option that controls ENABLE_POWER_BUTTON visibility.
940 source src/Kconfig.deprecated_options
941 source src/vendorcode/Kconfig