2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
83 config SCONFIG_GENPARSER
84 bool "Generate SCONFIG parser using flex and bison"
88 Enable this option if you are working on the sconfig
89 device tree parser and made changes to sconfig.l and
93 config USE_OPTION_TABLE
94 bool "Use CMOS for configuration values"
96 depends on HAVE_OPTION_TABLE
98 Enable this option if coreboot shall read options from the "CMOS"
99 NVRAM instead of using hard coded values.
103 source src/mainboard/Kconfig
104 source src/arch/i386/Kconfig
109 source src/cpu/Kconfig
110 comment "Northbridge"
111 source src/northbridge/Kconfig
112 comment "Southbridge"
113 source src/southbridge/Kconfig
115 source src/superio/Kconfig
117 source src/devices/Kconfig
121 menu "Generic Drivers"
122 source src/drivers/Kconfig
125 config PCI_BUS_SEGN_BITS
129 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
133 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
157 config MMCONF_SUPPORT_DEFAULT
161 config MMCONF_SUPPORT
168 source src/console/Kconfig
170 config HAVE_ACPI_RESUME
174 config HAVE_ACPI_SLIC
178 config ACPI_SSDTX_NUM
182 config HAVE_HARD_RESET
184 default y if BOARD_HAS_HARD_RESET
187 This variable specifies whether a given board has a hard_reset
188 function, no matter if it's provided by board code or chipset code.
190 config HAVE_INIT_TIMER
192 default n if UDELAY_IO
195 config HAVE_MAINBOARD_RESOURCES
199 config USE_OPTION_TABLE
203 config HAVE_OPTION_TABLE
207 This variable specifies whether a given board has a cmos.layout
208 file containing NVRAM/CMOS bit definitions.
209 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
215 config HAVE_SMI_HANDLER
219 config PCI_IO_CFG_EXT
227 # TODO: Can probably be removed once all chipsets have kconfig options for it.
232 config USE_WATCHDOG_ON_BOOT
240 Build board-specific VGA code.
246 Enable Unified Memory Architecture for graphics.
253 config HAVE_ACPI_TABLES
256 This variable specifies whether a given board has ACPI table support.
257 It is usually set in mainboard/*/Kconfig.
258 Whether or not the ACPI tables are actually generated by coreboot
259 is configurable by the user via GENERATE_ACPI_TABLES.
264 This variable specifies whether a given board has MP table support.
265 It is usually set in mainboard/*/Kconfig.
266 Whether or not the MP table is actually generated by coreboot
267 is configurable by the user via GENERATE_MP_TABLE.
269 config HAVE_PIRQ_TABLE
272 This variable specifies whether a given board has PIRQ table support.
273 It is usually set in mainboard/*/Kconfig.
274 Whether or not the PIRQ table is actually generated by coreboot
275 is configurable by the user via GENERATE_PIRQ_TABLE.
277 #These Options are here to avoid "undefined" warnings.
278 #The actual selection and help texts are in the following menu.
280 config GENERATE_ACPI_TABLES
282 default HAVE_ACPI_TABLES
284 config GENERATE_MP_TABLE
286 default HAVE_MP_TABLE
288 config GENERATE_PIRQ_TABLE
290 default HAVE_PIRQ_TABLE
294 config WRITE_HIGH_TABLES
295 bool "Write 'high' tables to avoid being overwritten in F segment"
299 bool "Generate Multiboot tables (for GRUB2)"
302 config GENERATE_ACPI_TABLES
303 depends on HAVE_ACPI_TABLES
304 bool "Generate ACPI tables"
307 Generate ACPI tables for this board.
311 config GENERATE_MP_TABLE
312 depends on HAVE_MP_TABLE
313 bool "Generate an MP table"
316 Generate an MP table (conforming to the Intel MultiProcessor
317 specification 1.4) for this board.
321 config GENERATE_PIRQ_TABLE
322 depends on HAVE_PIRQ_TABLE
323 bool "Generate a PIRQ table"
326 Generate a PIRQ table for this board.
335 prompt "Add a payload"
341 Select this option if you want to create an "empty" coreboot
342 ROM image for a certain mainboard, i.e. a coreboot ROM image
343 which does not yet contain a payload.
345 For such an image to be useful, you have to use 'cbfstool'
346 to add a payload to the ROM image later.
349 bool "An ELF executable payload"
351 Select this option if you have a payload image (an ELF file)
352 which coreboot should run as soon as the basic hardware
353 initialization is completed.
355 You will be able to specify the location and file name of the
360 config FALLBACK_PAYLOAD_FILE
361 string "Payload path and filename"
362 depends on PAYLOAD_ELF
363 default "payload.elf"
365 The path and filename of the ELF executable file to use as payload.
367 # TODO: Defined if no payload? Breaks build?
368 config COMPRESSED_PAYLOAD_LZMA
369 bool "Use LZMA compression for payloads"
371 depends on PAYLOAD_ELF
373 In order to reduce the size payloads take up in the ROM chip
374 coreboot can compress them using the LZMA algorithm.
376 config COMPRESSED_PAYLOAD_NRV2B
385 bool "Add a VGA BIOS image"
387 Select this option if you have a VGA BIOS image that you would
388 like to add to your ROM.
390 You will be able to specify the location and file name of the
393 config FALLBACK_VGA_BIOS_FILE
394 string "VGA BIOS path and filename"
396 default "vgabios.bin"
398 The path and filename of the file to use as VGA BIOS.
400 config FALLBACK_VGA_BIOS_ID
401 string "VGA device PCI IDs"
405 The comma-separated PCI vendor and device ID that would associate
406 your VGA BIOS to your video card.
410 In the above example 1106 is the PCI vendor ID (in hex, but without
411 the "0x" prefix) and 3230 specifies the PCI device ID of the
412 video card (also in hex, without "0x" prefix).
415 bool "Add an MBI image"
416 depends on NORTHBRIDGE_INTEL_I82830
418 Select this option if you have an Intel MBI image that you would
419 like to add to your ROM.
421 You will be able to specify the location and file name of the
424 config FALLBACK_MBI_FILE
425 string "Intel MBI path and filename"
429 The path and filename of the file to use as VGA BIOS.
434 depends on PCI_OPTION_ROM_RUN_YABEL
437 prompt "Show graphical bootsplash"
439 depends on PCI_OPTION_ROM_RUN_YABEL
441 This option shows a graphical bootsplash screen. The grapics are
442 loaded from the CBFS file bootsplash.jpg.
444 config FALLBACK_BOOTSPLASH_FILE
445 string "Bootsplash path and filename"
446 depends on BOOTSPLASH
447 default "bootsplash.jpg"
449 The path and filename of the file to use as graphical bootsplash
450 screen. The file format has to be jpg.
452 # TODO: Turn this into a "choice".
453 config FRAMEBUFFER_VESA_MODE
454 prompt "VESA framebuffer video mode"
457 depends on BOOTSPLASH
459 This option sets the resolution used for the coreboot framebuffer and
460 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
461 some day make this a "choice".
463 config COREBOOT_KEEP_FRAMEBUFFER
464 prompt "Keep VESA framebuffer"
466 depends on BOOTSPLASH
468 This option keeps the framebuffer mode set after coreboot finishes
469 execution. If this option is enabled, coreboot will pass a
470 framebuffer entry in its coreboot table and the payload will need a
471 framebuffer driver. If this option is disabled, coreboot will switch
472 back to text mode before handing control to a payload.
478 # TODO: Better help text and detailed instructions.
480 bool "GDB debugging support"
483 If enabled, you will be able to set breakpoints for gdb debugging.
484 See src/arch/i386/lib/c_start.S for details.
486 config HAVE_DEBUG_RAM_SETUP
489 config DEBUG_RAM_SETUP
490 bool "Output verbose RAM init debug messages"
492 depends on HAVE_DEBUG_RAM_SETUP
494 This option enables additional RAM init related debug messages.
495 It is recommended to enable this when debugging issues on your
496 board which might be RAM init related.
498 Note: This option will increase the size of the coreboot image.
502 config HAVE_DEBUG_CAR
505 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
506 # printk(BIOS_DEBUG, ...) calls.
508 bool "Output verbose Cache-as-RAM debug messages"
510 depends on HAVE_DEBUG_CAR && \
511 (DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8)
513 This option enables additional CAR related debug messages.
516 bool "Check PIRQ table consistency"
518 depends on GENERATE_PIRQ_TABLE
522 config HAVE_DEBUG_SMBUS
526 bool "Output verbose SMBus debug messages"
528 depends on HAVE_DEBUG_SMBUS
530 This option enables additional SMBus (and SPD) debug messages.
532 Note: This option will increase the size of the coreboot image.
537 bool "Output verbose SMI debug messages"
539 depends on HAVE_SMI_HANDLER
541 This option enables additional SMI related debug messages.
543 Note: This option will increase the size of the coreboot image.
547 config DEBUG_SMM_RELOCATION
548 bool "Debug SMM relocation code"
550 depends on HAVE_SMI_HANDLER
552 This option enables additional SMM handler relocation related
555 Note: This option will increase the size of the coreboot image.
559 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
560 # printk(BIOS_DEBUG, ...) calls.
562 bool "Output verbose malloc debug messages"
564 depends on DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
566 This option enables additional malloc related debug messages.
568 Note: This option will increase the size of the coreboot image.
572 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
573 # printk(BIOS_DEBUG, ...) calls.
574 config REALMODE_DEBUG
575 bool "Enable debug messages for option ROM execution"
577 depends on PCI_OPTION_ROM_RUN_REALMODE && \
578 (DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8)
580 This option enables additional x86emu related debug messages.
582 Note: This option will increase the time to emulate a ROM.
587 bool "Output verbose x86emu debug messages"
589 depends on PCI_OPTION_ROM_RUN_YABEL
591 This option enables additional x86emu related debug messages.
593 Note: This option will increase the size of the coreboot image.
597 config X86EMU_DEBUG_JMP
598 bool "Trace JMP/RETF"
600 depends on X86EMU_DEBUG
602 Print information about JMP and RETF opcodes from x86emu.
604 Note: This option will increase the size of the coreboot image.
608 config X86EMU_DEBUG_TRACE
609 bool "Trace all opcodes"
611 depends on X86EMU_DEBUG
613 Print _all_ opcodes that are executed by x86emu.
615 WARNING: This will produce a LOT of output and take a long time.
617 Note: This option will increase the size of the coreboot image.
621 config X86EMU_DEBUG_PNP
622 bool "Log Plug&Play accesses"
624 depends on X86EMU_DEBUG
626 Print Plug And Play accesses made by option ROMs.
628 Note: This option will increase the size of the coreboot image.
632 config X86EMU_DEBUG_DISK
635 depends on X86EMU_DEBUG
637 Print Disk I/O related messages.
639 Note: This option will increase the size of the coreboot image.
643 config X86EMU_DEBUG_PMM
646 depends on X86EMU_DEBUG
648 Print messages related to POST Memory Manager (PMM).
650 Note: This option will increase the size of the coreboot image.
655 config X86EMU_DEBUG_VBE
656 bool "Debug VESA BIOS Extensions"
658 depends on X86EMU_DEBUG
660 Print messages related to VESA BIOS Extension (VBE) functions.
662 Note: This option will increase the size of the coreboot image.
666 config X86EMU_DEBUG_INT10
667 bool "Redirect INT10 output to console"
669 depends on X86EMU_DEBUG
671 Let INT10 (i.e. character output) calls print messages to debug output.
673 Note: This option will increase the size of the coreboot image.
677 config X86EMU_DEBUG_INTERRUPTS
678 bool "Log intXX calls"
680 depends on X86EMU_DEBUG
682 Print messages related to interrupt handling.
684 Note: This option will increase the size of the coreboot image.
688 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
689 bool "Log special memory accesses"
691 depends on X86EMU_DEBUG
693 Print messages related to accesses to certain areas of the virtual
694 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
696 Note: This option will increase the size of the coreboot image.
700 config X86EMU_DEBUG_MEM
701 bool "Log all memory accesses"
703 depends on X86EMU_DEBUG
705 Print memory accesses made by option ROM.
706 Note: This also includes accesses to fetch instructions.
708 Note: This option will increase the size of the coreboot image.
712 config X86EMU_DEBUG_IO
713 bool "Log IO accesses"
715 depends on X86EMU_DEBUG
717 Print I/O accesses made by option ROM.
719 Note: This option will increase the size of the coreboot image.
724 bool "Built-in low-level shell"
727 If enabled, you will have a low level shell to examine your machine.
728 Put llshell() in your (romstage) code to start the shell.
729 See src/arch/i386/llshell/llshell.inc for details.
733 config LIFT_BSP_APIC_ID
737 # These probably belong somewhere else, but they are needed somewhere.
738 config AP_CODE_IN_CAR
742 config RAMINIT_SYSINFO
746 config ENABLE_APIC_EXT_ID
750 config WARNINGS_ARE_ERRORS
754 config ID_SECTION_OFFSET
758 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
759 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
760 # mutually exclusive. One of these options must be selected in the
761 # mainboard Kconfig if the chipset supports enabling and disabling of
762 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
763 # in mainboard/Kconfig to know if the button should be enabled or not.
765 config POWER_BUTTON_DEFAULT_ENABLE
768 Select when the board has a power button which can optionally be
769 disabled by the user.
771 config POWER_BUTTON_DEFAULT_DISABLE
774 Select when the board has a power button which can optionally be
775 enabled by the user, e.g. when the board ships with a jumper over
776 the power switch contacts.
778 config POWER_BUTTON_FORCE_ENABLE
781 Select when the board requires that the power button is always
784 config POWER_BUTTON_FORCE_DISABLE
787 Select when the board requires that the power button is always
788 disabled, e.g. when it has been hardwired to ground.
790 config POWER_BUTTON_IS_OPTIONAL
792 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
793 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
795 Internal option that controls ENABLE_POWER_BUTTON visibility.
797 source src/Kconfig.deprecated_options