2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
83 config SCONFIG_GENPARSER
84 bool "Generate SCONFIG parser using flex and bison"
88 Enable this option if you are working on the sconfig
89 device tree parser and made changes to sconfig.l and
93 config USE_OPTION_TABLE
94 bool "Use CMOS for configuration values"
96 depends on HAVE_OPTION_TABLE
98 Enable this option if coreboot shall read options from the "CMOS"
99 NVRAM instead of using hard coded values.
101 config COMPRESS_RAMSTAGE
102 bool "Compress ramstage with LZMA"
105 Compress ramstage to save memory in the flash image. Note
106 that decompression might slow down booting if the boot flash
107 is connected through a slow Link (i.e. SPI)
109 config INCLUDE_CONFIG_FILE
110 bool "Include the coreboot config file into the ROM image"
113 Include in CBFS the coreboot config file that was used to compile the ROM image
115 config EARLY_CBMEM_INIT
116 bool "Initialize CBMEM while in ROM stage"
119 Make coreboot initialize the cbmem structures while running in rom
120 stage. This could be useful when the rom stage wants to communicate
121 some, for instance, execution timestamps.
125 source src/mainboard/Kconfig
127 # This option is used to set the architecture of a mainboard to X86.
128 # It is usually set in mainboard/*/Kconfig.
134 source src/arch/x86/Kconfig
140 source src/cpu/Kconfig
141 comment "Northbridge"
142 source src/northbridge/Kconfig
143 comment "Southbridge"
144 source src/southbridge/Kconfig
146 source src/superio/Kconfig
148 source src/devices/Kconfig
149 comment "Embedded Controllers"
150 source src/ec/Kconfig
154 menu "Generic Drivers"
155 source src/drivers/Kconfig
158 config PCI_BUS_SEGN_BITS
174 config MMCONF_SUPPORT_DEFAULT
178 config MMCONF_SUPPORT
182 source src/console/Kconfig
184 # This should default to N and be set by SuperI/O drivers that have an UART
185 config HAVE_UART_IO_MAPPED
189 config HAVE_UART_MEMORY_MAPPED
193 config HAVE_ACPI_RESUME
197 config HAVE_ACPI_SLIC
201 config ACPI_SSDTX_NUM
205 config HAVE_HARD_RESET
207 default y if BOARD_HAS_HARD_RESET
210 This variable specifies whether a given board has a hard_reset
211 function, no matter if it's provided by board code or chipset code.
213 config HAVE_INIT_TIMER
215 default n if UDELAY_IO
218 config HAVE_MAINBOARD_RESOURCES
222 config USE_OPTION_TABLE
226 config HAVE_OPTION_TABLE
230 This variable specifies whether a given board has a cmos.layout
231 file containing NVRAM/CMOS bit definitions.
232 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
238 config HAVE_SMI_HANDLER
242 config PCI_IO_CFG_EXT
250 # TODO: Can probably be removed once all chipsets have kconfig options for it.
255 config USE_WATCHDOG_ON_BOOT
263 Build board-specific VGA code.
269 Enable Unified Memory Architecture for graphics.
276 config HAVE_ACPI_TABLES
279 This variable specifies whether a given board has ACPI table support.
280 It is usually set in mainboard/*/Kconfig.
281 Whether or not the ACPI tables are actually generated by coreboot
282 is configurable by the user via GENERATE_ACPI_TABLES.
287 This variable specifies whether a given board has MP table support.
288 It is usually set in mainboard/*/Kconfig.
289 Whether or not the MP table is actually generated by coreboot
290 is configurable by the user via GENERATE_MP_TABLE.
292 config HAVE_PIRQ_TABLE
295 This variable specifies whether a given board has PIRQ table support.
296 It is usually set in mainboard/*/Kconfig.
297 Whether or not the PIRQ table is actually generated by coreboot
298 is configurable by the user via GENERATE_PIRQ_TABLE.
300 #These Options are here to avoid "undefined" warnings.
301 #The actual selection and help texts are in the following menu.
303 config GENERATE_ACPI_TABLES
305 default HAVE_ACPI_TABLES
307 config GENERATE_MP_TABLE
309 default HAVE_MP_TABLE
311 config GENERATE_PIRQ_TABLE
313 default HAVE_PIRQ_TABLE
315 config GENERATE_SMBIOS_TABLES
321 config WRITE_HIGH_TABLES
322 bool "Write 'high' tables to avoid being overwritten in F segment"
326 bool "Generate Multiboot tables (for GRUB2)"
329 config GENERATE_ACPI_TABLES
330 depends on HAVE_ACPI_TABLES
331 bool "Generate ACPI tables"
334 Generate ACPI tables for this board.
338 config GENERATE_MP_TABLE
339 depends on HAVE_MP_TABLE
340 bool "Generate an MP table"
343 Generate an MP table (conforming to the Intel MultiProcessor
344 specification 1.4) for this board.
348 config GENERATE_PIRQ_TABLE
349 depends on HAVE_PIRQ_TABLE
350 bool "Generate a PIRQ table"
353 Generate a PIRQ table for this board.
357 config GENERATE_SMBIOS_TABLES
359 bool "Generate SMBIOS tables"
362 Generate SMBIOS tables for this board.
371 prompt "Add a payload"
372 default PAYLOAD_NONE if !ARCH_X86
373 default PAYLOAD_SEABIOS if ARCH_X86
378 Select this option if you want to create an "empty" coreboot
379 ROM image for a certain mainboard, i.e. a coreboot ROM image
380 which does not yet contain a payload.
382 For such an image to be useful, you have to use 'cbfstool'
383 to add a payload to the ROM image later.
386 bool "An ELF executable payload"
388 Select this option if you have a payload image (an ELF file)
389 which coreboot should run as soon as the basic hardware
390 initialization is completed.
392 You will be able to specify the location and file name of the
395 config PAYLOAD_SEABIOS
399 Select this option if you want to build a coreboot image
400 with a SeaBIOS payload. If you don't know what this is
401 about, just leave it enabled.
403 See http://coreboot.org/Payloads for more information.
408 Select this option if you want to build a coreboot image
409 with a FILO payload. If you don't know what this is
410 about, just leave it enabled.
412 See http://coreboot.org/Payloads for more information.
417 prompt "SeaBIOS version"
418 default SEABIOS_STABLE
419 depends on PAYLOAD_SEABIOS
421 config SEABIOS_STABLE
424 Stable SeaBIOS version
425 config SEABIOS_MASTER
428 Newest SeaBIOS version
432 prompt "FILO version"
434 depends on PAYLOAD_FILO
447 string "Payload path and filename"
448 depends on PAYLOAD_ELF
449 default "payload.elf"
451 The path and filename of the ELF executable file to use as payload.
454 depends on PAYLOAD_SEABIOS
455 default "$(obj)/seabios/out/bios.bin.elf"
458 depends on PAYLOAD_FILO
459 default "payloads/external/FILO/filo/build/filo.elf"
461 # TODO: Defined if no payload? Breaks build?
462 config COMPRESSED_PAYLOAD_LZMA
463 bool "Use LZMA compression for payloads"
465 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO
467 In order to reduce the size payloads take up in the ROM chip
468 coreboot can compress them using the LZMA algorithm.
470 config COMPRESSED_PAYLOAD_NRV2B
479 bool "Add a VGA BIOS image"
481 Select this option if you have a VGA BIOS image that you would
482 like to add to your ROM.
484 You will be able to specify the location and file name of the
488 string "VGA BIOS path and filename"
490 default "vgabios.bin"
492 The path and filename of the file to use as VGA BIOS.
495 string "VGA device PCI IDs"
499 The comma-separated PCI vendor and device ID that would associate
500 your VGA BIOS to your video card.
504 In the above example 1106 is the PCI vendor ID (in hex, but without
505 the "0x" prefix) and 3230 specifies the PCI device ID of the
506 video card (also in hex, without "0x" prefix).
509 bool "Add an MBI image"
510 depends on NORTHBRIDGE_INTEL_I82830
512 Select this option if you have an Intel MBI image that you would
513 like to add to your ROM.
515 You will be able to specify the location and file name of the
519 string "Intel MBI path and filename"
523 The path and filename of the file to use as VGA BIOS.
528 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
530 config FRAMEBUFFER_SET_VESA_MODE
531 prompt "Set VESA framebuffer mode"
533 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
535 Set VESA framebuffer mode (needed for bootsplash)
537 # TODO: Turn this into a "choice".
538 config FRAMEBUFFER_VESA_MODE
539 prompt "VESA framebuffer video mode"
542 depends on FRAMEBUFFER_SET_VESA_MODE
544 This option sets the resolution used for the coreboot framebuffer (and
545 bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will
546 some day make this a "choice".
548 config FRAMEBUFFER_KEEP_VESA_MODE
549 prompt "Keep VESA framebuffer"
551 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
553 This option keeps the framebuffer mode set after coreboot finishes
554 execution. If this option is enabled, coreboot will pass a
555 framebuffer entry in its coreboot table and the payload will need a
556 framebuffer driver. If this option is disabled, coreboot will switch
557 back to text mode before handing control to a payload.
560 prompt "Show graphical bootsplash"
562 depends on FRAMEBUFFER_SET_VESA_MODE
564 This option shows a graphical bootsplash screen. The grapics are
565 loaded from the CBFS file bootsplash.jpg.
567 config BOOTSPLASH_FILE
568 string "Bootsplash path and filename"
569 depends on BOOTSPLASH
570 default "bootsplash.jpg"
572 The path and filename of the file to use as graphical bootsplash
573 screen. The file format has to be jpg.
578 # TODO: Better help text and detailed instructions.
580 bool "GDB debugging support"
583 If enabled, you will be able to set breakpoints for gdb debugging.
584 See src/arch/x86/lib/c_start.S for details.
586 config HAVE_DEBUG_RAM_SETUP
589 config DEBUG_RAM_SETUP
590 bool "Output verbose RAM init debug messages"
592 depends on HAVE_DEBUG_RAM_SETUP
594 This option enables additional RAM init related debug messages.
595 It is recommended to enable this when debugging issues on your
596 board which might be RAM init related.
598 Note: This option will increase the size of the coreboot image.
602 config HAVE_DEBUG_CAR
607 depends on HAVE_DEBUG_CAR
609 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
610 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
611 # printk(BIOS_DEBUG, ...) calls.
613 bool "Output verbose Cache-as-RAM debug messages"
615 depends on HAVE_DEBUG_CAR
617 This option enables additional CAR related debug messages.
621 bool "Check PIRQ table consistency"
623 depends on GENERATE_PIRQ_TABLE
627 config HAVE_DEBUG_SMBUS
631 bool "Output verbose SMBus debug messages"
633 depends on HAVE_DEBUG_SMBUS
635 This option enables additional SMBus (and SPD) debug messages.
637 Note: This option will increase the size of the coreboot image.
642 bool "Output verbose SMI debug messages"
644 depends on HAVE_SMI_HANDLER
646 This option enables additional SMI related debug messages.
648 Note: This option will increase the size of the coreboot image.
652 config DEBUG_SMM_RELOCATION
653 bool "Debug SMM relocation code"
655 depends on HAVE_SMI_HANDLER
657 This option enables additional SMM handler relocation related
660 Note: This option will increase the size of the coreboot image.
667 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
668 # printk(BIOS_DEBUG, ...) calls.
669 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
671 bool "Output verbose malloc debug messages"
674 This option enables additional malloc related debug messages.
676 Note: This option will increase the size of the coreboot image.
684 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
685 # printk(BIOS_DEBUG, ...) calls.
686 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
688 bool "Output verbose ACPI debug messages"
691 This option enables additional ACPI related debug messages.
693 Note: This option will slightly increase the size of the coreboot image.
698 config REALMODE_DEBUG
700 depends on PCI_OPTION_ROM_RUN_REALMODE
702 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
703 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
704 # printk(BIOS_DEBUG, ...) calls.
705 config REALMODE_DEBUG
706 bool "Enable debug messages for option ROM execution"
708 depends on PCI_OPTION_ROM_RUN_REALMODE
710 This option enables additional x86emu related debug messages.
712 Note: This option will increase the time to emulate a ROM.
718 bool "Output verbose x86emu debug messages"
720 depends on PCI_OPTION_ROM_RUN_YABEL
722 This option enables additional x86emu related debug messages.
724 Note: This option will increase the size of the coreboot image.
728 config X86EMU_DEBUG_JMP
729 bool "Trace JMP/RETF"
731 depends on X86EMU_DEBUG
733 Print information about JMP and RETF opcodes from x86emu.
735 Note: This option will increase the size of the coreboot image.
739 config X86EMU_DEBUG_TRACE
740 bool "Trace all opcodes"
742 depends on X86EMU_DEBUG
744 Print _all_ opcodes that are executed by x86emu.
746 WARNING: This will produce a LOT of output and take a long time.
748 Note: This option will increase the size of the coreboot image.
752 config X86EMU_DEBUG_PNP
753 bool "Log Plug&Play accesses"
755 depends on X86EMU_DEBUG
757 Print Plug And Play accesses made by option ROMs.
759 Note: This option will increase the size of the coreboot image.
763 config X86EMU_DEBUG_DISK
766 depends on X86EMU_DEBUG
768 Print Disk I/O related messages.
770 Note: This option will increase the size of the coreboot image.
774 config X86EMU_DEBUG_PMM
777 depends on X86EMU_DEBUG
779 Print messages related to POST Memory Manager (PMM).
781 Note: This option will increase the size of the coreboot image.
786 config X86EMU_DEBUG_VBE
787 bool "Debug VESA BIOS Extensions"
789 depends on X86EMU_DEBUG
791 Print messages related to VESA BIOS Extension (VBE) functions.
793 Note: This option will increase the size of the coreboot image.
797 config X86EMU_DEBUG_INT10
798 bool "Redirect INT10 output to console"
800 depends on X86EMU_DEBUG
802 Let INT10 (i.e. character output) calls print messages to debug output.
804 Note: This option will increase the size of the coreboot image.
808 config X86EMU_DEBUG_INTERRUPTS
809 bool "Log intXX calls"
811 depends on X86EMU_DEBUG
813 Print messages related to interrupt handling.
815 Note: This option will increase the size of the coreboot image.
819 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
820 bool "Log special memory accesses"
822 depends on X86EMU_DEBUG
824 Print messages related to accesses to certain areas of the virtual
825 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
827 Note: This option will increase the size of the coreboot image.
831 config X86EMU_DEBUG_MEM
832 bool "Log all memory accesses"
834 depends on X86EMU_DEBUG
836 Print memory accesses made by option ROM.
837 Note: This also includes accesses to fetch instructions.
839 Note: This option will increase the size of the coreboot image.
843 config X86EMU_DEBUG_IO
844 bool "Log IO accesses"
846 depends on X86EMU_DEBUG
848 Print I/O accesses made by option ROM.
850 Note: This option will increase the size of the coreboot image.
855 bool "Built-in low-level shell"
858 If enabled, you will have a low level shell to examine your machine.
859 Put llshell() in your (romstage) code to start the shell.
860 See src/arch/x86/llshell/llshell.inc for details.
863 bool "Trace function calls"
866 If enabled, every function will print information to console once
867 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
868 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
869 of calling function. Please note some printk releated functions
870 are omitted from trace to have good looking console dumps.
873 config LIFT_BSP_APIC_ID
877 # These probably belong somewhere else, but they are needed somewhere.
878 config AP_CODE_IN_CAR
882 config RAMINIT_SYSINFO
886 config ENABLE_APIC_EXT_ID
890 config WARNINGS_ARE_ERRORS
894 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
895 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
896 # mutually exclusive. One of these options must be selected in the
897 # mainboard Kconfig if the chipset supports enabling and disabling of
898 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
899 # in mainboard/Kconfig to know if the button should be enabled or not.
901 config POWER_BUTTON_DEFAULT_ENABLE
904 Select when the board has a power button which can optionally be
905 disabled by the user.
907 config POWER_BUTTON_DEFAULT_DISABLE
910 Select when the board has a power button which can optionally be
911 enabled by the user, e.g. when the board ships with a jumper over
912 the power switch contacts.
914 config POWER_BUTTON_FORCE_ENABLE
917 Select when the board requires that the power button is always
920 config POWER_BUTTON_FORCE_DISABLE
923 Select when the board requires that the power button is always
924 disabled, e.g. when it has been hardwired to ground.
926 config POWER_BUTTON_IS_OPTIONAL
928 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
929 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
931 Internal option that controls ENABLE_POWER_BUTTON visibility.
933 source src/Kconfig.deprecated_options