2 * This file is part of the libpayload project.
4 * Copyright (C) 2010 coresystems GmbH
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 /* we implement at least this version */
34 #define PCI_LIB_VERSION 0x020200
38 #define PCI_CLASS_DEVICE REG_CLASS_DEV
39 #define PCI_SUBSYSTEM_VENDOR_ID REG_SUBSYS_VENDOR_ID
40 #define PCI_SUBSYSTEM_ID REG_SUBSYS_ID
42 #define PCI_COMMAND REG_COMMAND
43 #define PCI_COMMAND_IO REG_COMMAND_IO
44 #define PCI_COMMAND_MEMORY REG_COMMAND_MEM
45 #define PCI_COMMAND_MASTER REG_COMMAND_BM
47 #define PCI_HEADER_TYPE REG_HEADER_TYPE
48 #define PCI_HEADER_TYPE_NORMAL HEADER_TYPE_NORMAL
49 #define PCI_HEADER_TYPE_BRIDGE HEADER_TYPE_BRIDGE
50 #define PCI_HEADER_TYPE_CARDBUS HEADER_TYPE_CARDBUS
52 #define PCI_BASE_ADDRESS_0 0x10
53 #define PCI_BASE_ADDRESS_1 0x14
54 #define PCI_BASE_ADDRESS_2 0x18
55 #define PCI_BASE_ADDRESS_3 0x1c
56 #define PCI_BASE_ADDRESS_4 0x20
57 #define PCI_BASE_ADDRESS_5 0x24
58 #define PCI_BASE_ADDRESS_SPACE 1 // mask
59 #define PCI_BASE_ADDRESS_SPACE_IO 1
60 #define PCI_BASE_ADDRESS_SPACE_MEM 0
61 #define PCI_BASE_ADDRESS_IO_MASK ~0xf
62 #define PCI_BASE_ADDRESS_MEM_MASK ~0x3
64 #define PCI_ROM_ADDRESS 0x30
65 #define PCI_ROM_ADDRESS1 0x38 // on bridges
66 #define PCI_ROM_ADDRESS_MASK ~0x7ff
68 #define PCI_VENDOR_ID_INTEL 0x8086
73 u16 vendor_id, device_id;
78 * values to match devices against.
79 * "-1" means "don't care", everything else requires an exact match
82 int domain, bus, dev, func;
84 struct pci_dev *devices;
88 struct pci_dev *devices;
91 u8 pci_read_byte(struct pci_dev *dev, int pos);
92 u16 pci_read_word(struct pci_dev *dev, int pos);
93 u32 pci_read_long(struct pci_dev *dev, int pos);
95 int pci_write_byte(struct pci_dev *dev, int pos, u8 data);
96 int pci_write_word(struct pci_dev *dev, int pos, u16 data);
97 int pci_write_long(struct pci_dev *dev, int pos, u32 data);
99 struct pci_access *pci_alloc(void);
100 void pci_init(struct pci_access*);
101 void pci_cleanup(struct pci_access*);
102 char *pci_filter_parse_slot(struct pci_filter*, const char*);
103 int pci_filter_match(struct pci_filter*, struct pci_dev*);
104 void pci_filter_init(struct pci_access*, struct pci_filter*);
105 void pci_scan_bus(struct pci_access*);
106 struct pci_dev *pci_get_dev(struct pci_access*, u16, u8, u8, u8);