2 * This file is part of the libpayload project.
4 * Copyright (C) 2008-2010 coresystems GmbH
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #include <arch/virtual.h>
36 static void uhci_start (hci_t *controller);
37 static void uhci_stop (hci_t *controller);
38 static void uhci_reset (hci_t *controller);
39 static void uhci_shutdown (hci_t *controller);
40 static int uhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize);
41 static int uhci_control (usbdev_t *dev, pid_t dir, int drlen, void *devreq,
43 static void* uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming);
44 static void uhci_destroy_intr_queue (endpoint_t *ep, void *queue);
45 static u8* uhci_poll_intr_queue (void *queue);
50 uhci_dump (hci_t *controller)
52 printf ("dump:\nUSBCMD: %x\n", uhci_reg_read16 (controller, USBCMD));
53 printf ("USBSTS: %x\n", uhci_reg_read16 (controller, USBSTS));
54 printf ("USBINTR: %x\n", uhci_reg_read16 (controller, USBINTR));
55 printf ("FRNUM: %x\n", uhci_reg_read16 (controller, FRNUM));
56 printf ("FLBASEADD: %x\n", uhci_reg_read32 (controller, FLBASEADD));
57 printf ("SOFMOD: %x\n", uhci_reg_read8 (controller, SOFMOD));
58 printf ("PORTSC1: %x\n", uhci_reg_read16 (controller, PORTSC1));
59 printf ("PORTSC2: %x\n", uhci_reg_read16 (controller, PORTSC2));
79 sprintf(td_value, "%x", td->pid);
82 printf ("%s packet (at %lx) to %x.%x failed\n", td_type,
83 virt_to_phys (td), td->dev_addr, td->endp);
84 printf ("td (counter at %x) returns: ", td->counter);
85 printf (" bitstuff err: %x, ", td->status_bitstuff_err);
86 printf (" CRC err: %x, ", td->status_crc_err);
87 printf (" NAK rcvd: %x, ", td->status_nakrcvd);
88 printf (" Babble: %x, ", td->status_babble);
89 printf (" Data Buffer err: %x, ", td->status_databuf_err);
90 printf (" Stalled: %x, ", td->status_stalled);
91 printf (" Active: %x\n", td->status_active);
92 if (td->status_babble)
93 printf (" Babble because of %s\n",
94 td->status_bitstuff_err ? "host" : "device");
95 if (td->status_active)
96 printf (" still active - timeout?\n");
100 uhci_reset (hci_t *controller)
103 uhci_reg_write16 (controller, USBCMD, 4);
105 uhci_reg_write16 (controller, USBCMD, 0);
107 uhci_reg_write16 (controller, USBCMD, 2);
108 while ((uhci_reg_read16 (controller, USBCMD) & 2) != 0)
111 uhci_reg_write32 (controller, FLBASEADD,
112 (u32) virt_to_phys (UHCI_INST (controller)->
114 //printf ("framelist at %p\n",UHCI_INST(controller)->framelistptr);
117 uhci_reg_write16 (controller, USBINTR, 0);
119 /* reset framelist index */
120 uhci_reg_write16 (controller, FRNUM, 0);
122 uhci_reg_mask16 (controller, USBCMD, ~0, 0xc0); // max packets, configure flag
124 uhci_start (controller);
128 uhci_init (pcidev_t addr)
133 hci_t *controller = new_controller ();
136 usb_fatal("Could not create USB controller instance.\n");
138 controller->instance = malloc (sizeof (uhci_t));
139 if(!controller->instance)
140 usb_fatal("Not enough memory creating USB controller instance.\n");
142 controller->start = uhci_start;
143 controller->stop = uhci_stop;
144 controller->reset = uhci_reset;
145 controller->shutdown = uhci_shutdown;
146 controller->bulk = uhci_bulk;
147 controller->control = uhci_control;
148 controller->create_intr_queue = uhci_create_intr_queue;
149 controller->destroy_intr_queue = uhci_destroy_intr_queue;
150 controller->poll_intr_queue = uhci_poll_intr_queue;
151 for (i = 0; i < 128; i++) {
152 controller->devices[i] = 0;
154 init_device_entry (controller, 0);
155 UHCI_INST (controller)->roothub = controller->devices[0];
157 controller->bus_address = addr;
158 controller->reg_base = pci_read_config32 (controller->bus_address, 0x20) & ~1; /* ~1 clears the register type indicator that is set to 1 for IO space */
160 /* kill legacy support handler */
161 uhci_stop (controller);
163 uhci_reg_write16 (controller, USBSTS, 0x3f);
164 reg16 = pci_read_config16(controller->bus_address, 0xc0);
166 pci_write_config16 (controller->bus_address, 0xc0, reg16);
168 UHCI_INST (controller)->framelistptr = memalign (0x1000, 1024 * sizeof (flistp_t *)); /* 4kb aligned to 4kb */
169 if (! UHCI_INST (controller)->framelistptr)
170 usb_fatal("Not enough memory for USB frame list pointer.\n");
172 memset (UHCI_INST (controller)->framelistptr, 0,
173 1024 * sizeof (flistp_t));
175 /* According to the *BSD UHCI code, this one is needed on some
176 PIIX chips, because otherwise they misbehave. It must be
177 added to the last chain.
179 FIXME: this leaks, if the driver should ever be reinited
180 for some reason. Not a problem now.
182 td_t *antiberserk = memalign(16, sizeof(td_t));
184 usb_fatal("Not enough memory for chipset workaround.\n");
185 memset(antiberserk, 0, sizeof(td_t));
187 UHCI_INST (controller)->qh_prei = memalign (16, sizeof (qh_t));
188 UHCI_INST (controller)->qh_intr = memalign (16, sizeof (qh_t));
189 UHCI_INST (controller)->qh_data = memalign (16, sizeof (qh_t));
190 UHCI_INST (controller)->qh_last = memalign (16, sizeof (qh_t));
192 if (! UHCI_INST (controller)->qh_prei ||
193 ! UHCI_INST (controller)->qh_intr ||
194 ! UHCI_INST (controller)->qh_data ||
195 ! UHCI_INST (controller)->qh_last)
196 usb_fatal ("Not enough memory for USB controller queues.\n");
198 UHCI_INST (controller)->qh_prei->headlinkptr.ptr =
199 virt_to_phys (UHCI_INST (controller)->qh_intr);
200 UHCI_INST (controller)->qh_prei->headlinkptr.queue_head = 1;
201 UHCI_INST (controller)->qh_prei->elementlinkptr.ptr = 0;
202 UHCI_INST (controller)->qh_prei->elementlinkptr.terminate = 1;
204 UHCI_INST (controller)->qh_intr->headlinkptr.ptr =
205 virt_to_phys (UHCI_INST (controller)->qh_data);
206 UHCI_INST (controller)->qh_intr->headlinkptr.queue_head = 1;
207 UHCI_INST (controller)->qh_intr->elementlinkptr.ptr = 0;
208 UHCI_INST (controller)->qh_intr->elementlinkptr.terminate = 1;
210 UHCI_INST (controller)->qh_data->headlinkptr.ptr =
211 virt_to_phys (UHCI_INST (controller)->qh_last);
212 UHCI_INST (controller)->qh_data->headlinkptr.queue_head = 1;
213 UHCI_INST (controller)->qh_data->elementlinkptr.ptr = 0;
214 UHCI_INST (controller)->qh_data->elementlinkptr.terminate = 1;
216 UHCI_INST (controller)->qh_last->headlinkptr.ptr = virt_to_phys (UHCI_INST (controller)->qh_data);
217 UHCI_INST (controller)->qh_last->headlinkptr.terminate = 1;
218 UHCI_INST (controller)->qh_last->elementlinkptr.ptr = virt_to_phys (antiberserk);
219 UHCI_INST (controller)->qh_last->elementlinkptr.terminate = 1;
221 for (i = 0; i < 1024; i++) {
222 UHCI_INST (controller)->framelistptr[i].ptr =
223 virt_to_phys (UHCI_INST (controller)->qh_prei);
224 UHCI_INST (controller)->framelistptr[i].terminate = 0;
225 UHCI_INST (controller)->framelistptr[i].queue_head = 1;
227 controller->devices[0]->controller = controller;
228 controller->devices[0]->init = uhci_rh_init;
229 controller->devices[0]->init (controller->devices[0]);
230 uhci_reset (controller);
235 uhci_shutdown (hci_t *controller)
239 detach_controller (controller);
240 UHCI_INST (controller)->roothub->destroy (UHCI_INST (controller)->
242 uhci_reg_mask16 (controller, USBCMD, 0, 0); // stop work
243 free (UHCI_INST (controller)->framelistptr);
244 free (UHCI_INST (controller)->qh_prei);
245 free (UHCI_INST (controller)->qh_intr);
246 free (UHCI_INST (controller)->qh_data);
247 free (UHCI_INST (controller)->qh_last);
248 free (UHCI_INST (controller));
253 uhci_start (hci_t *controller)
255 uhci_reg_mask16 (controller, USBCMD, ~0, 1); // start work on schedule
259 uhci_stop (hci_t *controller)
261 uhci_reg_mask16 (controller, USBCMD, ~1, 0); // stop work on schedule
264 #define GET_TD(x) ((void*)(((unsigned int)(x))&~0xf))
267 wait_for_completed_qh (hci_t *controller, qh_t *qh)
269 int timeout = 1000000; /* max 30 ms. */
270 void *current = GET_TD (qh->elementlinkptr.ptr);
271 while ((qh->elementlinkptr.terminate == 0) && (timeout-- > 0)) {
272 if (current != GET_TD (qh->elementlinkptr.ptr)) {
273 current = GET_TD (qh->elementlinkptr.ptr);
276 uhci_reg_mask16 (controller, USBSTS, ~0, 0); // clear resettable registers
279 return (GET_TD (qh->elementlinkptr.ptr) ==
280 0) ? 0 : GET_TD (phys_to_virt (qh->elementlinkptr.ptr));
286 return (size - 1) & 0x7ff;
299 uhci_control (usbdev_t *dev, pid_t dir, int drlen, void *devreq, int dalen,
302 int endp = 0; /* this is control: always 0 */
303 int mlen = dev->endpoints[0].maxpacketsize;
304 int count = (2 + (dalen + mlen - 1) / mlen);
305 unsigned short req = ((unsigned short *) devreq)[0];
307 td_t *tds = memalign (16, sizeof (td_t) * count);
308 memset (tds, 0, sizeof (td_t) * count);
309 count--; /* to compensate for 0-indexed array */
310 for (i = 0; i < count; i++) {
311 tds[i].ptr = virt_to_phys (&tds[i + 1]);
312 tds[i].depth_first = 1;
313 tds[i].terminate = 0;
316 tds[count].depth_first = 1;
317 tds[count].terminate = 1;
320 tds[0].dev_addr = dev->address;
322 tds[0].maxlen = maxlen (drlen);
324 tds[0].data_toggle = 0;
325 tds[0].lowspeed = dev->speed;
326 tds[0].bufptr = virt_to_phys (devreq);
327 tds[0].status_active = 1;
330 for (i = 1; i < count; i++) {
332 tds[i].dev_addr = dev->address;
334 tds[i].maxlen = maxlen (min (mlen, dalen));
336 tds[i].data_toggle = toggle;
337 tds[i].lowspeed = dev->speed;
338 tds[i].bufptr = virt_to_phys (data);
339 tds[i].status_active = 1;
345 tds[count].pid = (dir == OUT) ? IN : OUT;
346 tds[count].dev_addr = dev->address;
347 tds[count].endp = endp;
348 tds[count].maxlen = maxlen (0);
349 tds[count].counter = 0; /* as per linux 2.4.10 */
350 tds[count].data_toggle = 1;
351 tds[count].lowspeed = dev->speed;
352 tds[count].bufptr = 0;
353 tds[count].status_active = 1;
354 UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
356 UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
357 UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
358 td_t *td = wait_for_completed_qh (dev->controller,
359 UHCI_INST (dev->controller)->
365 printf ("control packet, req %x\n", req);
374 create_schedule (int numpackets)
378 td_t *tds = memalign (16, sizeof (td_t) * numpackets);
379 memset (tds, 0, sizeof (td_t) * numpackets);
381 for (i = 0; i < numpackets; i++) {
382 tds[i].ptr = virt_to_phys (&tds[i + 1]);
383 tds[i].terminate = 0;
384 tds[i].queue_head = 0;
385 tds[i].depth_first = 1;
387 tds[numpackets - 1].ptr = 0;
388 tds[numpackets - 1].terminate = 1;
389 tds[numpackets - 1].queue_head = 0;
390 tds[numpackets - 1].depth_first = 0;
395 fill_schedule (td_t *td, endpoint_t *ep, int length, unsigned char *data,
398 td->pid = ep->direction;
399 td->dev_addr = ep->dev->address;
400 td->endp = ep->endpoint & 0xf;
401 td->maxlen = maxlen (length);
402 if (ep->direction == SETUP)
406 td->data_toggle = *toggle & 1;
407 td->lowspeed = ep->dev->speed;
408 td->bufptr = virt_to_phys (data);
410 td->status_active = 1;
415 run_schedule (usbdev_t *dev, td_t *td)
417 UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
419 UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
420 UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
421 td = wait_for_completed_qh (dev->controller,
422 UHCI_INST (dev->controller)->qh_data);
431 /* finalize == 1: if data is of packet aligned size, add a zero length packet */
433 uhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize)
435 int maxpsize = ep->maxpacketsize;
437 usb_fatal ("MaxPacketSize == 0!!!");
438 int numpackets = (size + maxpsize - 1 + finalize) / maxpsize;
441 td_t *tds = create_schedule (numpackets);
442 int i = 0, toggle = ep->toggle;
443 while ((size > 0) || ((size == 0) && (finalize != 0))) {
444 fill_schedule (&tds[i], ep, min (size, maxpsize), data,
450 if (run_schedule (ep->dev, tds) == 1) {
451 debug("Stalled. Trying to clean up.\n");
471 /* create and hook-up an intr queue into device schedule */
473 uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming)
475 u8 *data = malloc(reqsize*reqcount);
476 td_t *tds = memalign(16, sizeof(td_t) * reqcount);
477 qh_t *qh = memalign(16, sizeof(qh_t));
479 if (!data || !tds || !qh)
480 usb_fatal ("Not enough memory to create USB intr queue prerequisites.\n");
482 qh->elementlinkptr.ptr = virt_to_phys(tds);
483 qh->elementlinkptr.queue_head = 0;
484 qh->elementlinkptr.terminate = 0;
486 intr_q *q = malloc(sizeof(intr_q));
488 usb_fatal ("Not enough memory to create USB intr queue.\n");
494 q->reqsize = reqsize;
495 q->last_td = &tds[reqcount - 1];
497 memset (tds, 0, sizeof (td_t) * reqcount);
499 for (i = 0; i < reqcount; i++) {
500 tds[i].ptr = virt_to_phys (&tds[i + 1]);
501 tds[i].terminate = 0;
502 tds[i].queue_head = 0;
503 tds[i].depth_first = 0;
505 tds[i].pid = ep->direction;
506 tds[i].dev_addr = ep->dev->address;
507 tds[i].endp = ep->endpoint & 0xf;
508 tds[i].maxlen = maxlen (reqsize);
510 tds[i].data_toggle = ep->toggle & 1;
511 tds[i].lowspeed = ep->dev->speed;
512 tds[i].bufptr = virt_to_phys (data);
513 tds[i].status_active = 1;
517 tds[reqcount - 1].ptr = 0;
518 tds[reqcount - 1].terminate = 1;
519 tds[reqcount - 1].queue_head = 0;
520 tds[reqcount - 1].depth_first = 0;
521 for (i = reqtiming; i < 1024; i += reqtiming) {
522 /* FIXME: wrap in another qh, one for each occurance of the qh in the framelist */
523 qh->headlinkptr.ptr = UHCI_INST (ep->dev->controller)->framelistptr[i].ptr;
524 qh->headlinkptr.terminate = 0;
525 UHCI_INST (ep->dev->controller)->framelistptr[i].ptr = virt_to_phys(qh);
526 UHCI_INST (ep->dev->controller)->framelistptr[i].terminate = 0;
527 UHCI_INST (ep->dev->controller)->framelistptr[i].queue_head = 1;
532 /* remove queue from device schedule, dropping all data that came in */
534 uhci_destroy_intr_queue (endpoint_t *ep, void *q_)
536 intr_q *q = (intr_q*)q_;
537 u32 val = virt_to_phys (q->qh);
538 u32 end = virt_to_phys (UHCI_INST (ep->dev->controller)->qh_intr);
540 for (i=0; i<1024; i++) {
542 u32 ptr = UHCI_INST (ep->dev->controller)->framelistptr[i].ptr;
544 if (((qh_t*)phys_to_virt(ptr))->elementlinkptr.ptr == val) {
545 ((qh_t*)phys_to_virt(oldptr))->headlinkptr.ptr = ((qh_t*)phys_to_virt(ptr))->headlinkptr.ptr;
546 free(phys_to_virt(ptr));
550 ptr = ((qh_t*)phys_to_virt(ptr))->headlinkptr.ptr;
559 /* read one intr-packet from queue, if available. extend the queue for new input.
560 return NULL if nothing new available.
561 Recommended use: while (data=poll_intr_queue(q)) process(data);
564 uhci_poll_intr_queue (void *q_)
566 intr_q *q = (intr_q*)q_;
567 if (q->tds[q->lastread].status_active == 0) {
568 /* FIXME: handle errors */
569 int current = q->lastread;
571 if (q->lastread == 0) {
572 previous = q->total - 1;
574 previous = q->lastread - 1;
576 q->tds[previous].status = 0;
577 q->tds[previous].ptr = 0;
578 q->tds[previous].terminate = 1;
579 if (q->last_td != &q->tds[previous]) {
580 q->last_td->ptr = virt_to_phys(&q->tds[previous]);
581 q->last_td->terminate = 0;
582 q->last_td = &q->tds[previous];
584 q->tds[previous].status_active = 1;
585 q->lastread = (q->lastread + 1) % q->total;
586 return &q->data[current*q->reqsize];
592 uhci_reg_write32 (hci_t *ctrl, usbreg reg, u32 value)
594 outl (value, ctrl->reg_base + reg);
598 uhci_reg_read32 (hci_t *ctrl, usbreg reg)
600 return inl (ctrl->reg_base + reg);
604 uhci_reg_write16 (hci_t *ctrl, usbreg reg, u16 value)
606 outw (value, ctrl->reg_base + reg);
610 uhci_reg_read16 (hci_t *ctrl, usbreg reg)
612 return inw (ctrl->reg_base + reg);
616 uhci_reg_write8 (hci_t *ctrl, usbreg reg, u8 value)
618 outb (value, ctrl->reg_base + reg);
622 uhci_reg_read8 (hci_t *ctrl, usbreg reg)
624 return inb (ctrl->reg_base + reg);
628 uhci_reg_mask32 (hci_t *ctrl, usbreg reg, u32 andmask, u32 ormask)
630 uhci_reg_write32 (ctrl, reg,
631 (uhci_reg_read32 (ctrl, reg) & andmask) | ormask);
635 uhci_reg_mask16 (hci_t *ctrl, usbreg reg, u16 andmask, u16 ormask)
637 uhci_reg_write16 (ctrl, reg,
638 (uhci_reg_read16 (ctrl, reg) & andmask) | ormask);
642 uhci_reg_mask8 (hci_t *ctrl, usbreg reg, u8 andmask, u8 ormask)
644 uhci_reg_write8 (ctrl, reg,
645 (uhci_reg_read8 (ctrl, reg) & andmask) | ormask);