2 * This file is part of the libpayload project.
4 * Copyright (C) 2008 coresystems GmbH
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <arch/virtual.h>
34 static void uhci_start (hci_t *controller);
35 static void uhci_stop (hci_t *controller);
36 static void uhci_reset (hci_t *controller);
37 static void uhci_shutdown (hci_t *controller);
38 static int uhci_packet (usbdev_t *dev, int endp, int pid, int toggle,
39 int length, u8 *data);
40 static int uhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize);
41 static int uhci_control (usbdev_t *dev, pid_t dir, int drlen, void *devreq,
43 static void* uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming);
44 static void uhci_destroy_intr_queue (endpoint_t *ep, void *queue);
45 static u8* uhci_poll_intr_queue (void *queue);
50 uhci_dump (hci_t *controller)
52 printf ("dump:\nUSBCMD: %x\n", uhci_reg_read16 (controller, USBCMD));
53 printf ("USBSTS: %x\n", uhci_reg_read16 (controller, USBSTS));
54 printf ("USBINTR: %x\n", uhci_reg_read16 (controller, USBINTR));
55 printf ("FRNUM: %x\n", uhci_reg_read16 (controller, FRNUM));
56 printf ("FLBASEADD: %x\n", uhci_reg_read32 (controller, FLBASEADD));
57 printf ("SOFMOD: %x\n", uhci_reg_read8 (controller, SOFMOD));
58 printf ("PORTSC1: %x\n", uhci_reg_read16 (controller, PORTSC1));
59 printf ("PORTSC2: %x\n", uhci_reg_read16 (controller, PORTSC2));
66 printf ("%x packet (at %lx) to %x.%x failed\n", td->pid,
67 virt_to_phys (td), td->dev_addr, td->endp);
68 printf ("td (counter at %x) returns: ", td->counter);
69 printf (" bitstuff err: %x, ", td->status_bitstuff_err);
70 printf (" CRC err: %x, ", td->status_crc_err);
71 printf (" NAK rcvd: %x, ", td->status_nakrcvd);
72 printf (" Babble: %x, ", td->status_babble);
73 printf (" Data Buffer err: %x, ", td->status_databuf_err);
74 printf (" Stalled: %x, ", td->status_stalled);
75 printf (" Active: %x\n", td->status_active);
76 if (td->status_babble)
77 printf (" Babble because of %s\n",
78 td->status_bitstuff_err ? "host" : "device");
79 if (td->status_active)
80 printf (" still active - timeout?\n");
84 uhci_reset (hci_t *controller)
87 uhci_reg_write16 (controller, USBCMD, 4);
89 uhci_reg_write16 (controller, USBCMD, 0);
91 uhci_reg_write16 (controller, USBCMD, 2);
92 while ((uhci_reg_read16 (controller, USBCMD) & 2) != 0)
95 uhci_reg_write32 (controller, FLBASEADD,
96 (u32) virt_to_phys (UHCI_INST (controller)->
98 //printf ("framelist at %p\n",UHCI_INST(controller)->framelistptr);
101 uhci_reg_write16 (controller, USBINTR, 0);
103 /* reset framelist index */
104 uhci_reg_write16 (controller, FRNUM, 0);
106 uhci_reg_mask16 (controller, USBCMD, ~0, 0xc0); // max packets, configure flag
108 uhci_start (controller);
112 uhci_init (pcidev_t addr)
115 hci_t *controller = new_controller ();
117 controller->instance = malloc (sizeof (uhci_t));
118 controller->start = uhci_start;
119 controller->stop = uhci_stop;
120 controller->reset = uhci_reset;
121 controller->shutdown = uhci_shutdown;
122 controller->packet = uhci_packet;
123 controller->bulk = uhci_bulk;
124 controller->control = uhci_control;
125 controller->create_intr_queue = uhci_create_intr_queue;
126 controller->destroy_intr_queue = uhci_destroy_intr_queue;
127 controller->poll_intr_queue = uhci_poll_intr_queue;
128 for (i = 1; i < 128; i++) {
129 controller->devices[i] = 0;
131 init_device_entry (controller, 0);
132 UHCI_INST (controller)->roothub = controller->devices[0];
134 controller->bus_address = addr;
135 controller->reg_base = pci_read_config32 (controller->bus_address, 0x20) & ~1; /* ~1 clears the register type indicator that is set to 1 for IO space */
137 /* kill legacy support handler */
138 uhci_stop (controller);
140 uhci_reg_write16 (controller, USBSTS, 0x3f);
141 pci_write_config32 (controller->bus_address, 0xc0, 0x8f00);
143 UHCI_INST (controller)->framelistptr = memalign (0x1000, 1024 * sizeof (flistp_t *)); /* 4kb aligned to 4kb */
144 memset (UHCI_INST (controller)->framelistptr, 0,
145 1024 * sizeof (flistp_t));
147 /* According to the *BSD UHCI code, this one is needed on some
148 PIIX chips, because otherwise they misbehave. It must be
149 added to the last chain.
151 FIXME: this leaks, if the driver should ever be reinited
152 for some reason. Not a problem now.
154 td_t *antiberserk = memalign(16, sizeof(td_t));
155 memset(antiberserk, 0, sizeof(td_t));
157 UHCI_INST (controller)->qh_prei = memalign (16, sizeof (qh_t));
158 UHCI_INST (controller)->qh_intr = memalign (16, sizeof (qh_t));
159 UHCI_INST (controller)->qh_data = memalign (16, sizeof (qh_t));
160 UHCI_INST (controller)->qh_last = memalign (16, sizeof (qh_t));
162 UHCI_INST (controller)->qh_prei->headlinkptr.ptr =
163 virt_to_phys (UHCI_INST (controller)->qh_intr);
164 UHCI_INST (controller)->qh_prei->headlinkptr.queue_head = 1;
165 UHCI_INST (controller)->qh_prei->elementlinkptr.ptr = 0;
166 UHCI_INST (controller)->qh_prei->elementlinkptr.terminate = 1;
168 UHCI_INST (controller)->qh_intr->headlinkptr.ptr =
169 virt_to_phys (UHCI_INST (controller)->qh_data);
170 UHCI_INST (controller)->qh_intr->headlinkptr.queue_head = 1;
171 UHCI_INST (controller)->qh_intr->elementlinkptr.ptr = 0;
172 UHCI_INST (controller)->qh_intr->elementlinkptr.terminate = 1;
174 UHCI_INST (controller)->qh_data->headlinkptr.ptr =
175 virt_to_phys (UHCI_INST (controller)->qh_last);
176 UHCI_INST (controller)->qh_data->headlinkptr.queue_head = 1;
177 UHCI_INST (controller)->qh_data->elementlinkptr.ptr = 0;
178 UHCI_INST (controller)->qh_data->elementlinkptr.terminate = 1;
180 UHCI_INST (controller)->qh_last->headlinkptr.ptr = virt_to_phys (UHCI_INST (controller)->qh_data);
181 UHCI_INST (controller)->qh_last->headlinkptr.terminate = 1;
182 UHCI_INST (controller)->qh_last->elementlinkptr.ptr = virt_to_phys (antiberserk);
183 UHCI_INST (controller)->qh_last->elementlinkptr.terminate = 1;
185 for (i = 0; i < 1024; i++) {
186 UHCI_INST (controller)->framelistptr[i].ptr =
187 virt_to_phys (UHCI_INST (controller)->qh_prei);
188 UHCI_INST (controller)->framelistptr[i].terminate = 0;
189 UHCI_INST (controller)->framelistptr[i].queue_head = 1;
191 controller->devices[0]->controller = controller;
192 controller->devices[0]->init = uhci_rh_init;
193 controller->devices[0]->init (controller->devices[0]);
194 uhci_reset (controller);
199 uhci_shutdown (hci_t *controller)
203 detach_controller (controller);
204 UHCI_INST (controller)->roothub->destroy (UHCI_INST (controller)->
206 uhci_reg_mask16 (controller, USBCMD, 0, 0); // stop work
207 free (UHCI_INST (controller)->framelistptr);
208 free (UHCI_INST (controller)->qh_prei);
209 free (UHCI_INST (controller)->qh_intr);
210 free (UHCI_INST (controller)->qh_data);
211 free (UHCI_INST (controller)->qh_last);
212 free (UHCI_INST (controller));
217 uhci_start (hci_t *controller)
219 uhci_reg_mask16 (controller, USBCMD, ~0, 1); // start work on schedule
223 uhci_stop (hci_t *controller)
225 uhci_reg_mask16 (controller, USBCMD, ~1, 0); // stop work on schedule
228 #define GET_TD(x) ((void*)(((unsigned int)(x))&~0xf))
231 wait_for_completed_qh (hci_t *controller, qh_t *qh)
233 int timeout = 1000000; /* max 30 ms. */
234 void *current = GET_TD (qh->elementlinkptr.ptr);
235 while ((qh->elementlinkptr.terminate == 0) && (timeout-- > 0)) {
236 if (current != GET_TD (qh->elementlinkptr.ptr)) {
237 current = GET_TD (qh->elementlinkptr.ptr);
240 uhci_reg_mask16 (controller, USBSTS, ~0, 0); // clear resettable registers
243 return (GET_TD (qh->elementlinkptr.ptr) ==
244 0) ? 0 : GET_TD (phys_to_virt (qh->elementlinkptr.ptr));
248 wait_for_completed_td (hci_t *controller, td_t *td)
251 while ((td->status_active == 1)
252 && ((uhci_reg_read16 (controller, USBSTS) & 2) == 0)
253 && (timeout-- > 0)) {
254 uhci_reg_mask16 (controller, USBSTS, ~0, 0); // clear resettable registers
262 return (size - 1) & 0x7ff;
275 uhci_control (usbdev_t *dev, pid_t dir, int drlen, void *devreq, int dalen,
278 int endp = 0; /* this is control: always 0 */
279 int mlen = dev->endpoints[0].maxpacketsize;
280 int count = (2 + (dalen + mlen - 1) / mlen);
281 unsigned short req = ((unsigned short *) devreq)[0];
283 td_t *tds = memalign (16, sizeof (td_t) * count);
284 memset (tds, 0, sizeof (td_t) * count);
285 count--; /* to compensate for 0-indexed array */
286 for (i = 0; i < count; i++) {
287 tds[i].ptr = virt_to_phys (&tds[i + 1]);
288 tds[i].depth_first = 1;
289 tds[i].terminate = 0;
292 tds[count].depth_first = 1;
293 tds[count].terminate = 1;
296 tds[0].dev_addr = dev->address;
298 tds[0].maxlen = maxlen (drlen);
300 tds[0].data_toggle = 0;
301 tds[0].lowspeed = dev->lowspeed;
302 tds[0].bufptr = virt_to_phys (devreq);
303 tds[0].status_active = 1;
306 for (i = 1; i < count; i++) {
308 tds[i].dev_addr = dev->address;
310 tds[i].maxlen = maxlen (min (mlen, dalen));
312 tds[i].data_toggle = toggle;
313 tds[i].lowspeed = dev->lowspeed;
314 tds[i].bufptr = virt_to_phys (data);
315 tds[i].status_active = 1;
321 tds[count].pid = (dir == OUT) ? IN : OUT;
322 tds[count].dev_addr = dev->address;
323 tds[count].endp = endp;
324 tds[count].maxlen = maxlen (0);
325 tds[count].counter = 0; /* as per linux 2.4.10 */
326 tds[count].data_toggle = 1;
327 tds[count].lowspeed = dev->lowspeed, tds[count].bufptr = 0;
328 tds[count].status_active = 1;
329 UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
331 UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
332 UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
333 td_t *td = wait_for_completed_qh (dev->controller,
334 UHCI_INST (dev->controller)->
340 printf ("control packet, req %x\n", req);
349 uhci_packet (usbdev_t *dev, int endp, int pid, int toggle, int length,
354 td = memalign (16, sizeof (td_t));
356 memset (td, 0, sizeof (td_t));
362 td->dev_addr = dev->address;
363 td->endp = endp & 0xf;
364 td->maxlen = maxlen (length);
369 td->data_toggle = toggle & 1;
370 td->lowspeed = dev->lowspeed;
371 td->bufptr = virt_to_phys (data);
373 td->status_active = 1;
375 UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
377 UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
378 UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
379 wait_for_completed_td (dev->controller, td);
380 if ((td->status & 0x7f) == 0) {
381 //printf("successfully sent a %x packet to %x.%x\n",pid, dev->address,endp);
391 create_schedule (int numpackets)
395 td_t *tds = memalign (16, sizeof (td_t) * numpackets);
396 memset (tds, 0, sizeof (td_t) * numpackets);
398 for (i = 0; i < numpackets; i++) {
399 tds[i].ptr = virt_to_phys (&tds[i + 1]);
400 tds[i].terminate = 0;
401 tds[i].queue_head = 0;
402 tds[i].depth_first = 1;
404 tds[numpackets - 1].ptr = 0;
405 tds[numpackets - 1].terminate = 1;
406 tds[numpackets - 1].queue_head = 0;
407 tds[numpackets - 1].depth_first = 0;
412 fill_schedule (td_t *td, endpoint_t *ep, int length, unsigned char *data,
415 td->pid = ep->direction;
416 td->dev_addr = ep->dev->address;
417 td->endp = ep->endpoint & 0xf;
418 td->maxlen = maxlen (length);
419 if (ep->direction == SETUP)
423 td->data_toggle = *toggle & 1;
424 td->lowspeed = ep->dev->lowspeed;
425 td->bufptr = virt_to_phys (data);
427 td->status_active = 1;
432 run_schedule (usbdev_t *dev, td_t *td)
434 UHCI_INST (dev->controller)->qh_data->elementlinkptr.ptr =
436 UHCI_INST (dev->controller)->qh_data->elementlinkptr.queue_head = 0;
437 UHCI_INST (dev->controller)->qh_data->elementlinkptr.terminate = 0;
438 td = wait_for_completed_qh (dev->controller,
439 UHCI_INST (dev->controller)->qh_data);
448 /* finalize == 1: if data is of packet aligned size, add a zero length packet */
450 uhci_bulk (endpoint_t *ep, int size, u8 *data, int finalize)
452 int maxpsize = ep->maxpacketsize;
454 fatal ("MaxPacketSize == 0!!!");
455 int numpackets = (size + maxpsize - 1 + finalize) / maxpsize;
458 td_t *tds = create_schedule (numpackets);
459 int i = 0, toggle = ep->toggle;
460 while ((size > 0) || ((size == 0) && (finalize != 0))) {
461 fill_schedule (&tds[i], ep, min (size, maxpsize), data,
467 if (run_schedule (ep->dev, tds) == 1) {
487 /* create and hook-up an intr queue into device schedule */
489 uhci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming)
491 u8 *data = malloc(reqsize*reqcount);
492 td_t *tds = memalign(16, sizeof(td_t) * reqcount);
493 qh_t *qh = memalign(16, sizeof(qh_t));
495 qh->elementlinkptr.ptr = virt_to_phys(tds);
496 qh->elementlinkptr.terminate = 0;
498 intr_q *q = malloc(sizeof(intr_q));
504 q->reqsize = reqsize;
505 q->last_td = &tds[reqcount - 1];
507 memset (tds, 0, sizeof (td_t) * reqcount);
509 for (i = 0; i < reqcount; i++) {
510 tds[i].ptr = virt_to_phys (&tds[i + 1]);
511 tds[i].terminate = 0;
512 tds[i].queue_head = 0;
513 tds[i].depth_first = 0;
515 tds[i].pid = ep->direction;
516 tds[i].dev_addr = ep->dev->address;
517 tds[i].endp = ep->endpoint & 0xf;
518 tds[i].maxlen = maxlen (reqsize);
520 tds[i].data_toggle = ep->toggle & 1;
521 tds[i].lowspeed = ep->dev->lowspeed;
522 tds[i].bufptr = virt_to_phys (data);
523 tds[i].status_active = 1;
527 tds[reqcount - 1].ptr = 0;
528 tds[reqcount - 1].terminate = 1;
529 tds[reqcount - 1].queue_head = 0;
530 tds[reqcount - 1].depth_first = 0;
531 for (i = reqtiming; i < 1024; i += reqtiming) {
532 /* FIXME: wrap in another qh, one for each occurance of the qh in the framelist */
533 qh->headlinkptr.ptr = UHCI_INST (ep->dev->controller)->framelistptr[i].ptr;
534 qh->headlinkptr.terminate = 0;
535 UHCI_INST (ep->dev->controller)->framelistptr[i].ptr = virt_to_phys(qh);
536 UHCI_INST (ep->dev->controller)->framelistptr[i].terminate = 0;
537 UHCI_INST (ep->dev->controller)->framelistptr[i].queue_head = 1;
542 /* remove queue from device schedule, dropping all data that came in */
544 uhci_destroy_intr_queue (endpoint_t *ep, void *q_)
546 intr_q *q = (intr_q*)q_;
547 u32 val = virt_to_phys (q->qh);
548 u32 end = virt_to_phys (UHCI_INST (ep->dev->controller)->qh_intr);
550 for (i=0; i<1024; i++) {
552 u32 ptr = UHCI_INST (ep->dev->controller)->framelistptr[i].ptr;
554 if (((qh_t*)phys_to_virt(ptr))->elementlinkptr.ptr == val) {
555 ((qh_t*)phys_to_virt(oldptr))->headlinkptr.ptr = ((qh_t*)phys_to_virt(ptr))->headlinkptr.ptr;
556 free(phys_to_virt(ptr));
560 ptr = ((qh_t*)phys_to_virt(ptr))->headlinkptr.ptr;
569 /* read one intr-packet from queue, if available. extend the queue for new input.
570 return NULL if nothing new available.
571 Recommended use: while (data=poll_intr_queue(q)) process(data);
574 uhci_poll_intr_queue (void *q_)
576 intr_q *q = (intr_q*)q_;
577 if (q->tds[q->lastread].status_active == 0) {
578 /* FIXME: handle errors */
579 int current = q->lastread;
581 if (q->lastread == 0) {
582 previous = q->total - 1;
584 previous = q->lastread - 1;
586 q->tds[previous].status = 0;
587 q->tds[previous].ptr = 0;
588 q->tds[previous].terminate = 1;
589 if (q->last_td != &q->tds[previous]) {
590 q->last_td->ptr = virt_to_phys(&q->tds[previous]);
591 q->last_td->terminate = 0;
592 q->last_td = &q->tds[previous];
594 q->tds[previous].status_active = 1;
595 q->lastread = (q->lastread + 1) % q->total;
596 return &q->data[current*q->reqsize];
602 uhci_reg_write32 (hci_t *ctrl, usbreg reg, u32 value)
604 outl (value, ctrl->reg_base + reg);
608 uhci_reg_read32 (hci_t *ctrl, usbreg reg)
610 return inl (ctrl->reg_base + reg);
614 uhci_reg_write16 (hci_t *ctrl, usbreg reg, u16 value)
616 outw (value, ctrl->reg_base + reg);
620 uhci_reg_read16 (hci_t *ctrl, usbreg reg)
622 return inw (ctrl->reg_base + reg);
626 uhci_reg_write8 (hci_t *ctrl, usbreg reg, u8 value)
628 outb (value, ctrl->reg_base + reg);
632 uhci_reg_read8 (hci_t *ctrl, usbreg reg)
634 return inb (ctrl->reg_base + reg);
638 uhci_reg_mask32 (hci_t *ctrl, usbreg reg, u32 andmask, u32 ormask)
640 uhci_reg_write32 (ctrl, reg,
641 (uhci_reg_read32 (ctrl, reg) & andmask) | ormask);
645 uhci_reg_mask16 (hci_t *ctrl, usbreg reg, u16 andmask, u16 ormask)
647 uhci_reg_write16 (ctrl, reg,
648 (uhci_reg_read16 (ctrl, reg) & andmask) | ormask);
652 uhci_reg_mask8 (hci_t *ctrl, usbreg reg, u8 andmask, u8 ormask)
654 uhci_reg_write8 (ctrl, reg,
655 (uhci_reg_read8 (ctrl, reg) & andmask) | ormask);