.

diff --git a/2012-02-08_14:04_coreboot.log b/2012-02-08_14:04_coreboot.log
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diff --git a/2012-02-08_14:12_coreboot.log b/2012-02-08_14:12_coreboot.log
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diff --git a/2012-02-08_14:18_coreboot.log b/2012-02-08_14:18_coreboot.log
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diff --git a/2012-02-08_14:21_coreboot.log b/2012-02-08_14:21_coreboot.log
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diff --git a/2012-02-08_14:22_coreboot.log b/2012-02-08_14:22_coreboot.log
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diff --git a/2012-02-08_14:27_coreboot.log b/2012-02-08_14:27_coreboot.log
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diff --git a/2012-02-08_14:30_coreboot.log b/2012-02-08_14:30_coreboot.log
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diff --git a/2012-02-08_14:33_coreboot.log b/2012-02-08_14:33_coreboot.log
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diff --git a/2012-02-08_14:38_coreboot.log b/2012-02-08_14:38_coreboot.log
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diff --git a/2012-02-08_14:45_coreboot.log b/2012-02-08_14:45_coreboot.log
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diff --git a/2012-02-08_14:49_coreboot.log b/2012-02-08_14:49_coreboot.log
new file mode 100644 (file)
index 0000000..6f25147
--- /dev/null
+++ b/2012-02-08_14:49_coreboot.log
@@ -0,0 +1,863 @@
+½\81\81\81\81\81ÁÁÁÁÁ\85\85\85\85\85ÑÑÑÑÑ\8d\8d\8d\8d\8d¡¡¡¡¡\81\81\81\81\81¥¥¥¥¥\91\91\91\91\91\81\81\81\81\81õõõõõ\81\81\81\81\81ÁÁÁÁÁáááááÁÁÁÁÁÅÅÅÅÅÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ\89\89\89\89\89\99\99\99\99\99\81\81\81\81\81\81\81\81\81\81ÍÍÍÍÍÕÕÕÕÕ\8d\8d\8d\8d\8d\8d\8d\8d\8d\8d\95\95\95\95\95ÍÍÍÍÍÍÍÍÍÍ55555)))))55555)))))ÿsccctpppccppauuuSSuurSeeeSSteettteAttdAAMMAA\rM
+DDDMMDMMMDSMMSSRRSSRR   R  * AP     0 ddd3ddooooonnnnneeeee\r\r\r\r\r
+
+
+
+
+stiiiinnnianriiiinittttt__te__ffff_d\riiiifdi
+dddvvdvviiiividddd_d___aaa_appppap((((ss(sstttstaaaatgagggeegee111e11)))) )   aa aappppapiiiiciccciiiciddddid::::  :  000 041230\r5\r\r\r
+
+\r
+
+
+FFFF*FIIIII ADDDDDVVPVVVIIII IDDDDD0 4    ooooonnnnn     AAAAAPPPPP:::::     0000051234\r\r\r\r\r
+
+
+
+
+started\r
+* AP 05started\r
+\r
+POST: 0x38\r
+rs780_early_setup()\r
+fam10_optimization()\r
+rs780_por_init\r
+\r
+Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440 \r
+POST: 0x39\r
+FIDVID on BSP, APIC_id: 00\r
+BSP fid = 0\r
+Wait for AP stage 1: ap_apicid = 1\r
+       readback = 1000001\r
+       common_fid(packed) = 0\r
+Wait for AP stage 1: ap_apicid = 2\r
+       readback = 2000001\r
+       common_fid(packed) = 0\r
+Wait for AP stage 1: ap_apicid = 3\r
+       readback = 3000001\r
+       common_fid(packed) = 0\r
+Wait for AP stage 1: ap_apicid = 4\r
+       readback = 4000001\r
+       common_fid(packed) = 0\r
+Wait for AP stage 1: ap_apicid = 5\r
+       readback = 5000001\r
+       common_fid(packed) = 0\r
+common_fid = 0\r
+POST: 0x3a\r
+End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440 \r
+rs780_htinit cpu_ht_freq=b.\r
+rs780_htinit: HT3 mode\r
+...WARM RESET...\r
+\r
+\r
+\r
+\r
+coreboot-4.0-2026-g15127e2-dirty Wed Feb  8 14:48:08 CET 2012 starting...\r
+\r
+BSP Family_Model: 00100fa0 \r
+*sysinfo range: [000cc000,000cf360]\r
+bsp_apicid = 00 \r
+cpu_init_detectedx = 00000000 \r
+microcode: equivalent rev id  = 0x10a0, current patch id = 0x00000000\r
+microcode: patch id to apply = 0x010000bf\r
+microcode: updated to patch id = 0x010000bf  success\r
+\r
+POST: 0x33\r
+cpuSetAMDMSR  done\r
+POST: 0x34\r
+Enter amd_ht_init()\r
+Exit amd_ht_init()\r
+POST: 0x35\r
+SB900 - Early.c - get_sbdn - Start.\r
+SB900 - Early.c - get_sbdn - End.\r
+cpuSetAMDPCI 00 done\r
+Prep FID/VID Node:00 \r
+P-state info in MSRC001_0064 is invalid !!!\r
+P-state info in MSRc0010064 is invalid !!!\r
+  F3x80: e600e681 \r
+  F3x84: 80e641e6 \r
+  F3xD4: c8810f26 \r
+  F3xD8: 03001016 \r
+  F3xDC: 0000611a \r
+POST: 0x36\r
+core0 started: \r
+start_other_cores()\r
+init node: 00  cores: 05 \r
+Start other core - nodeid: 00  cores: 05\r
+POST: 0x37\r
+started ap apicid: PPOPPOOPOSTSOSSTSTT: T::::   00x00 xx0xx3333300000\r\r\r\r\r
+
+
+
+
+     cccccooooorrrrreeeeexxxxx:::::          ---------------     {{{{{     AAAAAPPPPPIIIIICCCCCIIIIIDDDDD     =====     0000053241     NNNNNOOOOODDDDDEEEEEIIIIIDDDDD     =====     0000000000     CCCCCOOOOORRRRREEEEEIIIIIDDDDD     =====     0000015324}}}}}     ---------------\r\r\r\r\r
+
+
+
+
+* AmmmmmPiiiii cccccrrrrr0oooo1occcccooooodddddeeeee:::::     eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt     rrrrreeeeevvvvv     iiiiiddddd          =====     00000xxxxx1111100000aaaaa00000,,,,,     cccccuuuuurrrrrrrrrreeeeennnnnttttt     pppppaaaaatttttccccchhhhh     iiiiiddddd     =====     00000xxxxx0000000000000000000000000000000000000000\r\r\r\r\r
+
+
+
+
+startmmemmmiiiidiccc\rccrr
+rrrooooocccccooooodddddeeeee:::::     pppppaaaaatttttccccchhhhh     iiiiiddddd     tttttooooo     aaaaapppppppppplllllyyyyy     =====     00000xxxxx000001111100000000000000000000bbbbbfffff\r\r\r\r\r
+
+
+
+
+m*mmmm iiiiicccccArrrrProoo ooccc0ccoo2ooodddddeeeee:::::     uuuuupppppdddddaaaaattttteeeeeddddd     tttttooooo     pppppaaaaatttttccccchhhhh     iiiiiddddd     =====     00000xxxxx000001111100000000000000000000bbbbbfffff          sssssuuuuucccccccccceeeeessssssssss\r\r\r\r\r
+
+
+
+
+\r\r\r\r\r
+
+
+
+
+sccppccctupppauuuurSSSSSteeeeettetdAAtt\rMMAAA
+DDMMMMMDDDSSMMMSSRRSRRR     * AP  0    ddddd3ooooonnnnneeeee\r\r\r\r\r
+
+
+
+
+stiiiiinnannniriiiitttttte_____fffffdiiii\ridddd
+dvvvvviiiiiddddd_____ssssstttttaaaaagggggeeeee22222     aaaaapppppiiiiiccccciiiiiddddd:::::     0000041235\r\r\r\r\r
+
+
+
+
+* AP 04started\r
+* AP 05started\r
+\r
+POST: 0x38\r
+rs780_early_setup()\r
+fam10_optimization()\r
+rs780_por_init\r
+\r
+Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440 \r
+POST: 0x39\r
+POST: 0x3a\r
+End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440 \r
+rs780_htinit cpu_ht_freq=b.\r
+rs780_htinit: HT3 mode\r
+POST: 0x3b\r
+fill_mem_ctrl()\r
+POST: 0x40\r
+raminit_amdmct()\r
+raminit_amdmct begin:\r
+        DIMMPresence: DIMMValid=c\r
+        DIMMPresence: DIMMPresent=c\r
+        DIMMPresence: RegDIMMPresent=0\r
+        DIMMPresence: DimmECCPresent=0\r
+        DIMMPresence: DimmPARPresent=0\r
+        DIMMPresence: Dimmx4Present=0\r
+        DIMMPresence: Dimmx8Present=c\r
+        DIMMPresence: Dimmx16Present=0\r
+        DIMMPresence: DimmPlPresent=0\r
+        DIMMPresence: DimmDRPresent=c\r
+        DIMMPresence: DimmQRPresent=0\r
+        DIMMPresence: DATAload[0]=2\r
+        DIMMPresence: MAload[0]=10\r
+        DIMMPresence: MAdimms[0]=1\r
+        DIMMPresence: DATAload[1]=2\r
+        DIMMPresence: MAload[1]=10\r
+        DIMMPresence: MAdimms[1]=1\r
+        DIMMPresence: Status 1000\r
+        DIMMPresence: ErrStatus 0\r
+        DIMMPresence: ErrCode 0\r
+        DIMMPresence: Done\r
+\r
+               DCTInit_D: mct_DIMMPresence Done\r
+SPDCalcWidth: Status 1000\r
+SPDCalcWidth: ErrStatus 0\r
+SPDCalcWidth: ErrCode 0\r
+SPDCalcWidth: Done\r
+               DCTInit_D: mct_SPDCalcWidth Done\r
+SPDGetTCL_D: DIMMCASL 4\r
+SPDGetTCL_D: DIMMAutoSpeed 4\r
+SPDGetTCL_D: Status 1000\r
+SPDGetTCL_D: ErrStatus 0\r
+SPDGetTCL_D: ErrCode 0\r
+SPDGetTCL_D: Done\r
+\r
+AutoCycTiming: Status 1000\r
+AutoCycTiming: ErrStatus 0\r
+AutoCycTiming: ErrCode 0\r
+AutoCycTiming: Done\r
+\r
+               DCTInit_D: AutoCycTiming_D Done\r
+SPDSetBanks: CSPresent c\r
+SPDSetBanks: Status 1000\r
+SPDSetBanks: ErrStatus 0\r
+SPDSetBanks: ErrCode 0\r
+SPDSetBanks: Done\r
+\r
+AfterStitch pDCTstat->NodeSysBase = 0\r
+mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff\r
+StitchMemory: Status 1000\r
+StitchMemory: ErrStatus 0\r
+StitchMemory: ErrCode 0\r
+StitchMemory: Done\r
+\r
+InterleaveBanks_D: Status 1000\r
+InterleaveBanks_D: ErrStatus 0\r
+InterleaveBanks_D: ErrCode 0\r
+InterleaveBanks_D: Done\r
+\r
+AutoConfig_D: DramControl: 2a06\r
+AutoConfig_D: DramTimingLo: 90092\r
+AutoConfig_D: DramConfigMisc: 0\r
+AutoConfig_D: DramConfigMisc2: 0\r
+AutoConfig_D: DramConfigLo: 10000\r
+AutoConfig_D: DramConfigHi: f40000b\r
+AutoConfig: Status 1000\r
+AutoConfig: ErrStatus 0\r
+AutoConfig: ErrCode 0\r
+AutoConfig: Done\r
+\r
+               DCTInit_D: AutoConfig_D Done\r
+               DCTInit_D: PlatformSpec_D Done\r
+               DCTInit_D: StartupDCT_D\r
+               DCTInit_D: mct_DIMMPresence Done\r
+SPDCalcWidth: Status 1000\r
+SPDCalcWidth: ErrStatus 0\r
+SPDCalcWidth: ErrCode 0\r
+SPDCalcWidth: Done\r
+               DCTInit_D: mct_SPDCalcWidth Done\r
+AutoCycTiming: Status 1000\r
+AutoCycTiming: ErrStatus 0\r
+AutoCycTiming: ErrCode 0\r
+AutoCycTiming: Done\r
+\r
+               DCTInit_D: AutoCycTiming_D Done\r
+SPDSetBanks: CSPresent c\r
+SPDSetBanks: Status 1000\r
+SPDSetBanks: ErrStatus 0\r
+SPDSetBanks: ErrCode 0\r
+SPDSetBanks: Done\r
+\r
+AfterStitch pDCTstat->NodeSysBase = 0\r
+mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe\r
+StitchMemory: Status 1000\r
+StitchMemory: ErrStatus 0\r
+StitchMemory: ErrCode 0\r
+StitchMemory: Done\r
+\r
+InterleaveBanks_D: Status 1000\r
+InterleaveBanks_D: ErrStatus 0\r
+InterleaveBanks_D: ErrCode 0\r
+InterleaveBanks_D: Done\r
+\r
+AutoConfig_D: DramControl: 2a06\r
+AutoConfig_D: DramTimingLo: 90092\r
+AutoConfig_D: DramConfigMisc: 0\r
+AutoConfig_D: DramConfigMisc2: 0\r
+AutoConfig_D: DramConfigLo: 10000\r
+AutoConfig_D: DramConfigHi: f40000b\r
+AutoConfig: Status 1000\r
+AutoConfig: ErrStatus 0\r
+AutoConfig: ErrCode 0\r
+AutoConfig: Done\r
+\r
+               DCTInit_D: AutoConfig_D Done\r
+               DCTInit_D: PlatformSpec_D Done\r
+               DCTInit_D: StartupDCT_D\r
+mctAutoInitMCT_D: SyncDCTsReady_D\r
+mctAutoInitMCT_D: HTMemMapInit_D\r
+ Node: 00  base: 00  limit: 1ffffff  BottomIO: c00000\r
+ Node: 00  base: 03  limit: 23fffff \r
+ Node: 01  base: 00  limit: 00 \r
+ Node: 02  base: 00  limit: 00 \r
+ Node: 03  base: 00  limit: 00 \r
+ Node: 04  base: 00  limit: 00 \r
+ Node: 05  base: 00  limit: 00 \r
+ Node: 06  base: 00  limit: 00 \r
+ Node: 07  base: 00  limit: 00 \r
+mctAutoInitMCT_D: CPUMemTyping_D\r
+        CPUMemTyping: Cache32bTOP:c00000\r
+        CPUMemTyping: Bottom32bIO:c00000\r
+        CPUMemTyping: Bottom40bIO:2400000\r
+mctAutoInitMCT_D: DQSTiming_D\r
+TrainRcvrEn: Status 1100\r
+TrainRcvrEn: ErrStatus 0\r
+TrainRcvrEn: ErrCode 0\r
+TrainRcvrEn: Done\r
+\r
+TrainDQSRdWrPos: Status 1100\r
+TrainDQSRdWrPos: TrainErrors 0\r
+TrainDQSRdWrPos: ErrStatus 0\r
+TrainDQSRdWrPos: ErrCode 0\r
+TrainDQSRdWrPos: Done\r
+\r
+TrainDQSRdWrPos: Status 1100\r
+TrainDQSRdWrPos: TrainErrors 0\r
+TrainDQSRdWrPos: ErrStatus 0\r
+TrainDQSRdWrPos: ErrCode 0\r
+TrainDQSRdWrPos: Done\r
+\r
+TrainDQSRdWrPos: Status 1100\r
+TrainDQSRdWrPos: TrainErrors 0\r
+TrainDQSRdWrPos: ErrStatus 0\r
+TrainDQSRdWrPos: ErrCode 0\r
+TrainDQSRdWrPos: Done\r
+\r
+TrainDQSRdWrPos: Status 1100\r
+TrainDQSRdWrPos: TrainErrors 0\r
+TrainDQSRdWrPos: ErrStatus 0\r
+TrainDQSRdWrPos: ErrCode 0\r
+TrainDQSRdWrPos: Done\r
+\r
+mctAutoInitMCT_D: UMAMemTyping_D\r
+mctAutoInitMCT_D: :OtherTiming\r
+InterleaveNodes_D: Status 1100\r
+InterleaveNodes_D: ErrStatus 0\r
+InterleaveNodes_D: ErrCode 0\r
+InterleaveNodes_D: Done\r
+\r
+InterleaveChannels_D: Node 0\r
+InterleaveChannels_D: Status 1100\r
+InterleaveChannels_D: ErrStatus 0\r
+InterleaveChannels_D: ErrCode 0\r
+InterleaveChannels_D: Node 1\r
+InterleaveChannels_D: Status 1000\r
+InterleaveChannels_D: ErrStatus 0\r
+InterleaveChannels_D: ErrCode 0\r
+InterleaveChannels_D: Node 2\r
+InterleaveChannels_D: Status 1000\r
+InterleaveChannels_D: ErrStatus 0\r
+InterleaveChannels_D: ErrCode 0\r
+InterleaveChannels_D: Node 3\r
+InterleaveChannels_D: Status 1000\r
+InterleaveChannels_D: ErrStatus 0\r
+InterleaveChannels_D: ErrCode 0\r
+InterleaveChannels_D: Node 4\r
+InterleaveChannels_D: Status 1000\r
+InterleaveChannels_D: ErrStatus 0\r
+InterleaveChannels_D: ErrCode 0\r
+InterleaveChannels_D: Node 5\r
+InterleaveChannels_D: Status 1000\r
+InterleaveChannels_D: ErrStatus 0\r
+InterleaveChannels_D: ErrCode 0\r
+InterleaveChannels_D: Node 6\r
+InterleaveChannels_D: Status 1000\r
+InterleaveChannels_D: ErrStatus 0\r
+InterleaveChannels_D: ErrCode 0\r
+InterleaveChannels_D: Node 7\r
+InterleaveChannels_D: Status 1000\r
+InterleaveChannels_D: ErrStatus 0\r
+InterleaveChannels_D: ErrCode 0\r
+InterleaveChannels_D: Done\r
+\r
+mctAutoInitMCT_D: ECCInit_D\r
+All Done\r
+raminit_amdmct end:\r
+POST: 0x41\r
+POST: 0x42\r
+v_esp=000cbef8\r
+testx = 5a5a5a5a\r
+Copying data from cache to RAM -- switching to use RAM as stack... Done\r
+testx = 5a5a5a5a\r
+Disabling cache as ram now \r
+Clearing initial memory region: Done\r
+Loading image.\r
+Searching for fallback/coreboot_ram\r
+Check cmos_layout.bin\r
+Check fallback/romstage\r
+Check fallback/coreboot_ram\r
+Stage: loading fallback/coreboot_ram @ 0x200000 (1277952 bytes), entry @ 0x200000\r
+Stage: done loading.\r
+Jumping to image.\r
+POST: 0x80\r
+POST: 0x39\r
+coreboot-4.0-2026-g15127e2-dirty Wed Feb  8 14:48:08 CET 2012 booting...\r
+POST: 0x40\r
+Enumerating buses...\r
+Show all devs...Before device enumeration.\r
+Root Device: enabled 1\r
+APIC_CLUSTER: 0: enabled 1\r
+APIC: 00: enabled 1\r
+PCI_DOMAIN: 0000: enabled 1\r
+PCI: 00:18.0: enabled 1\r
+PCI: 00:00.0: enabled 1\r
+PCI: 00:02.0: enabled 1\r
+PCI: 00:03.0: enabled 0\r
+PCI: 00:04.0: enabled 1\r
+PCI: 00:05.0: enabled 0\r
+PCI: 00:06.0: enabled 0\r
+PCI: 00:07.0: enabled 0\r
+PCI: 00:08.0: enabled 0\r
+PCI: 00:09.0: enabled 1\r
+PCI: 00:0a.0: enabled 1\r
+PCI: 00:11.0: enabled 1\r
+PCI: 00:12.0: enabled 1\r
+PCI: 00:12.2: enabled 1\r
+PCI: 00:13.0: enabled 1\r
+PCI: 00:13.2: enabled 1\r
+PCI: 00:14.0: enabled 1\r
+I2C: 00:50: enabled 1\r
+I2C: 00:51: enabled 1\r
+I2C: 00:52: enabled 1\r
+I2C: 00:53: enabled 1\r
+PCI: 00:14.1: enabled 1\r
+PCI: 00:14.2: enabled 1\r
+PCI: 00:14.3: enabled 1\r
+PNP: 002e.0: enabled 0\r
+PNP: 002e.1: enabled 0\r
+PNP: 002e.2: enabled 1\r
+PNP: 002e.3: enabled 1\r
+PNP: 002e.5: enabled 1\r
+PNP: 002e.6: enabled 0\r
+PNP: 002e.7: enabled 0\r
+PNP: 002e.8: enabled 0\r
+PNP: 002e.9: enabled 0\r
+PNP: 002e.a: enabled 0\r
+PNP: 002e.b: enabled 1\r
+PCI: 00:14.4: enabled 0\r
+PCI: 00:14.5: enabled 1\r
+PCI: 00:14.6: enabled 0\r
+PCI: 00:15.0: enabled 1\r
+PCI: 00:15.1: enabled 1\r
+PCI: 00:15.2: enabled 1\r
+PCI: 00:15.3: enabled 1\r
+PCI: 00:16.0: enabled 1\r
+PCI: 00:16.2: enabled 1\r
+PCI: 00:18.1: enabled 1\r
+PCI: 00:18.2: enabled 1\r
+PCI: 00:18.3: enabled 1\r
+PCI: 00:18.4: enabled 1\r
+Compare with tree...\r
+Root Device: enabled 1\r
+ APIC_CLUSTER: 0: enabled 1\r
+  APIC: 00: enabled 1\r
+ PCI_DOMAIN: 0000: enabled 1\r
+  PCI: 00:18.0: enabled 1\r
+   PCI: 00:00.0: enabled 1\r
+   PCI: 00:02.0: enabled 1\r
+   PCI: 00:03.0: enabled 0\r
+   PCI: 00:04.0: enabled 1\r
+   PCI: 00:05.0: enabled 0\r
+   PCI: 00:06.0: enabled 0\r
+   PCI: 00:07.0: enabled 0\r
+   PCI: 00:08.0: enabled 0\r
+   PCI: 00:09.0: enabled 1\r
+   PCI: 00:0a.0: enabled 1\r
+   PCI: 00:11.0: enabled 1\r
+   PCI: 00:12.0: enabled 1\r
+   PCI: 00:12.2: enabled 1\r
+   PCI: 00:13.0: enabled 1\r
+   PCI: 00:13.2: enabled 1\r
+   PCI: 00:14.0: enabled 1\r
+    I2C: 00:50: enabled 1\r
+    I2C: 00:51: enabled 1\r
+    I2C: 00:52: enabled 1\r
+    I2C: 00:53: enabled 1\r
+   PCI: 00:14.1: enabled 1\r
+   PCI: 00:14.2: enabled 1\r
+   PCI: 00:14.3: enabled 1\r
+    PNP: 002e.0: enabled 0\r
+    PNP: 002e.1: enabled 0\r
+    PNP: 002e.2: enabled 1\r
+    PNP: 002e.3: enabled 1\r
+    PNP: 002e.5: enabled 1\r
+    PNP: 002e.6: enabled 0\r
+    PNP: 002e.7: enabled 0\r
+    PNP: 002e.8: enabled 0\r
+    PNP: 002e.9: enabled 0\r
+    PNP: 002e.a: enabled 0\r
+    PNP: 002e.b: enabled 1\r
+   PCI: 00:14.4: enabled 0\r
+   PCI: 00:14.5: enabled 1\r
+   PCI: 00:14.6: enabled 0\r
+   PCI: 00:15.0: enabled 1\r
+   PCI: 00:15.1: enabled 1\r
+   PCI: 00:15.2: enabled 1\r
+   PCI: 00:15.3: enabled 1\r
+   PCI: 00:16.0: enabled 1\r
+   PCI: 00:16.2: enabled 1\r
+  PCI: 00:18.1: enabled 1\r
+  PCI: 00:18.2: enabled 1\r
+  PCI: 00:18.3: enabled 1\r
+  PCI: 00:18.4: enabled 1\r
+Mainboard ASUS M5A99X-EVO Enable. dev=0x002324c0\r
+Enumerating buses... starting with root now\r
+scan_static_bus for Root Device\r
+APIC_CLUSTER: 0 enabled\r
+PCI_DOMAIN: 0000 enabled\r
+APIC_CLUSTER: 0 scanning...\r
+cpu_bus_scan: starting...\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+  PCI: 00:18.3 siblings=5\r
+CPU: APIC: 00 enabled\r
+CPU: APIC: 01 enabled\r
+CPU: APIC: 02 enabled\r
+CPU: APIC: 03 enabled\r
+CPU: APIC: 04 enabled\r
+CPU: APIC: 05 enabled\r
+cpu_bus_scan: done.\r
+PCI_DOMAIN: 0000 scanning...\r
+PCI: pci_scan_bus for bus 00\r
+POST: 0x24\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 192\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_probe_dev: ohai, non-dummy stuff!\r
+pci_probe_dev: before enable! 0x00000000\r
+pci_probe_dev: before read!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_probe_dev: after  read: 0x12001022\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+PCI: 00:18.0 [1022/1200] bus ops\r
+PCI: 00:18.0 [1022/1200] enabled\r
+pci_scan_bus: after  pci_probe_dev!\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 193\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_probe_dev: ohai, non-dummy stuff!\r
+pci_probe_dev: before enable! 0x00000000\r
+pci_probe_dev: before read!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_probe_dev: after  read: 0x12011022\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+PCI: 00:18.1 [1022/1201] enabled\r
+pci_scan_bus: after  pci_probe_dev!\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 194\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_probe_dev: ohai, non-dummy stuff!\r
+pci_probe_dev: before enable! 0x00000000\r
+pci_probe_dev: before read!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_probe_dev: after  read: 0x12021022\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+PCI: 00:18.2 [1022/1202] enabled\r
+pci_scan_bus: after  pci_probe_dev!\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 195\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_probe_dev: ohai, non-dummy stuff!\r
+pci_probe_dev: before enable! 0x00000000\r
+pci_probe_dev: before read!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_probe_dev: after  read: 0x12031022\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+PCI: 00:18.3 [1022/1203] ops\r
+PCI: 00:18.3 [1022/1203] enabled\r
+pci_scan_bus: after  pci_probe_dev!\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 196\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_probe_dev: ohai, non-dummy stuff!\r
+pci_probe_dev: before enable! 0x00000000\r
+pci_probe_dev: before read!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_probe_dev: after  read: 0x12041022\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+PCI: 00:18.4 [1022/1204] enabled\r
+pci_scan_bus: after  pci_probe_dev!\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 197\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_scan_bus: after  pci_probe_dev!\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 198\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_scan_bus: after  pci_probe_dev!\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 199\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_scan_bus: after  pci_probe_dev!\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 200\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_scan_bus: after  pci_probe_dev!\r
+pci_scan_bus: ohai, +7\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 208\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_scan_bus: after  pci_probe_dev!\r
+pci_scan_bus: ohai, +7\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 216\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_scan_bus: after  pci_probe_dev!\r
+pci_scan_bus: ohai, +7\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 224\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_scan_bus: after  pci_probe_dev!\r
+pci_scan_bus: ohai, +7\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 232\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_scan_bus: after  pci_probe_dev!\r
+pci_scan_bus: ohai, +7\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 240\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_scan_bus: after  pci_probe_dev!\r
+pci_scan_bus: ohai, +7\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 248\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_scan_bus: after  pci_probe_dev!\r
+pci_scan_bus: ohai, +7\r
+\r
+POST: 0x25\r
+amdfam10_scan_chains: starting...\r
+amdfam10_scan_chains: link: 00232834\r
+amdfam10_scan_chain: starting...\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+amdfam10_scan_chain: link_type: 0x00000007\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+amdfam10_scan_chain: link_type: 0x00000007\r
+amdfam10_scan_chain: before get_ht_c_index\r
+amdfam10_scan_chain: after  get_ht_c_index\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+amdfam10_scan_chain: before set_config_map_reg\r
+amdfam10_scan_chain: after  set_config_map_reg\r
+amdfam10_scan_chain: before hypertransport_scan_chain\r
+hypertransport_scan_chain: before ht_collapse_early_enumeration\r
+hypertransport_scan_chain: after  ht_collapse_early_enumeration\r
+hypertransport_scan_chain: before ht_scan_get_devs\r
+hypertransport_scan_chain: after  ht_scan_get_devs\r
+hypertransport_scan_chain: before pci_probe_dev\r
+pci_probe_dev: ohai, non-dummy stuff!\r
+pci_probe_dev: before enable! 0x00205d54\r
+pci_probe_dev: we're going to call enable stuff?\r
+rs780_enable: WHAT THE FUCK\r
+PCI: Using configuration type 1\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+rs780_enable: dev=00232a8c, VID_DID=0x5a141002\r
+Bus-0, Dev-0, Fun-0.\r
+enable_pcie_bar3()\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+addr=e0000000,bus=0,devfn=40\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+NB_PCI_REG04 = 2.\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+NB_PCI_REG84 = 3000095.\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+NB_PCI_REG4C = 52042.\r
+rs780_enable: done\r
+pci_probe_dev: before read!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_probe_dev: after  read: 0x5a141002\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+PCI: 00:00.0 [1002/5a14] enabled\r
+hypertransport_scan_chain: after  pci_probe_dev\r
+hypertransport_scan_chain: before ht_lookup_slave_capability\r
+Capability: type 0x08 @ 0xf0\r
+flags: 0xa803\r
+Capability: type 0x08 @ 0xf0\r
+Capability: type 0x08 @ 0xc4\r
+flags: 0x0281\r
+hypertransport_scan_chain: after  ht_lookup_slave_capability\r
+hypertransport_scan_chain: end_of_chain.  w00t!\r
+hypertransport_scan_chain: before pci_scan_bus!\r
+PCI: pci_scan_bus for bus 00\r
+PCI: pci_scan_bus limits devfn 0 - devfn ffffffff\r
+PCI: pci_scan_bus upper limit too big. Using 0xff.\r
+POST: 0x24\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 0\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_probe_dev: ohai, non-dummy stuff!\r
+pci_probe_dev: before enable! 0x00205d54\r
+pci_probe_dev: we're going to call enable stuff?\r
+rs780_enable: WHAT THE FUCK\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+rs780_enable: dev=00232a8c, VID_DID=0x5a141002\r
+Bus-0, Dev-0, Fun-0.\r
+enable_pcie_bar3()\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+NB_PCI_REG04 = 2.\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+NB_PCI_REG84 = 3000095.\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+NB_PCI_REG4C = 52042.\r
+rs780_enable: done\r
+pci_probe_dev: before read!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_probe_dev: after  read: 0x5a141002\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+PCI: 00:00.0 [1002/5a14] enabled\r
+pci_scan_bus: after  pci_probe_dev!\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 1\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_scan_bus: after  pci_probe_dev!\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 2\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_scan_bus: after  pci_probe_dev!\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 3\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_scan_bus: after  pci_probe_dev!\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 4\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_scan_bus: after  pci_probe_dev!\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 5\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_scan_bus: after  pci_probe_dev!\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 6\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_scan_bus: after  pci_probe_dev!\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 7\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_scan_bus: after  pci_probe_dev!\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 8\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r
+pci_scan_bus: after  pci_probe_dev!\r
+pci_scan_bus: ohai, +7\r
+\r
+pci_scan_bus: before pci_scan_get_dev! devfn: 16\r
+pci_scan_bus: after  pci_scan_get_dev!\r
+pci_scan_bus: before pci_probe_dev!\r
+pci_probe_dev: ohai, non-dummy stuff!\r
+pci_probe_dev: before enable! 0x00205d54\r
+pci_probe_dev: we're going to call enable stuff?\r
+rs780_enable: WHAT THE FUCK\r
+pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f\r

diff --git a/2012-02-08_14:54_coreboot.log b/2012-02-08_14:54_coreboot.log
new file mode 100644 (file)
index 0000000..a3e0c60
Binary files /dev/null and b/2012-02-08_14:54_coreboot.log differ

diff --git a/2012-02-08_16:13_config b/2012-02-08_16:13_config
new file mode 100644 (file)
index 0000000..ecf3cd9
--- /dev/null
+++ b/2012-02-08_16:13_config
@@ -0,0 +1,388 @@
+#
+# Automatically generated make config: don't edit
+# coreboot version: 4.0-2031-g2f6cfcf-dirty
+# Wed Feb  8 15:14:19 2012
+#
+
+#
+# General setup
+#
+# CONFIG_EXPERT is not set
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_SCANBUILD_ENABLE is not set
+# CONFIG_CCACHE is not set
+# CONFIG_USE_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+
+#
+# Mainboard
+#
+# CONFIG_VENDOR_AAEON is not set
+# CONFIG_VENDOR_ABIT is not set
+# CONFIG_VENDOR_ADVANSUS is not set
+# CONFIG_VENDOR_ADVANTECH is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_ARIMA is not set
+# CONFIG_VENDOR_ARTEC_GROUP is not set
+# CONFIG_VENDOR_ASI is not set
+# CONFIG_VENDOR_ASROCK is not set
+CONFIG_VENDOR_ASUS=y
+# CONFIG_VENDOR_A_TREND is not set
+# CONFIG_VENDOR_AVALUE is not set
+# CONFIG_VENDOR_AXUS is not set
+# CONFIG_VENDOR_AZZA is not set
+# CONFIG_VENDOR_BCOM is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BROADCOM is not set
+# CONFIG_VENDOR_COMPAQ is not set
+# CONFIG_VENDOR_DELL is not set
+# CONFIG_VENDOR_DIGITAL_LOGIC is not set
+# CONFIG_VENDOR_EAGLELION is not set
+# CONFIG_VENDOR_ECS is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_IWAVE is not set
+# CONFIG_VENDOR_IWILL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LANNER is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MITAC is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_NEC is not set
+# CONFIG_VENDOR_NEWISYS is not set
+# CONFIG_VENDOR_NOKIA is not set
+# CONFIG_VENDOR_NVIDIA is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_RCA is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SOYO is not set
+# CONFIG_VENDOR_SUNW is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TECHNEXION is not set
+# CONFIG_VENDOR_TECHNOLOGIC is not set
+# CONFIG_VENDOR_TELEVIDEO is not set
+# CONFIG_VENDOR_THOMSON is not set
+# CONFIG_VENDOR_TRAVERSE is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+# CONFIG_VENDOR_WINENT is not set
+# CONFIG_VENDOR_WYSE is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="asus/m5a99x-evo"
+CONFIG_MAINBOARD_PART_NUMBER="M5A99X-EVO"
+CONFIG_IRQ_SLOT_COUNT=11
+CONFIG_MAINBOARD_VENDOR="ASUS"
+CONFIG_APIC_ID_OFFSET=0x0
+CONFIG_HW_MEM_HOLE_SIZEK=0x100000
+CONFIG_MAX_CPUS=8
+CONFIG_MAX_PHYSICAL_CPUS=1
+# CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC is not set
+CONFIG_MEM_TRAIN_SEQ=2
+CONFIG_SB_HT_CHAIN_ON_BUS0=1
+CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
+CONFIG_HT_CHAIN_UNITID_BASE=0x0
+CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_010000bf.h"
+CONFIG_RAMTOP=0x2000000
+CONFIG_HEAP_SIZE=0xc0000
+CONFIG_RAMBASE=0x200000
+CONFIG_DCACHE_RAM_BASE=0xc4000
+CONFIG_DCACHE_RAM_SIZE=0x0c000
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
+CONFIG_SERIAL_CPU_INIT=y
+CONFIG_ACPI_SSDTX_NUM=0
+# CONFIG_VGA_BIOS is not set
+# CONFIG_AMD_AGESA is not set
+CONFIG_STACK_SIZE=0x8000
+# CONFIG_DRIVERS_PS2_KEYBOARD is not set
+# CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_CONSOLE_POST=y
+CONFIG_SATA_CONTROLLER_MODE=0x0
+# CONFIG_BOARD_ASUS_A8N_E is not set
+# CONFIG_BOARD_ASUS_A8V_E_SE is not set
+# CONFIG_BOARD_ASUS_A8V_E_DELUXE is not set
+# CONFIG_BOARD_ASUS_K8V_X is not set
+# CONFIG_BOARD_ASUS_M2N_E is not set
+# CONFIG_BOARD_ASUS_M2V is not set
+# CONFIG_BOARD_ASUS_M2V_MX_SE is not set
+# CONFIG_BOARD_ASUS_M4A785M is not set
+# CONFIG_BOARD_ASUS_M4A785TM is not set
+# CONFIG_BOARD_ASUS_M4A78_EM is not set
+# CONFIG_BOARD_ASUS_M5A88_V is not set
+CONFIG_BOARD_ASUS_M5A99X_EVO=y
+# CONFIG_BOARD_ASUS_MEW_AM is not set
+# CONFIG_BOARD_ASUS_MEW_VM is not set
+# CONFIG_BOARD_ASUS_P2B is not set
+# CONFIG_BOARD_ASUS_P2B_D is not set
+# CONFIG_BOARD_ASUS_P2B_DS is not set
+# CONFIG_BOARD_ASUS_P2B_F is not set
+# CONFIG_BOARD_ASUS_P2B_LS is not set
+# CONFIG_BOARD_ASUS_P3B_F is not set
+CONFIG_AGP_APERTURE_SIZE=0x4000000
+# CONFIG_PCI_64BIT_PREF_MEM is not set
+CONFIG_MMCONF_BASE_ADDRESS=0xe0000000
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/cimx/sb900/bootblock.c"
+CONFIG_MMCONF_SUPPORT_DEFAULT=y
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_LOGICAL_CPUS=y
+CONFIG_IOAPIC=y
+CONFIG_SMP=y
+CONFIG_TTYS0_BAUD=115200
+CONFIG_TTYS0_BASE=0x3f8
+CONFIG_TTYS0_LCS=3
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+CONFIG_CONSOLE_SERIAL8250=y
+# CONFIG_PCI_ROM_RUN is not set
+# CONFIG_USBDEBUG is not set
+CONFIG_VAR_MTRR_HOLE=y
+CONFIG_LIFT_BSP_APIC_ID=y
+# CONFIG_WAIT_BEFORE_CPUS_INIT is not set
+CONFIG_HT3_SUPPORT=y
+# CONFIG_K8_REV_F_SUPPORT is not set
+CONFIG_BOARD_ROMSIZE_KB_4096=y
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_4096=y
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=4096
+CONFIG_ROM_SIZE=0x400000
+CONFIG_ARCH_X86=y
+
+#
+# Architecture (x86)
+#
+# CONFIG_AP_IN_SIPI_WAIT is not set
+CONFIG_ROMBASE=0xffff0000
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_X86_BOOTBLOCK_SIMPLE=y
+# CONFIG_X86_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_ROMCC is not set
+CONFIG_PC80_SYSTEM=y
+CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/amd/amdfam10/bootblock.c"
+# CONFIG_HAVE_CMOS_DEFAULT is not set
+# CONFIG_BIG_ENDIAN is not set
+CONFIG_LITTLE_ENDIAN=y
+
+#
+# Chipset
+#
+
+#
+# CPU
+#
+CONFIG_CPU_ADDR_BITS=48
+CONFIG_CPU_SOCKET_TYPE=0x11
+# CONFIG_EXT_RT_TBL_SUPPORT is not set
+# CONFIG_EXT_CONF_SUPPORT is not set
+CONFIG_CBB=0x0
+CONFIG_CDB=0x18
+CONFIG_XIP_ROM_SIZE=0x80000
+CONFIG_CPU_AMD_SOCKET_AM3=y
+CONFIG_DIMM_SUPPORT=0x0005
+# CONFIG_UDELAY_IO is not set
+CONFIG_SET_FIDVID=y
+CONFIG_SET_FIDVID_DEBUG=y
+# CONFIG_SET_FIDVID_CORE0_ONLY is not set
+CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST=y
+CONFIG_CPU_AMD_MODEL_10XXX=y
+CONFIG_SET_FIDVID_CORE_RANGE=0
+CONFIG_UPDATE_CPU_MICROCODE=y
+CONFIG_XIP_ROM_BASE=0xfff00000
+CONFIG_HAVE_INIT_TIMER=y
+CONFIG_SSE2=y
+# CONFIG_UDELAY_LAPIC is not set
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_UDELAY_TIMER2 is not set
+# CONFIG_TSC_CALIBRATE_WITH_IO is not set
+CONFIG_CACHE_AS_RAM=y
+CONFIG_SSE=y
+
+#
+# Northbridge
+#
+CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=y
+CONFIG_QRANK_DIMM_SUPPORT=y
+# CONFIG_DIMM_DDR2 is not set
+CONFIG_DIMM_REGISTERED=y
+CONFIG_VIDEO_MB=0
+CONFIG_NORTHBRIDGE_AMD_AMDFAM10=y
+CONFIG_AMDMCT=y
+CONFIG_MMCONF_BUS_NUMBER=256
+# CONFIG_DIMM_FBDIMM is not set
+CONFIG_DIMM_DDR3=y
+# CONFIG_SVI_HIGH_FREQ is not set
+CONFIG_NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX=y
+# CONFIG_CONSOLE_VGA_MULTI is not set
+CONFIG_AMD_NB_CIMX=y
+CONFIG_NORTHBRIDGE_AMD_CIMX_RD890=y
+# CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL is not set
+# CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK is not set
+
+#
+# Southbridge
+#
+CONFIG_AMD_SB_CIMX=y
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
+CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900=y
+# CONFIG_PCIB_ENABLE is not set
+CONFIG_ACPI_SCI_IRQ=0x9
+
+#
+# Super I/O
+#
+CONFIG_SUPERIO_ITE_IT8721F=y
+
+#
+# Devices
+#
+# CONFIG_VGA_BRIDGE_SETUP is not set
+# CONFIG_VGA_ROM_RUN is not set
+# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
+CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT=y
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_AGP_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+
+#
+# Embedded Controllers
+#
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_OXFORD_OXPCIE is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_PCI_BUS_SEGN_BITS=0
+CONFIG_MMCONF_SUPPORT=y
+
+#
+# Console
+#
+CONFIG_CONSOLE_SERIAL_COM1=y
+# CONFIG_CONSOLE_SERIAL_COM2 is not set
+# CONFIG_CONSOLE_SERIAL_COM3 is not set
+# CONFIG_CONSOLE_SERIAL_COM4 is not set
+CONFIG_CONSOLE_SERIAL_115200=y
+# CONFIG_CONSOLE_SERIAL_57600 is not set
+# CONFIG_CONSOLE_SERIAL_38400 is not set
+# CONFIG_CONSOLE_SERIAL_19200 is not set
+# CONFIG_CONSOLE_SERIAL_9600 is not set
+# CONFIG_HAVE_USBDEBUG is not set
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_CONSOLE_LOGBUF is not set
+# CONFIG_NO_POST is not set
+CONFIG_POST_PORT=0x80
+CONFIG_HAVE_UART_IO_MAPPED=y
+# CONFIG_HAVE_UART_MEMORY_MAPPED is not set
+# CONFIG_HAVE_ACPI_RESUME is not set
+# CONFIG_HAVE_ACPI_SLIC is not set
+CONFIG_HAVE_HARD_RESET=y
+CONFIG_HAVE_MAINBOARD_RESOURCES=y
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+# CONFIG_HAVE_SMI_HANDLER is not set
+CONFIG_PCI_IO_CFG_EXT=y
+# CONFIG_USE_WATCHDOG_ON_BOOT is not set
+# CONFIG_VGA is not set
+# CONFIG_GFXUMA is not set
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_HAVE_MP_TABLE=y
+CONFIG_HAVE_PIRQ_TABLE=y
+CONFIG_GENERATE_ACPI_TABLES=y
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# System tables
+#
+CONFIG_WRITE_HIGH_TABLES=y
+CONFIG_MULTIBOOT=y
+
+#
+# Payload
+#
+# CONFIG_PAYLOAD_NONE is not set
+# CONFIG_PAYLOAD_ELF is not set
+CONFIG_PAYLOAD_SEABIOS=y
+# CONFIG_PAYLOAD_FILO is not set
+CONFIG_SEABIOS_STABLE=y
+# CONFIG_SEABIOS_MASTER is not set
+CONFIG_PAYLOAD_FILE="$(obj)/seabios/out/bios.bin.elf"
+CONFIG_COMPRESSED_PAYLOAD_LZMA=y
+# CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set
+
+#
+# VGA BIOS
+#
+
+#
+# Debugging
+#
+CONFIG_GDB_STUB=y
+CONFIG_HAVE_DEBUG_RAM_SETUP=y
+# CONFIG_DEBUG_RAM_SETUP is not set
+CONFIG_HAVE_DEBUG_CAR=y
+# CONFIG_DEBUG_CAR is not set
+CONFIG_DEBUG_PIRQ=y
+CONFIG_HAVE_DEBUG_SMBUS=y
+# CONFIG_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_MALLOC is not set
+CONFIG_DEBUG_ACPI=y
+# CONFIG_LLSHELL is not set
+# CONFIG_TRACE is not set
+# CONFIG_AP_CODE_IN_CAR is not set
+CONFIG_RAMINIT_SYSINFO=y
+CONFIG_ENABLE_APIC_EXT_ID=y
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+
+#
+# Deprecated
+#
+# CONFIG_BOARD_HAS_HARD_RESET is not set
+CONFIG_BOARD_HAS_FADT=y
+CONFIG_HAVE_BUS_CONFIG=y
+# CONFIG_PCIE_TUNING is not set
+CONFIG_ID_SECTION_OFFSET=0x80

diff --git a/2012-02-08_16:13_coreboot.log b/2012-02-08_16:13_coreboot.log
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/2012-02-08_16:13_log b/2012-02-08_16:13_log
new file mode 100644 (file)
index 0000000..a7c8e72
Binary files /dev/null and b/2012-02-08_16:13_log differ

diff --git a/2012-02-08_16:13_rom b/2012-02-08_16:13_rom
new file mode 100644 (file)
index 0000000..f0a910d
Binary files /dev/null and b/2012-02-08_16:13_rom differ

diff --git a/Makefile b/Makefile
index 6a88d5adfc0c1123a93cdf9101d8a601e4ce8688..6fc8959dda9fe1a0dd26f596838baf8747fb0adc 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -13,8 +13,10 @@ writerom:
        flashrom $(PROGRAMMER) -n -w 2012-01-24_21:28_m5a99xevo.rom
 
 newlog:
+       cp ../repo/build/coreboot.rom $(DATE)_rom
+       cp ../repo/.config $(DATE)_config
        stty -F /dev/ttyS0 115200 nl
-       cat /dev/ttyS0 | tee $(DATE)_coreboot.log
+       cat /dev/ttyS0 | tee $(DATE)_log
 
 lastlog:
        vim `ls *.log | sort -rn | head -n1`