1 ½
\81\81\81\81\81ÁÁÁÁÁ
\85\85\85\85\85ÑÑÑÑÑ
\8d\8d\8d\8d\8d¡¡¡¡¡
\81\81\81\81\81¥¥¥¥¥
\91\91\91\91\91\81\81\81\81\81õõõõõ
\81\81\81\81\81ÁÁÁÁÁáááááÁÁÁÁÁÅÅÅÅÅÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
\89\89\89\89\89\99\99\99\99\99\81\81\81\81\81\81\81\81\81\81ÍÍÍÍÍÕÕÕÕÕ
\8d\8d\8d\8d\8d\8d\8d\8d\8d\8d\95\95\95\95\95ÍÍÍÍÍÍÍÍÍÍ55555)))))55555)))))ÿsccctpppccppauuuSSuurSeeeSSteettteAttdAAMMAA
\rM
2 DDDMMDMMMDSMMSSRRSSRR R * AP 0 ddd3ddooooonnnnneeeee
\r\r\r\r\r
7 stiiiinnnianriiiinittttt__te__ffff_d
\riiiifdi
8 dddvvdvviiiividddd_d___aaa_appppap((((ss(sstttstaaaatgagggeegee111e11)))) ) aa aappppapiiiiciccciiiciddddid:::: : 000 041230
\r5
\r\r\r
13 FFFF*FIIIII ADDDDDVVPVVVIIII IDDDDD0 4 ooooonnnnn AAAAAPPPPP::::: 0000051234
\r\r\r\r\r
23 fam10_optimization()
\r
26 Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440
\r
28 FIDVID on BSP, APIC_id: 00
\r
30 Wait for AP stage 1: ap_apicid = 1
\r
32 common_fid(packed) = 0
\r
33 Wait for AP stage 1: ap_apicid = 2
\r
35 common_fid(packed) = 0
\r
36 Wait for AP stage 1: ap_apicid = 3
\r
38 common_fid(packed) = 0
\r
39 Wait for AP stage 1: ap_apicid = 4
\r
41 common_fid(packed) = 0
\r
42 Wait for AP stage 1: ap_apicid = 5
\r
44 common_fid(packed) = 0
\r
47 End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440
\r
48 rs780_htinit cpu_ht_freq=b.
\r
49 rs780_htinit: HT3 mode
\r
55 coreboot-4.0-2026-g15127e2-dirty Wed Feb 8 14:48:08 CET 2012 starting...
\r
57 BSP Family_Model: 00100fa0
\r
58 *sysinfo range: [000cc000,000cf360]
\r
60 cpu_init_detectedx = 00000000
\r
61 microcode: equivalent rev id = 0x10a0, current patch id = 0x00000000
\r
62 microcode: patch id to apply = 0x010000bf
\r
63 microcode: updated to patch id = 0x010000bf success
\r
71 SB900 - Early.c - get_sbdn - Start.
\r
72 SB900 - Early.c - get_sbdn - End.
\r
73 cpuSetAMDPCI 00 done
\r
74 Prep FID/VID Node:00
\r
75 P-state info in MSRC001_0064 is invalid !!!
\r
76 P-state info in MSRc0010064 is invalid !!!
\r
85 init node: 00 cores: 05
\r
86 Start other core - nodeid: 00 cores: 05
\r
88 started ap apicid: PPOPPOOPOSTSOSSTSTT: T:::: 00x00 xx0xx3333300000
\r\r\r\r\r
93 cccccooooorrrrreeeeexxxxx::::: --------------- {{{{{ AAAAAPPPPPIIIIICCCCCIIIIIDDDDD ===== 0000053241 NNNNNOOOOODDDDDEEEEEIIIIIDDDDD ===== 0000000000 CCCCCOOOOORRRRREEEEEIIIIIDDDDD ===== 0000015324}}}}} ---------------
\r\r\r\r\r
98 * AmmmmmPiiiii cccccrrrrr0oooo1occcccooooodddddeeeee::::: eeeeeqqqqquuuuuiiiiivvvvvaaaaallllleeeeennnnnttttt rrrrreeeeevvvvv iiiiiddddd ===== 00000xxxxx1111100000aaaaa00000,,,,, cccccuuuuurrrrrrrrrreeeeennnnnttttt pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx0000000000000000000000000000000000000000
\r\r\r\r\r
103 startmmemmmiiiidiccc
\rccrr
104 rrrooooocccccooooodddddeeeee::::: pppppaaaaatttttccccchhhhh iiiiiddddd tttttooooo aaaaapppppppppplllllyyyyy ===== 00000xxxxx000001111100000000000000000000bbbbbfffff
\r\r\r\r\r
109 m*mmmm iiiiicccccArrrrProoo ooccc0ccoo2ooodddddeeeee::::: uuuuupppppdddddaaaaattttteeeeeddddd tttttooooo pppppaaaaatttttccccchhhhh iiiiiddddd ===== 00000xxxxx000001111100000000000000000000bbbbbfffff sssssuuuuucccccccccceeeeessssssssss
\r\r\r\r\r
119 sccppccctupppauuuurSSSSSteeeeettetdAAtt
\rMMAAA
120 DDMMMMMDDDSSMMMSSRRSRRR * AP 0 ddddd3ooooonnnnneeeee
\r\r\r\r\r
125 stiiiiinnannniriiiitttttte_____fffffdiiii
\ridddd
126 dvvvvviiiiiddddd_____ssssstttttaaaaagggggeeeee22222 aaaaapppppiiiiiccccciiiiiddddd::::: 0000041235
\r\r\r\r\r
135 rs780_early_setup()
\r
136 fam10_optimization()
\r
139 Begin FIDVID MSR 0xc0010071 0x31c20031 0x40013440
\r
142 End FIDVIDMSR 0xc0010071 0x31c20031 0x40013440
\r
143 rs780_htinit cpu_ht_freq=b.
\r
144 rs780_htinit: HT3 mode
\r
149 raminit_amdmct begin:
\r
150 DIMMPresence: DIMMValid=c
\r
151 DIMMPresence: DIMMPresent=c
\r
152 DIMMPresence: RegDIMMPresent=0
\r
153 DIMMPresence: DimmECCPresent=0
\r
154 DIMMPresence: DimmPARPresent=0
\r
155 DIMMPresence: Dimmx4Present=0
\r
156 DIMMPresence: Dimmx8Present=c
\r
157 DIMMPresence: Dimmx16Present=0
\r
158 DIMMPresence: DimmPlPresent=0
\r
159 DIMMPresence: DimmDRPresent=c
\r
160 DIMMPresence: DimmQRPresent=0
\r
161 DIMMPresence: DATAload[0]=2
\r
162 DIMMPresence: MAload[0]=10
\r
163 DIMMPresence: MAdimms[0]=1
\r
164 DIMMPresence: DATAload[1]=2
\r
165 DIMMPresence: MAload[1]=10
\r
166 DIMMPresence: MAdimms[1]=1
\r
167 DIMMPresence: Status 1000
\r
168 DIMMPresence: ErrStatus 0
\r
169 DIMMPresence: ErrCode 0
\r
172 DCTInit_D: mct_DIMMPresence Done
\r
173 SPDCalcWidth: Status 1000
\r
174 SPDCalcWidth: ErrStatus 0
\r
175 SPDCalcWidth: ErrCode 0
\r
177 DCTInit_D: mct_SPDCalcWidth Done
\r
178 SPDGetTCL_D: DIMMCASL 4
\r
179 SPDGetTCL_D: DIMMAutoSpeed 4
\r
180 SPDGetTCL_D: Status 1000
\r
181 SPDGetTCL_D: ErrStatus 0
\r
182 SPDGetTCL_D: ErrCode 0
\r
185 AutoCycTiming: Status 1000
\r
186 AutoCycTiming: ErrStatus 0
\r
187 AutoCycTiming: ErrCode 0
\r
188 AutoCycTiming: Done
\r
190 DCTInit_D: AutoCycTiming_D Done
\r
191 SPDSetBanks: CSPresent c
\r
192 SPDSetBanks: Status 1000
\r
193 SPDSetBanks: ErrStatus 0
\r
194 SPDSetBanks: ErrCode 0
\r
197 AfterStitch pDCTstat->NodeSysBase = 0
\r
198 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffff
\r
199 StitchMemory: Status 1000
\r
200 StitchMemory: ErrStatus 0
\r
201 StitchMemory: ErrCode 0
\r
204 InterleaveBanks_D: Status 1000
\r
205 InterleaveBanks_D: ErrStatus 0
\r
206 InterleaveBanks_D: ErrCode 0
\r
207 InterleaveBanks_D: Done
\r
209 AutoConfig_D: DramControl: 2a06
\r
210 AutoConfig_D: DramTimingLo: 90092
\r
211 AutoConfig_D: DramConfigMisc: 0
\r
212 AutoConfig_D: DramConfigMisc2: 0
\r
213 AutoConfig_D: DramConfigLo: 10000
\r
214 AutoConfig_D: DramConfigHi: f40000b
\r
215 AutoConfig: Status 1000
\r
216 AutoConfig: ErrStatus 0
\r
217 AutoConfig: ErrCode 0
\r
220 DCTInit_D: AutoConfig_D Done
\r
221 DCTInit_D: PlatformSpec_D Done
\r
222 DCTInit_D: StartupDCT_D
\r
223 DCTInit_D: mct_DIMMPresence Done
\r
224 SPDCalcWidth: Status 1000
\r
225 SPDCalcWidth: ErrStatus 0
\r
226 SPDCalcWidth: ErrCode 0
\r
228 DCTInit_D: mct_SPDCalcWidth Done
\r
229 AutoCycTiming: Status 1000
\r
230 AutoCycTiming: ErrStatus 0
\r
231 AutoCycTiming: ErrCode 0
\r
232 AutoCycTiming: Done
\r
234 DCTInit_D: AutoCycTiming_D Done
\r
235 SPDSetBanks: CSPresent c
\r
236 SPDSetBanks: Status 1000
\r
237 SPDSetBanks: ErrStatus 0
\r
238 SPDSetBanks: ErrCode 0
\r
241 AfterStitch pDCTstat->NodeSysBase = 0
\r
242 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 1fffffe
\r
243 StitchMemory: Status 1000
\r
244 StitchMemory: ErrStatus 0
\r
245 StitchMemory: ErrCode 0
\r
248 InterleaveBanks_D: Status 1000
\r
249 InterleaveBanks_D: ErrStatus 0
\r
250 InterleaveBanks_D: ErrCode 0
\r
251 InterleaveBanks_D: Done
\r
253 AutoConfig_D: DramControl: 2a06
\r
254 AutoConfig_D: DramTimingLo: 90092
\r
255 AutoConfig_D: DramConfigMisc: 0
\r
256 AutoConfig_D: DramConfigMisc2: 0
\r
257 AutoConfig_D: DramConfigLo: 10000
\r
258 AutoConfig_D: DramConfigHi: f40000b
\r
259 AutoConfig: Status 1000
\r
260 AutoConfig: ErrStatus 0
\r
261 AutoConfig: ErrCode 0
\r
264 DCTInit_D: AutoConfig_D Done
\r
265 DCTInit_D: PlatformSpec_D Done
\r
266 DCTInit_D: StartupDCT_D
\r
267 mctAutoInitMCT_D: SyncDCTsReady_D
\r
268 mctAutoInitMCT_D: HTMemMapInit_D
\r
269 Node: 00 base: 00 limit: 1ffffff BottomIO: c00000
\r
270 Node: 00 base: 03 limit: 23fffff
\r
271 Node: 01 base: 00 limit: 00
\r
272 Node: 02 base: 00 limit: 00
\r
273 Node: 03 base: 00 limit: 00
\r
274 Node: 04 base: 00 limit: 00
\r
275 Node: 05 base: 00 limit: 00
\r
276 Node: 06 base: 00 limit: 00
\r
277 Node: 07 base: 00 limit: 00
\r
278 mctAutoInitMCT_D: CPUMemTyping_D
\r
279 CPUMemTyping: Cache32bTOP:c00000
\r
280 CPUMemTyping: Bottom32bIO:c00000
\r
281 CPUMemTyping: Bottom40bIO:2400000
\r
282 mctAutoInitMCT_D: DQSTiming_D
\r
283 TrainRcvrEn: Status 1100
\r
284 TrainRcvrEn: ErrStatus 0
\r
285 TrainRcvrEn: ErrCode 0
\r
288 TrainDQSRdWrPos: Status 1100
\r
289 TrainDQSRdWrPos: TrainErrors 0
\r
290 TrainDQSRdWrPos: ErrStatus 0
\r
291 TrainDQSRdWrPos: ErrCode 0
\r
292 TrainDQSRdWrPos: Done
\r
294 TrainDQSRdWrPos: Status 1100
\r
295 TrainDQSRdWrPos: TrainErrors 0
\r
296 TrainDQSRdWrPos: ErrStatus 0
\r
297 TrainDQSRdWrPos: ErrCode 0
\r
298 TrainDQSRdWrPos: Done
\r
300 TrainDQSRdWrPos: Status 1100
\r
301 TrainDQSRdWrPos: TrainErrors 0
\r
302 TrainDQSRdWrPos: ErrStatus 0
\r
303 TrainDQSRdWrPos: ErrCode 0
\r
304 TrainDQSRdWrPos: Done
\r
306 TrainDQSRdWrPos: Status 1100
\r
307 TrainDQSRdWrPos: TrainErrors 0
\r
308 TrainDQSRdWrPos: ErrStatus 0
\r
309 TrainDQSRdWrPos: ErrCode 0
\r
310 TrainDQSRdWrPos: Done
\r
312 mctAutoInitMCT_D: UMAMemTyping_D
\r
313 mctAutoInitMCT_D: :OtherTiming
\r
314 InterleaveNodes_D: Status 1100
\r
315 InterleaveNodes_D: ErrStatus 0
\r
316 InterleaveNodes_D: ErrCode 0
\r
317 InterleaveNodes_D: Done
\r
319 InterleaveChannels_D: Node 0
\r
320 InterleaveChannels_D: Status 1100
\r
321 InterleaveChannels_D: ErrStatus 0
\r
322 InterleaveChannels_D: ErrCode 0
\r
323 InterleaveChannels_D: Node 1
\r
324 InterleaveChannels_D: Status 1000
\r
325 InterleaveChannels_D: ErrStatus 0
\r
326 InterleaveChannels_D: ErrCode 0
\r
327 InterleaveChannels_D: Node 2
\r
328 InterleaveChannels_D: Status 1000
\r
329 InterleaveChannels_D: ErrStatus 0
\r
330 InterleaveChannels_D: ErrCode 0
\r
331 InterleaveChannels_D: Node 3
\r
332 InterleaveChannels_D: Status 1000
\r
333 InterleaveChannels_D: ErrStatus 0
\r
334 InterleaveChannels_D: ErrCode 0
\r
335 InterleaveChannels_D: Node 4
\r
336 InterleaveChannels_D: Status 1000
\r
337 InterleaveChannels_D: ErrStatus 0
\r
338 InterleaveChannels_D: ErrCode 0
\r
339 InterleaveChannels_D: Node 5
\r
340 InterleaveChannels_D: Status 1000
\r
341 InterleaveChannels_D: ErrStatus 0
\r
342 InterleaveChannels_D: ErrCode 0
\r
343 InterleaveChannels_D: Node 6
\r
344 InterleaveChannels_D: Status 1000
\r
345 InterleaveChannels_D: ErrStatus 0
\r
346 InterleaveChannels_D: ErrCode 0
\r
347 InterleaveChannels_D: Node 7
\r
348 InterleaveChannels_D: Status 1000
\r
349 InterleaveChannels_D: ErrStatus 0
\r
350 InterleaveChannels_D: ErrCode 0
\r
351 InterleaveChannels_D: Done
\r
353 mctAutoInitMCT_D: ECCInit_D
\r
355 raminit_amdmct end:
\r
360 Copying data from cache to RAM -- switching to use RAM as stack... Done
\r
362 Disabling cache as ram now
\r
363 Clearing initial memory region: Done
\r
365 Searching for fallback/coreboot_ram
\r
366 Check cmos_layout.bin
\r
367 Check fallback/romstage
\r
368 Check fallback/coreboot_ram
\r
369 Stage: loading fallback/coreboot_ram @ 0x200000 (1277952 bytes), entry @ 0x200000
\r
370 Stage: done loading.
\r
374 coreboot-4.0-2026-g15127e2-dirty Wed Feb 8 14:48:08 CET 2012 booting...
\r
376 Enumerating buses...
\r
377 Show all devs...Before device enumeration.
\r
378 Root Device: enabled 1
\r
379 APIC_CLUSTER: 0: enabled 1
\r
380 APIC: 00: enabled 1
\r
381 PCI_DOMAIN: 0000: enabled 1
\r
382 PCI: 00:18.0: enabled 1
\r
383 PCI: 00:00.0: enabled 1
\r
384 PCI: 00:02.0: enabled 1
\r
385 PCI: 00:03.0: enabled 0
\r
386 PCI: 00:04.0: enabled 1
\r
387 PCI: 00:05.0: enabled 0
\r
388 PCI: 00:06.0: enabled 0
\r
389 PCI: 00:07.0: enabled 0
\r
390 PCI: 00:08.0: enabled 0
\r
391 PCI: 00:09.0: enabled 1
\r
392 PCI: 00:0a.0: enabled 1
\r
393 PCI: 00:11.0: enabled 1
\r
394 PCI: 00:12.0: enabled 1
\r
395 PCI: 00:12.2: enabled 1
\r
396 PCI: 00:13.0: enabled 1
\r
397 PCI: 00:13.2: enabled 1
\r
398 PCI: 00:14.0: enabled 1
\r
399 I2C: 00:50: enabled 1
\r
400 I2C: 00:51: enabled 1
\r
401 I2C: 00:52: enabled 1
\r
402 I2C: 00:53: enabled 1
\r
403 PCI: 00:14.1: enabled 1
\r
404 PCI: 00:14.2: enabled 1
\r
405 PCI: 00:14.3: enabled 1
\r
406 PNP: 002e.0: enabled 0
\r
407 PNP: 002e.1: enabled 0
\r
408 PNP: 002e.2: enabled 1
\r
409 PNP: 002e.3: enabled 1
\r
410 PNP: 002e.5: enabled 1
\r
411 PNP: 002e.6: enabled 0
\r
412 PNP: 002e.7: enabled 0
\r
413 PNP: 002e.8: enabled 0
\r
414 PNP: 002e.9: enabled 0
\r
415 PNP: 002e.a: enabled 0
\r
416 PNP: 002e.b: enabled 1
\r
417 PCI: 00:14.4: enabled 0
\r
418 PCI: 00:14.5: enabled 1
\r
419 PCI: 00:14.6: enabled 0
\r
420 PCI: 00:15.0: enabled 1
\r
421 PCI: 00:15.1: enabled 1
\r
422 PCI: 00:15.2: enabled 1
\r
423 PCI: 00:15.3: enabled 1
\r
424 PCI: 00:16.0: enabled 1
\r
425 PCI: 00:16.2: enabled 1
\r
426 PCI: 00:18.1: enabled 1
\r
427 PCI: 00:18.2: enabled 1
\r
428 PCI: 00:18.3: enabled 1
\r
429 PCI: 00:18.4: enabled 1
\r
430 Compare with tree...
\r
431 Root Device: enabled 1
\r
432 APIC_CLUSTER: 0: enabled 1
\r
433 APIC: 00: enabled 1
\r
434 PCI_DOMAIN: 0000: enabled 1
\r
435 PCI: 00:18.0: enabled 1
\r
436 PCI: 00:00.0: enabled 1
\r
437 PCI: 00:02.0: enabled 1
\r
438 PCI: 00:03.0: enabled 0
\r
439 PCI: 00:04.0: enabled 1
\r
440 PCI: 00:05.0: enabled 0
\r
441 PCI: 00:06.0: enabled 0
\r
442 PCI: 00:07.0: enabled 0
\r
443 PCI: 00:08.0: enabled 0
\r
444 PCI: 00:09.0: enabled 1
\r
445 PCI: 00:0a.0: enabled 1
\r
446 PCI: 00:11.0: enabled 1
\r
447 PCI: 00:12.0: enabled 1
\r
448 PCI: 00:12.2: enabled 1
\r
449 PCI: 00:13.0: enabled 1
\r
450 PCI: 00:13.2: enabled 1
\r
451 PCI: 00:14.0: enabled 1
\r
452 I2C: 00:50: enabled 1
\r
453 I2C: 00:51: enabled 1
\r
454 I2C: 00:52: enabled 1
\r
455 I2C: 00:53: enabled 1
\r
456 PCI: 00:14.1: enabled 1
\r
457 PCI: 00:14.2: enabled 1
\r
458 PCI: 00:14.3: enabled 1
\r
459 PNP: 002e.0: enabled 0
\r
460 PNP: 002e.1: enabled 0
\r
461 PNP: 002e.2: enabled 1
\r
462 PNP: 002e.3: enabled 1
\r
463 PNP: 002e.5: enabled 1
\r
464 PNP: 002e.6: enabled 0
\r
465 PNP: 002e.7: enabled 0
\r
466 PNP: 002e.8: enabled 0
\r
467 PNP: 002e.9: enabled 0
\r
468 PNP: 002e.a: enabled 0
\r
469 PNP: 002e.b: enabled 1
\r
470 PCI: 00:14.4: enabled 0
\r
471 PCI: 00:14.5: enabled 1
\r
472 PCI: 00:14.6: enabled 0
\r
473 PCI: 00:15.0: enabled 1
\r
474 PCI: 00:15.1: enabled 1
\r
475 PCI: 00:15.2: enabled 1
\r
476 PCI: 00:15.3: enabled 1
\r
477 PCI: 00:16.0: enabled 1
\r
478 PCI: 00:16.2: enabled 1
\r
479 PCI: 00:18.1: enabled 1
\r
480 PCI: 00:18.2: enabled 1
\r
481 PCI: 00:18.3: enabled 1
\r
482 PCI: 00:18.4: enabled 1
\r
483 Mainboard ASUS M5A99X-EVO Enable. dev=0x002324c0
\r
484 Enumerating buses... starting with root now
\r
485 scan_static_bus for Root Device
\r
486 APIC_CLUSTER: 0 enabled
\r
487 PCI_DOMAIN: 0000 enabled
\r
488 APIC_CLUSTER: 0 scanning...
\r
489 cpu_bus_scan: starting...
\r
490 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
491 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
492 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
493 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
494 PCI: 00:18.3 siblings=5
\r
495 CPU: APIC: 00 enabled
\r
496 CPU: APIC: 01 enabled
\r
497 CPU: APIC: 02 enabled
\r
498 CPU: APIC: 03 enabled
\r
499 CPU: APIC: 04 enabled
\r
500 CPU: APIC: 05 enabled
\r
501 cpu_bus_scan: done.
\r
502 PCI_DOMAIN: 0000 scanning...
\r
503 PCI: pci_scan_bus for bus 00
\r
505 pci_scan_bus: before pci_scan_get_dev! devfn: 192
\r
506 pci_scan_bus: after pci_scan_get_dev!
\r
507 pci_scan_bus: before pci_probe_dev!
\r
508 pci_probe_dev: ohai, non-dummy stuff!
\r
509 pci_probe_dev: before enable! 0x00000000
\r
510 pci_probe_dev: before read!
\r
511 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
512 pci_probe_dev: after read: 0x12001022
\r
513 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
514 PCI: 00:18.0 [1022/1200] bus ops
\r
515 PCI: 00:18.0 [1022/1200] enabled
\r
516 pci_scan_bus: after pci_probe_dev!
\r
518 pci_scan_bus: before pci_scan_get_dev! devfn: 193
\r
519 pci_scan_bus: after pci_scan_get_dev!
\r
520 pci_scan_bus: before pci_probe_dev!
\r
521 pci_probe_dev: ohai, non-dummy stuff!
\r
522 pci_probe_dev: before enable! 0x00000000
\r
523 pci_probe_dev: before read!
\r
524 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
525 pci_probe_dev: after read: 0x12011022
\r
526 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
527 PCI: 00:18.1 [1022/1201] enabled
\r
528 pci_scan_bus: after pci_probe_dev!
\r
530 pci_scan_bus: before pci_scan_get_dev! devfn: 194
\r
531 pci_scan_bus: after pci_scan_get_dev!
\r
532 pci_scan_bus: before pci_probe_dev!
\r
533 pci_probe_dev: ohai, non-dummy stuff!
\r
534 pci_probe_dev: before enable! 0x00000000
\r
535 pci_probe_dev: before read!
\r
536 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
537 pci_probe_dev: after read: 0x12021022
\r
538 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
539 PCI: 00:18.2 [1022/1202] enabled
\r
540 pci_scan_bus: after pci_probe_dev!
\r
542 pci_scan_bus: before pci_scan_get_dev! devfn: 195
\r
543 pci_scan_bus: after pci_scan_get_dev!
\r
544 pci_scan_bus: before pci_probe_dev!
\r
545 pci_probe_dev: ohai, non-dummy stuff!
\r
546 pci_probe_dev: before enable! 0x00000000
\r
547 pci_probe_dev: before read!
\r
548 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
549 pci_probe_dev: after read: 0x12031022
\r
550 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
551 PCI: 00:18.3 [1022/1203] ops
\r
552 PCI: 00:18.3 [1022/1203] enabled
\r
553 pci_scan_bus: after pci_probe_dev!
\r
555 pci_scan_bus: before pci_scan_get_dev! devfn: 196
\r
556 pci_scan_bus: after pci_scan_get_dev!
\r
557 pci_scan_bus: before pci_probe_dev!
\r
558 pci_probe_dev: ohai, non-dummy stuff!
\r
559 pci_probe_dev: before enable! 0x00000000
\r
560 pci_probe_dev: before read!
\r
561 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
562 pci_probe_dev: after read: 0x12041022
\r
563 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
564 PCI: 00:18.4 [1022/1204] enabled
\r
565 pci_scan_bus: after pci_probe_dev!
\r
567 pci_scan_bus: before pci_scan_get_dev! devfn: 197
\r
568 pci_scan_bus: after pci_scan_get_dev!
\r
569 pci_scan_bus: before pci_probe_dev!
\r
570 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
571 pci_scan_bus: after pci_probe_dev!
\r
573 pci_scan_bus: before pci_scan_get_dev! devfn: 198
\r
574 pci_scan_bus: after pci_scan_get_dev!
\r
575 pci_scan_bus: before pci_probe_dev!
\r
576 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
577 pci_scan_bus: after pci_probe_dev!
\r
579 pci_scan_bus: before pci_scan_get_dev! devfn: 199
\r
580 pci_scan_bus: after pci_scan_get_dev!
\r
581 pci_scan_bus: before pci_probe_dev!
\r
582 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
583 pci_scan_bus: after pci_probe_dev!
\r
585 pci_scan_bus: before pci_scan_get_dev! devfn: 200
\r
586 pci_scan_bus: after pci_scan_get_dev!
\r
587 pci_scan_bus: before pci_probe_dev!
\r
588 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
589 pci_scan_bus: after pci_probe_dev!
\r
590 pci_scan_bus: ohai, +7
\r
592 pci_scan_bus: before pci_scan_get_dev! devfn: 208
\r
593 pci_scan_bus: after pci_scan_get_dev!
\r
594 pci_scan_bus: before pci_probe_dev!
\r
595 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
596 pci_scan_bus: after pci_probe_dev!
\r
597 pci_scan_bus: ohai, +7
\r
599 pci_scan_bus: before pci_scan_get_dev! devfn: 216
\r
600 pci_scan_bus: after pci_scan_get_dev!
\r
601 pci_scan_bus: before pci_probe_dev!
\r
602 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
603 pci_scan_bus: after pci_probe_dev!
\r
604 pci_scan_bus: ohai, +7
\r
606 pci_scan_bus: before pci_scan_get_dev! devfn: 224
\r
607 pci_scan_bus: after pci_scan_get_dev!
\r
608 pci_scan_bus: before pci_probe_dev!
\r
609 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
610 pci_scan_bus: after pci_probe_dev!
\r
611 pci_scan_bus: ohai, +7
\r
613 pci_scan_bus: before pci_scan_get_dev! devfn: 232
\r
614 pci_scan_bus: after pci_scan_get_dev!
\r
615 pci_scan_bus: before pci_probe_dev!
\r
616 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
617 pci_scan_bus: after pci_probe_dev!
\r
618 pci_scan_bus: ohai, +7
\r
620 pci_scan_bus: before pci_scan_get_dev! devfn: 240
\r
621 pci_scan_bus: after pci_scan_get_dev!
\r
622 pci_scan_bus: before pci_probe_dev!
\r
623 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
624 pci_scan_bus: after pci_probe_dev!
\r
625 pci_scan_bus: ohai, +7
\r
627 pci_scan_bus: before pci_scan_get_dev! devfn: 248
\r
628 pci_scan_bus: after pci_scan_get_dev!
\r
629 pci_scan_bus: before pci_probe_dev!
\r
630 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
631 pci_scan_bus: after pci_probe_dev!
\r
632 pci_scan_bus: ohai, +7
\r
635 amdfam10_scan_chains: starting...
\r
636 amdfam10_scan_chains: link: 00232834
\r
637 amdfam10_scan_chain: starting...
\r
638 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
639 amdfam10_scan_chain: link_type: 0x00000007
\r
640 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
641 amdfam10_scan_chain: link_type: 0x00000007
\r
642 amdfam10_scan_chain: before get_ht_c_index
\r
643 amdfam10_scan_chain: after get_ht_c_index
\r
644 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
645 amdfam10_scan_chain: before set_config_map_reg
\r
646 amdfam10_scan_chain: after set_config_map_reg
\r
647 amdfam10_scan_chain: before hypertransport_scan_chain
\r
648 hypertransport_scan_chain: before ht_collapse_early_enumeration
\r
649 hypertransport_scan_chain: after ht_collapse_early_enumeration
\r
650 hypertransport_scan_chain: before ht_scan_get_devs
\r
651 hypertransport_scan_chain: after ht_scan_get_devs
\r
652 hypertransport_scan_chain: before pci_probe_dev
\r
653 pci_probe_dev: ohai, non-dummy stuff!
\r
654 pci_probe_dev: before enable! 0x00205d54
\r
655 pci_probe_dev: we're going to call enable stuff?
\r
656 rs780_enable: WHAT THE FUCK
\r
657 PCI: Using configuration type 1
\r
658 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
659 rs780_enable: dev=00232a8c, VID_DID=0x5a141002
\r
660 Bus-0, Dev-0, Fun-0.
\r
662 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
663 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
664 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
665 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
666 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
667 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
668 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
669 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
670 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
671 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
672 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
673 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
674 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
675 addr=e0000000,bus=0,devfn=40
\r
676 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
677 gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
\r
678 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
679 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
680 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
681 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
682 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
683 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
684 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
685 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
686 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
687 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
688 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
689 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
690 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
691 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
692 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
693 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
694 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
695 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
696 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
697 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
698 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
699 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
700 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
701 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
702 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
703 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
704 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
705 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
706 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
707 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
708 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
709 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
710 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
711 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
712 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
713 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
715 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
716 NB_PCI_REG84 = 3000095.
\r
717 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
718 NB_PCI_REG4C = 52042.
\r
720 pci_probe_dev: before read!
\r
721 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
722 pci_probe_dev: after read: 0x5a141002
\r
723 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
724 PCI: 00:00.0 [1002/5a14] enabled
\r
725 hypertransport_scan_chain: after pci_probe_dev
\r
726 hypertransport_scan_chain: before ht_lookup_slave_capability
\r
727 Capability: type 0x08 @ 0xf0
\r
729 Capability: type 0x08 @ 0xf0
\r
730 Capability: type 0x08 @ 0xc4
\r
732 hypertransport_scan_chain: after ht_lookup_slave_capability
\r
733 hypertransport_scan_chain: end_of_chain. w00t!
\r
734 hypertransport_scan_chain: before pci_scan_bus!
\r
735 PCI: pci_scan_bus for bus 00
\r
736 PCI: pci_scan_bus limits devfn 0 - devfn ffffffff
\r
737 PCI: pci_scan_bus upper limit too big. Using 0xff.
\r
739 pci_scan_bus: before pci_scan_get_dev! devfn: 0
\r
740 pci_scan_bus: after pci_scan_get_dev!
\r
741 pci_scan_bus: before pci_probe_dev!
\r
742 pci_probe_dev: ohai, non-dummy stuff!
\r
743 pci_probe_dev: before enable! 0x00205d54
\r
744 pci_probe_dev: we're going to call enable stuff?
\r
745 rs780_enable: WHAT THE FUCK
\r
746 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
747 rs780_enable: dev=00232a8c, VID_DID=0x5a141002
\r
748 Bus-0, Dev-0, Fun-0.
\r
750 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
751 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
752 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
753 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206dd6
\r
754 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
755 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
756 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
757 gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
\r
758 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
759 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
760 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
761 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
762 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
763 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
764 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
765 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
766 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
767 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
768 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
769 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
770 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
771 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
772 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
773 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
774 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
775 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
776 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
777 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
778 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
779 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
780 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
781 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
782 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
783 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
784 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
785 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
786 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
787 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
788 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
789 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
790 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
791 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
792 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
793 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
795 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
796 NB_PCI_REG84 = 3000095.
\r
797 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
798 NB_PCI_REG4C = 52042.
\r
800 pci_probe_dev: before read!
\r
801 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
802 pci_probe_dev: after read: 0x5a141002
\r
803 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
804 PCI: 00:00.0 [1002/5a14] enabled
\r
805 pci_scan_bus: after pci_probe_dev!
\r
807 pci_scan_bus: before pci_scan_get_dev! devfn: 1
\r
808 pci_scan_bus: after pci_scan_get_dev!
\r
809 pci_scan_bus: before pci_probe_dev!
\r
810 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
811 pci_scan_bus: after pci_probe_dev!
\r
813 pci_scan_bus: before pci_scan_get_dev! devfn: 2
\r
814 pci_scan_bus: after pci_scan_get_dev!
\r
815 pci_scan_bus: before pci_probe_dev!
\r
816 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
817 pci_scan_bus: after pci_probe_dev!
\r
819 pci_scan_bus: before pci_scan_get_dev! devfn: 3
\r
820 pci_scan_bus: after pci_scan_get_dev!
\r
821 pci_scan_bus: before pci_probe_dev!
\r
822 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
823 pci_scan_bus: after pci_probe_dev!
\r
825 pci_scan_bus: before pci_scan_get_dev! devfn: 4
\r
826 pci_scan_bus: after pci_scan_get_dev!
\r
827 pci_scan_bus: before pci_probe_dev!
\r
828 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
829 pci_scan_bus: after pci_probe_dev!
\r
831 pci_scan_bus: before pci_scan_get_dev! devfn: 5
\r
832 pci_scan_bus: after pci_scan_get_dev!
\r
833 pci_scan_bus: before pci_probe_dev!
\r
834 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
835 pci_scan_bus: after pci_probe_dev!
\r
837 pci_scan_bus: before pci_scan_get_dev! devfn: 6
\r
838 pci_scan_bus: after pci_scan_get_dev!
\r
839 pci_scan_bus: before pci_probe_dev!
\r
840 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
841 pci_scan_bus: after pci_probe_dev!
\r
843 pci_scan_bus: before pci_scan_get_dev! devfn: 7
\r
844 pci_scan_bus: after pci_scan_get_dev!
\r
845 pci_scan_bus: before pci_probe_dev!
\r
846 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
847 pci_scan_bus: after pci_probe_dev!
\r
849 pci_scan_bus: before pci_scan_get_dev! devfn: 8
\r
850 pci_scan_bus: after pci_scan_get_dev!
\r
851 pci_scan_bus: before pci_probe_dev!
\r
852 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r
853 pci_scan_bus: after pci_probe_dev!
\r
854 pci_scan_bus: ohai, +7
\r
856 pci_scan_bus: before pci_scan_get_dev! devfn: 16
\r
857 pci_scan_bus: after pci_scan_get_dev!
\r
858 pci_scan_bus: before pci_probe_dev!
\r
859 pci_probe_dev: ohai, non-dummy stuff!
\r
860 pci_probe_dev: before enable! 0x00205d54
\r
861 pci_probe_dev: we're going to call enable stuff?
\r
862 rs780_enable: WHAT THE FUCK
\r
863 pci_read_config32: ops_pci_bus(pbus)->read32: 0x00206c7f
\r