variable mem_op : std_logic;\r
variable alu_jump : std_logic;\r
variable nop : std_logic;\r
+ \r
+ variable pinc_v, pwr_en_v : std_logic;\r
+ \r
+ variable prog_cnt_nxt : std_logic_vector(prog_cnt'range);\r
begin\r
result_v := alu_state;\r
\r
addr <= add_result.result;\r
data <= right_operand;\r
\r
- pinc <= '0';\r
- pwr_en <= '0';\r
+ pinc_v := '0';\r
+ pwr_en_v := '0';\r
+ \r
paddr <= (others =>'0');\r
\r
result_v.result := add_result.result;\r
-\r
+ prog_cnt_nxt := std_logic_vector(unsigned(prog_cnt)+1);\r
case cond is\r
when COND_NZERO =>\r
cond_met := not(alu_state.status.zero);\r
left_o <= prog_cnt;\r
end if;\r
alu_jump := '1';\r
- when JMP_ST_OP => null;\r
+ when JMP_ST_OP => \r
+ left_o <= prog_cnt;\r
+ men_en := '1';\r
+ alu_jump := '1';\r
+ men_op := '1';\r
+ pinc_v := '1';\r
+ pinc_wr_en := '1';\r
+ paddr <= (others =>'0');\r
+ \r
+ addr <= pval;\r
+ data <= prog_cnt_nxt;\r
+ -- if(op_detail(RET_OPT) = '1' then\r
+ -- null;\r
+ -- end if;\r
\r
end case;\r
\r
result_v.mem_op := mem_op and cond_met;\r
result_v.alu_jump := alu_jump and cond_met;\r
result_v.brpr := brpr and nop;\r
+ \r
+ pwr_en_v := pwr_en_v and cond_met;\r
\r
if (result_v.alu_jump = '0') and (brpr = '1') then\r
result_v.result := (others => '0');\r
- result_v.result(prog_cnt'range) := std_logic_vector(unsigned(prog_cnt)+1);\r
+ result_v.result(prog_cnt'range) := prog_cnt_nxt;\r
--result_v.reg_op := '1';\r
end if;\r
\r
alu_result <= result_v;\r
+ pinc <= pinc_v;\r
+ pwr_en <= pwr_en_v;\r
\r
end process calc; \r
\r
constant RIGHT_OPT : integer := 3;
constant JMP_REG_OPT : integer := 3;
- constant ST_OPT : integer := 3;
+ constant ST_OPT : integer := 3; -- store opt
+ constant RET_OPT : integer := 3;
constant NO_PSW_OPT : integer := 4;--no sharing
constant NO_DST_OPT : integer := 5; --no sharing