architecture behav of writeback_stage is
signal data_ram_read, data_ram_read_ext : word_t;
+signal data_addr : word_t;
signal wb_reg, wb_reg_nxt : writeback_rec;
port map (
clk,
- wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
- wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
+ data_addr(DATA_ADDR_WIDTH+1 downto 2),
+ data_addr(DATA_ADDR_WIDTH+1 downto 2),
wb_reg_nxt.dmem_write_en,
ram_data,
data_ram_read
-out_logic: process(write_en, result_addr, wb_reg, alu_jmp)
+out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt)
begin
reg_we <= (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
reg_addr <= result_addr;
+
+ data_addr <= (others => '0');
+
+ if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) = '1') then
+ data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
+ end if;
end process;