isa: working version

diff --git a/2_isa/Makefile b/2_isa/Makefile
index 3995bc9ee85c767f4a0dc09530abdc977643a2bc..4f9406c45c411b9730e3a0c47cd23c6f06f2027a 100644 (file)
--- a/2_isa/Makefile
+++ b/2_isa/Makefile
@@ -1,6 +1,6 @@
 SHELL := bash
 
-FILES  = isa.tex conds.tex
+FILES  = isa.tex conds.tex flags.tex callingconv.tex
 FILES += Makefile
 TARGET = isa.pdf
 

diff --git a/2_isa/arith.ptex b/2_isa/arith.ptex
index 5abb0aca848bad25b6a986a49ef8168fbd5bc506..54075b7c827a496e722ad77dceb31ef77066af8f 100644 (file)
--- a/2_isa/arith.ptex
+++ b/2_isa/arith.ptex
@@ -1,20 +1,21 @@
 ins ('32', 'add', 'Add',
-'4 | 5 | 4 | 4 | 4 | 10 | 1',
-'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | C',
+'4 | 5 | 4 | 4 | 4 | 9 | 1 | 1',
+'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | C | SU',
 'Adds Register A and Register B and save result in Register Destination \\\\
-When bit C is set, the content of the carry flag is also added.',
+When bit C is set, the content of the carry flag is also added. When the SU bit is set, the PSW gets updated (default is set)',
 'is set to the MSB of the result | is set if addition has a carry out | is set if a overflow occured | is set if the result is zero ',
 'add  r0, r2, r4 ; add low bytes
  addc r1, r3, r5 ; add high bytes');
 
-ins ('32', 'addi', 'Add im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | S | C');
+ins ('32', 'addi', 'Add im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | S | C',
+'H/L oder C kommen raus, daf\\"ur SU rein');
 
-ins ('32', 'addx', 'Add im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | S | C');
+# ins ('32', 'addx', 'Add im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | S | C');
 
-ins ('32', 'sub', 'Sub', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | C');
+ins ('32', 'sub', 'Sub', '4 | 5 | 4 | 4 | 4 | 9 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | C | SU');
 
 ins ('32', 'subi', 'Sub im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | S | C');
 
-ins ('32', 'subx', 'Sub im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | S | C');
+# ins ('32', 'subx', 'Sub im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | S | C');
 
 

diff --git a/2_isa/callingconv.tex b/2_isa/callingconv.tex
new file mode 100644 (file)
index 0000000..c48a52f
--- /dev/null
+++ b/2_isa/callingconv.tex
@@ -0,0 +1,26 @@
+\section{calling convention}
+
+\begin{table}
+       \centering
+       \begin{tabular}{|c|c|c|} \hline
+               Register & saved by & usage  \\ \hline
+               r0       & caller   & return \\ \hline
+               r1       & caller   & first parameter \\ \hline
+               r2       & caller   & second parameter \\ \hline
+               r3       & caller   & third parameter \\ \hline
+               r4       & caller   & fourth parameter \\ \hline
+               r5       & caller   & fifth parameter \\ \hline
+               r6       & caller   & \\ \hline
+               r7       & caller   & \\ \hline
+               r8       & caller   & \\ \hline
+               r9       & caller   & \\ \hline
+               r10      & callee   & \\ \hline
+               r11      & callee   & \\ \hline
+               r12      & callee   & \\ \hline
+               r13      & callee   & \\ \hline
+               r14      & callee   & \\ \hline
+               r15      & callee   & \\ \hline
+       \end{tabular}
+       \caption{Register save \ldots}
+%      \label{tab:<+label+>}
+\end{table}

diff --git a/2_isa/common.sty b/2_isa/common.sty
index 4c55cb1f586874d4aa415b12865256ba79c3530c..648f14f4c812394119b7c364db1047f9c3149cf6 100644 (file)
--- a/2_isa/common.sty
+++ b/2_isa/common.sty
@@ -6,6 +6,8 @@
 \usepackage{listings}
 \usepackage{ngerman}
 
+\usepackage{longtable}
+
 %used for coloring of instr.
 \usepackage{colortbl}
 

diff --git a/2_isa/data.ptex b/2_isa/data.ptex
index 0dbde7543fbc965b9883195c26b9113149c69a92..dacbed66c96065ddc1ce38c15255410c3cbb0e51 100644 (file)
--- a/2_isa/data.ptex
+++ b/2_isa/data.ptex
@@ -1,6 +1,6 @@
-ins ('32', 'movpf', 'Move from PSW', '4 | 5 | 4 | 19', 'Conditions | OpCode | Register Destination| - ');
+ins ('32', 'movpf', 'Move from PSW/Stack', '4 | 5 | 4 | 1 | 18', 'Conditions | OpCode | Register Destination| stack | - ');
 
-ins ('32', 'movpt', 'Move to PSW', '4 | 5 | 4 | 19', 'Conditions | OpCode | Register Source| - ');
+ins ('32', 'movpt', 'Move to PSW', '4 | 5 | 4 | 1 | 18', 'Conditions | OpCode | Register Source | stack | - ');
 
 ins ('32', 'ldw', 'Load word; needs to be aligned to 32bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment? ');
 ins ('32', 'ldh', 'Load half word; needs to be aligned to 16bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment? ');
@@ -8,19 +8,21 @@ ins ('32', 'ldb', 'Load byte, 8bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode
 
 ins ('32', 'ldi', 'Load immediate', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | - | h/l | S ');
 
-ins ('32', 'stw', 'store word; needs to be aligned to 32bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| - ');
-ins ('32', 'sth', 'store half word; needs to be aligned to 16bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| - ');
-ins ('32', 'stb', 'store byte, 8bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| - ');
+ins ('32', 'stw', 'store word; needs to be aligned to 32bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment ');
+ins ('32', 'sth', 'store half word; needs to be aligned to 16bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment ');
+ins ('32', 'stb', 'store byte, 8bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment ');
 
 ins ('32', 'ldx', 'Load from programspace', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment ');
 
 ins ('32', 'stx', 'Store to programspace', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
 
 
-ins ('32', 'pop', 'pop from stack', '4 | 5 | 4 | 19', 'Conditions | OpCode | Register Destination | - ');
+ins ('32', 'stackop', 'pop/push/disc/fetch from/to stack', '4 | 5 | 4 | 2 | 17', 'Conditions | OpCode | Register Destination (not for disc) | Type | - ');
 
-ins ('32', 'push', 'push to stack', '4 | 5 | 4 |  19', 'Conditions | OpCode | Register Source | - ');
+#ins ('32', 'pop', 'pop from stack', '4 | 5 | 4 | 19', 'Conditions | OpCode | Register Destination | - ');
 
-ins ('32', 'disc', 'discard top-element from stack', '4 | 5 |  23', 'Conditions | OpCode | - ');
+#ins ('32', 'push', 'push to stack', '4 | 5 | 4 |  19', 'Conditions | OpCode | Register Source | - ');
 
-ins ('32', 'fetch', 'get top-element from stack', '4 | 5 | 4 |  19', 'Conditions | OpCode | Register Destination | - ');
+#ins ('32', 'disc', 'discard top-element from stack', '4 | 5 |  23', 'Conditions | OpCode | - ');
+
+#ins ('32', 'fetch', 'get top-element from stack', '4 | 5 | 4 |  19', 'Conditions | OpCode | Register Destination | - ');

diff --git a/2_isa/desdis.tex b/2_isa/desdis.tex
index 1ab7430c44f3869b4345e8833e1d196381ed0671..2f8a4448a45abcd0ffe77854864ebcf556d96d01 100644 (file)
--- a/2_isa/desdis.tex
+++ b/2_isa/desdis.tex
@@ -12,3 +12,5 @@ extension module vs. other
 
 see note in conditions. there is a difference between x86/amd64/avr and arm.
 we will very likely go with arm (or?)
+
+\subsection{big/little endian}

diff --git a/2_isa/flags.tex b/2_isa/flags.tex
new file mode 100644 (file)
index 0000000..52a3bc0
--- /dev/null
+++ b/2_isa/flags.tex
@@ -0,0 +1,13 @@
+\begin{table}
+       \centering
+       \begin{longtable}{|c|c|c|} \hline
+               flag & function & default value \\ \hline
+               C    & carry    & 0 (not set)   \\ \hline
+               SU   & Status register update & 1 (set) \\ \hline
+               H/L  & use high or low 16-bits & L (not set) \\ \hline
+               F    & fill unused 16-bits with value of F & 0 (not set)\footnotemark[1]\\ \hline
+       \end{longtable}
+       \footnotetext[1]{this means that andxf must be used if the not specified 16-bit should be preserve}
+       \caption{ISA flag overview}
+%\label{tab:<+label+>}
+\end{table}

diff --git a/2_isa/isa.tex b/2_isa/isa.tex
index f74a40c80f8ff0bebe7e32ba80a3b82a7bc19d26..52872ecf593b5c802fea5766391f687b88d4f92a 100644 (file)
--- a/2_isa/isa.tex
+++ b/2_isa/isa.tex
@@ -20,6 +20,7 @@
 if a condition is not met, the instruction is executed but no changes (on data or flags) occure.
 \clearpage
 \section{instr}
+\input{flags}
 
 \subsection{arith}
 modifies all flags

diff --git a/2_isa/logic.ptex b/2_isa/logic.ptex
index 4d6b7f02035afd377e06c732f7f3f24564ec030b..02f3b0e654f42a6f4ca852fe4a7c6651c3d39ed7 100644 (file)
--- a/2_isa/logic.ptex
+++ b/2_isa/logic.ptex
@@ -1,23 +1,23 @@
 
 
-ins ('32', 'and', 'And', '4 | 5 | 4 | 4 | 4 | 11', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | -');
+ins ('32', 'and', 'And', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | SU');
 
-ins ('32', 'andi', 'And im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
+# ins ('32', 'andi', 'And im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
 
-ins ('32', 'andx', 'And im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | -');
+ins ('32', 'andx', 'And im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | SU');
 
-ins ('32', 'or', 'Or', '4 | 5 | 4 | 4 | 4 | 11', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | -');
+ins ('32', 'or', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | SU');
 
-ins ('32', 'ori', 'Or im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
+# ins ('32', 'ori', 'Or im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
 
-ins ('32', 'orx', 'Or im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | -');
+ins ('32', 'orx', 'Or im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | SU');
 
-ins ('32', 'xor', 'Or', '4 | 5 | 4 | 4 | 4 | 11', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | -');
+ins ('32', 'xor', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | SU');
 
-ins ('32', 'xori', 'Xor im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
+# ins ('32', 'xori', 'Xor im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
 
-ins ('32', 'xorx', 'Xor im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | -');
+ins ('32', 'xorx', 'Xor im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | SU');
 
-ins ('32', 'lls', 'left shift', '4 | 5 | 4 | 4 | 5 | 9 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | C');
+ins ('32', 'lls', 'left shift', '4 | 5 | 4 | 4 | 5 | 8 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | C | SU');
 
-ins ('32', 'lrs', 'right shift', '4 | 5 | 4 | 4 | 5 | 8 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | ARITH | C');
+ins ('32', 'lrs', 'right shift', '4 | 5 | 4 | 4 | 5 | 7 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | ARITH | C | SU');

diff --git a/2_isa/misc.ptex b/2_isa/misc.ptex
index 951e2b5ad24fbed6261886aa168899c9dd056002..cc3af7e568825a6c8a49939f6fa332da994d58d8 100644 (file)
--- a/2_isa/misc.ptex
+++ b/2_isa/misc.ptex
@@ -1,12 +1,14 @@
-ins ('32', 'branch', 'Branch; save pc+4 in stack, jump to pc+imm', '4 | 5 | 16 | 5 | 1 | 1', 'Conditions | OpCode | Immediate | - | +/- | S');
+ins ('32', 'branch', 'Branch; jump to pc+imm', '4 | 5 | 16 | 3 | 2 | 1 | 1', 'Conditions | OpCode | Immediate | - | Branch/Call/Ret(i) | +/- | S');
 
-ins ('32', 'jump', 'Jump; jump to pc+imm', '4 | 5 | 16 | 5 | 1 | 1', 'Conditions | OpCode | Immediate | - | +/- | S');
+#ins ('32', 'call', 'Call; save pc+4 in stack, jump to pc+imm', '4 | 5 | 16 | 5 | 1 | 1', 'Conditions | OpCode | Immediate | - | +/- | S');
 
-ins ('32', 'jumpreg', 'Jump; jump to value of reg', '4 | 5 | 4 | 17 | 1 | 1', 'Conditions | OpCode | Register Source| - | +/- | S');
+#ins ('32', 'branchreg', 'Branch; branch to value of reg', '4 | 5 | 4 | 17 | 1 | 1', 'Conditions | OpCode | Register Source| - | +/- | S');
 
-ins ('32', 'ret', 'ret', '4 | 5 | 23 ', 'Conditions | OpCode | -');
+#ins ('32', 'ret(i)', 'return (from interrupt)', '4 | 5 | 1 | 22 ', 'Conditions | OpCode | I |-');
 
-ins ('32', 'reti', 'reti', '4 | 5 | 23 ', 'Conditions | OpCode | -');
+#ins ('32', 'ret', 'ret', '4 | 5 | 23 ', 'Conditions | OpCode | -');
+
+#ins ('32', 'reti', 'reti', '4 | 5 | 23 ', 'Conditions | OpCode | -');
 
 ins ('32', 'cmp', 'compare (rS1 - rS2)', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register A (Source1) | Register B (Source2) | -');