SHELL := bash
-FILES = isa.tex conds.tex flags.tex callingconv.tex
+FILES = isa.tex conds.tex flags.tex callingconv.tex cmp.tex
FILES += Makefile
TARGET = isa.pdf
ins ('32', 'add', 'Add',
'4 | 5 | 4 | 4 | 4 | 9 | 1 | 1',
'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | C | SU',
-'Adds Register A and Register B and save result in Register Destination \\\\
-When bit C is set, the content of the carry flag is also added. When the SU bit is set, the PSW gets updated (default is set)',
-'is set to the MSB of the result | is set if addition has a carry out | is set if a overflow occured | is set if the result is zero ',
+'Adds register A and register B and saves the result in register Destination',
+'is set to the MSB of the result | is set if addition has a carry out | is set if a overflow occurred | is set if the result is zero ',
'add r0, r2, r4 ; add low bytes
addc r1, r3, r5 ; add high bytes');
ins ('32', 'addi', 'Add im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | S | C',
-'H/L oder C kommen raus, daf\\"ur SU rein');
+'Adds register A and immediate and saves the result in register Destination',
+'','',
+'mov rD, rS - addi rD, rS, 0');
# ins ('32', 'addx', 'Add im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | S | C');
-\section{calling convention}
+\section{Calling Convention}
+
+Programs and functions implementing this instruction set, should implement the following calling conventions. The register usage should be done as stated in table~\ref{tab:callcon}. If the callee should be given more than five parameters, other parameters should be passed over by the stack.
\begin{table}[ht]
\centering
\begin{tabular}{|c|c|c|} \hline
- Register & saved by & usage \\ \hline
+ register & saved by & usage \\ \hline
r0 & caller & return \\ \hline
r1 & caller & first parameter \\ \hline
r2 & caller & second parameter \\ \hline
r14 & callee & \\ \hline
r15 & callee & \\ \hline
\end{tabular}
- \caption{Register save \ldots}
-% \label{tab:<+label+>}
+ \caption{Calling Convention}
+ \label{tab:callcon}
\end{table}
-\subsection{Assembler Syntax}
+\subsection{Assembler Syntax}
\begin{itemize}
-\item \textbf{Immediates}: decimal \texttt{12345}, hex \texttt{0xabcde123},
+\item \textbf{Immediate s}: decimal \texttt{12345}, hex \texttt{0xabcde123},
binary \texttt{0b10101110}\\
If an immediate is to large for the given instruction the assembler terminates
with an error
\subsubsection{Directives}
In order to gain extra comfort, several directives are interpreted by the
-assembler:
+assembler, a list is given in table~\ref{tab:asmdirs}.
\begin{table}[ht]
\centering
\begin{tabular}{|l|p{10cm}|} \hline
%http://www.myri.com/scs/L3/doc/as_7.html#SEC85)
\end{tabular}
\caption{supported directives by the assembler}
-% \label{tab:<+label+>}
+ \label{tab:asmdirs}
\end{table}
--- /dev/null
+\section{Comparison}
+
+\subsection{Description of the ISA}
+\begin{itemize}
+ \item The ISA describe a register machine.
+ \item It is a RISC architecture.
+ \item All latencies are handled in the hardware and are not visible to the ISA level.
+ \item Conditional branches are unbundled, a branch only checks if the flags for the conditions are set properly.
+ \item In an FPGA :)
+ \item Be fast enough, to be faster than the other groups.
+ \item Predicated instructions, 16-bit immediates for logical instruction.
+ \item at the moment we are not aware of anything that we would like to change.
+\end{itemize}
+
+\subsection{Aim}
+Our approach was to cherry pick the best features, which can be easily implemented, of the ISA we compared in task 1.
+We took the predicated instructions like ARM is using them, static branch prediction which is used in PowerPC and extension modules like SPEAR2 uses.
+
+\subsection{Listing}
+\lstinputlisting[caption=sum Code]{src/sum.s}
+The Loop contains five instructions with each one cycle execution-time. The codesize is 20 Bytes because each instruction is 32-Bits big.
+
\section{Conditions}
+Every instruction can be predicated with a condition that will prevent the execution\footnote{The instruction will be executed, but no changes occur.} of the instruction iff the condition is not met. A list of available conditions, including the suffixes for the instruction, is shown in table~\ref{tab:conds}
+
+Above and below are for unsigned values. Greater and less for signed values.\\
+\textbf{Note:} The definition of tests of unsigned values (in the context of bits which will be tested) depends on the ISA. x86, AMD64 and AVR defines below (unsigned lower) as carry not set. ARM on the other hand defines below as carry set. We will follow the definition of arm in this manner.
+
\begin{table}[ht]
\centering
\begin{tabular}{|c|c|c|c|}\hline
- Bitcode & Condition & Bits to test & suffixes \\ \hline
- 0000 & not equal / not zero & ZF = 0 & nq, nz \\ \hline
- 0001 & equal / zero & ZF = 1 & eq, zs \\ \hline
- 0010 & not overflow & OF = 0 & no \\ \hline
- 0011 & overflow & OF = 1 & ov \\ \hline
- 0100 & not carry / above e q & CF = 0 & nc, ae \\ \hline
- 0101 & carry / below & CF = 1 & cs, bl \\ \hline
- 0110 & not signed / not neg. & SF = 0 & ns, nn \\ \hline
- 0111 & signed / neg. & SF = 1 & ss, ns \\ \hline
- 1000 & above & (CF == 0 $\wedge$ ZF == 0) & ab \\ \hline
- 1001 & below or equal & (CF == 1 $\vee$ ZF == 1) & be \\ \hline
- 1010 & greater than or equal & SF == OF & ge \\ \hline
- 1011 & less than & SF != OF & lt \\ \hline
- 1100 & greater than & (ZF == 0 $\wedge$ SF == OF) & gt \\ \hline
- 1101 & less than or equal & (ZF == 1 $\vee$ SF != OF) & le \\ \hline
- 1110 & always & & \texttt{none} \\ \hline
- 1111 & never & & nv \\ \hline
+ Bitcode & Condition & Bits to test & suffixes \\ \hline
+ 0000 & not equal / not zero & ZF = 0 & nq, nz \\ \hline
+ 0001 & equal / zero & ZF = 1 & eq, zs \\ \hline
+ 0010 & not overflow & OF = 0 & no \\ \hline
+ 0011 & overflow & OF = 1 & ov \\ \hline
+ 0100 & not carry / above or eq. & CF = 0 & nc, ae \\ \hline
+ 0101 & carry / below & CF = 1 & cs, bl \\ \hline
+ 0110 & not signed / not neg. & SF = 0 & ns, nn \\ \hline
+ 0111 & signed / neg. & SF = 1 & ss, ns \\ \hline
+ 1000 & above & (CF == 0 $\wedge$ ZF == 0) & ab \\ \hline
+ 1001 & below or equal & (CF == 1 $\vee$ ZF == 1) & be \\ \hline
+ 1010 & greater than or equal & SF == OF & ge \\ \hline
+ 1011 & less than & SF != OF & lt \\ \hline
+ 1100 & greater than & (ZF == 0 $\wedge$ SF == OF) & gt \\ \hline
+ 1101 & less than or equal & (ZF == 1 $\vee$ SF != OF) & le \\ \hline
+ 1110 & always & & \texttt{none} \\ \hline
+ 1111 & never & & nv \\ \hline
\end{tabular}
- \caption{codierung von conditions WARNING! may contain BUGS!!}
+ \caption{coding of conditions}
+ \label{tab:conds}
\end{table}
+%note: it seams that the definition of conditions on unsigned values depend on the instruction set. below is CF = 1 by x86/amd64 and avr, CF = 0 by arm. when cmp is defined as cmp r1, r2 == r1-r2 == is r1 COND r2 then arm looks more saner. the conditons marked with a X in the bitcode are open for change because of this unclear situation \Large{RFC} \normalsize
-above and below are for unsigned, greater and less for signed values
-
-note: it seams that the definition of conditions on unsigned values depend on the instruction set. below is CF = 1 by x86/amd64 and avr, CF = 0 by arm. when cmp is defined as cmp r1, r2 == r1-r2 == is r1 COND r2 then arm looks more saner. the conditons marked with a X in the bitcode are open for change because of this unclear situation \Large{RFC} \normalsize
-
-\begin{table}
+\begin{table}[hpt]
\centering
\begin{tabular}{|l|c|c|c|c|} \hline
Bit & 3 & 2 & 1 & 0 \\ \hline
Flag & SF & CF & OF & ZF \\ \hline
\end{tabular}
- \caption{billig PSW bitorder}
+ \caption{Bits in the PSW}
\end{table}
-ins ('32', 'movpf', 'Move from PSW/Stack', '4 | 5 | 4 | 1 | 18', 'Conditions | OpCode | Register Destination| stack | - ');
+ins ('32', 'movpf', 'Move from PSW/Stack', '4 | 5 | 4 | 1 | 18', 'Conditions | OpCode | Register Destination| st | - ');
-ins ('32', 'movpt', 'Move to PSW', '4 | 5 | 4 | 1 | 18', 'Conditions | OpCode | Register Source | stack | - ');
+ins ('32', 'movpt', 'Move to PSW/Stack', '4 | 5 | 4 | 1 | 18', 'Conditions | OpCode | Register Source | st | - ',
+'This instruction will set PSW or Stack to the value stored in the source register. When the move is to PSW the flags will be set like they are set in the source register.');
-ins ('32', 'ldw', 'Load word; needs to be aligned to 32bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment? ');
-ins ('32', 'ldh', 'Load half word; needs to be aligned to 16bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment? ');
-ins ('32', 'ldb', 'Load byte, 8bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment? ');
+ins ('32', 'ldw', 'Load word; needs to be aligned to 32bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
+ins ('32', 'ldh', 'Load half word; needs to be aligned to 16bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
+ins ('32', 'ldb', 'Load byte, 8bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement');
ins ('32', 'ldi', 'Load immediate', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | - | h/l | S ');
-ins ('32', 'stw', 'store word; needs to be aligned to 32bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment ');
-ins ('32', 'sth', 'store half word; needs to be aligned to 16bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment ');
-ins ('32', 'stb', 'store byte, 8bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment ');
+ins ('32', 'stw', 'store word; needs to be aligned to 32bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
+ins ('32', 'sth', 'store half word; needs to be aligned to 16bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
+ins ('32', 'stb', 'store byte, 8bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
-ins ('32', 'ldx', 'Load from programspace', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment ');
+ins ('32', 'ldx', 'Load from program space', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
-ins ('32', 'stx', 'Store to programspace', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
+ins ('32', 'stx', 'Store to program space', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
-ins ('32', 'stackop', 'pop/push/disc/fetch from/to stack', '4 | 5 | 4 | 2 | 17', 'Conditions | OpCode | Register Destination (not for disc) | Type | - ');
+ins ('32', 'stackop', 'pop/push/disc/fetch from/to stack', '4 | 5 | 4 | 2 | 17', 'Conditions | OpCode | Register Destination (not for disc) | Type | - ',
+'This operation should not be used direct, instead the aliases pop, push, disc and fetch should be used.');
#ins ('32', 'pop', 'pop from stack', '4 | 5 | 4 | 19', 'Conditions | OpCode | Register Destination | - ');
-\section{Design Desicions}
-
-\subsection{Howto save the return address of a call}
-
-stack or linkregister
-
-\subsection{howto implement uart, timer, \ldots}
-
-extension module vs. other
-
-\subsection{how does we define cmp on unsigned values}
-
-see note in conditions. there is a difference between x86/amd64/avr and arm.
-we will very likely go with arm (or?)
-
-\subsection{big/little endian}
+\section{Design Decisions}
+
+\begin{itemize}
+ \item Saving the return address of a call onto the stack and not into a link register
+ \item UART and timers are implemented as extension modules, which will allow us to implement additions modules for various functions
+ \item We defined that carry set is the condition below (unsigned lower)
+ \item We use little endian for encoding our data and program space
+\end{itemize}
-\begin{longtable}{|c|c|c|}
- \hline
+In table~\ref{tab:flags} the flags that can suffix instructions are described. If and which flags are available depends on the instruction.
- flag & function & default value \\ \hline
- C & carry & 0 (not set) \\ \hline
- SU & Status register update & 1 (set) \\ \hline
- H/L & use high or low 16-bits & L (not set) \\ \hline
- F & fill unused 16-bits with value of F & 0 (not set)\footnote{this means that andxf must be used if the not specified 16-bit should be preserve} \\ \hline
- ST & read/write stack instead of PSW & 0 (not set) \\ \hline
- S & sign extension & 0 (not set) \\ \hline
- +/- & branch taken or not taken & + (taken) \\ \hline
+\begin{longtable}{|c|c|c|}\hline
+ flag & function & default value \\ \hline
+ C & carry & 0 (not set) \\ \hline
+ SU & Status register update & 1 (set) \\ \hline
+ H/L & use high or low 16-bits & L (not set) \\ \hline
+ F & fill unused 16-bits with value of F & 0 (not set)\footnote{this means that andxf must be used, if the not specified 16-bit, should be preserve} \\ \hline
+ ST & read/write stack instead of PSW & 0 (not set) \\ \hline
+ S & sign extension & 0 (not set) \\ \hline
+ +/- & branch taken or not taken & + (taken) \\ \hline
+ A & if set the shift operation will be arithmetic instead of logic & 0 (logic) \\ \hline
\caption{ISA flag overview}
+ \label{tab:flags}
\end{longtable}
\tableofcontents
\newpage
+\input{cmp}
+
\input{desdis}
\input{conds}
-if a condition is not met, the instruction is executed but no changes (on data or flags) occure.
-\clearpage
-\input{callingconv}
+\input{callingconv}
\clearpage
-\section{instr}
+\section{Instruction Set Overview}
\input{flags}
-\subsection{arith}
-modifies all flags
+\subsection{arithmetic instructions}
+When not stated otherwise the following instructions will modify all flags of the PSW.
\input{arith}
-\subsection{logic}
-modifies zero and sign flag only. shifts may modify carry
-
-rotate?!?!?!?
-
-C is for shift to desc. a shift through carry
-F is for fill the unused
-ARITH makes logic right shift to arithemtic right shift
-
-not kann durch xorif rD, rS, \#0x7FF ersetzt werden. makro \_NOT daf\"ur.
-
+\subsection{logical instructions}
+When not stated otherwise the following instructions will only modify the zero and sign flag.
\input{logic}
-\subsection{data}
-
-use addi rD, rS, \#0 for mov rD, rS \\
-
+\subsection{data modifying instructions}
+When not stated otherwise the following instructions will not modify any flag.
\input{data}
-\subsection{misc}
+
+\subsection{miscellaneous instructions}
\input{misc}
# ins ('32', 'xori', 'Xor im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
-ins ('32', 'xorx', 'Xor im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | SU');
+ins ('32', 'xorx', 'Xor im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | SU',
+'', '', '', 'not rD - xorxlf rD, rD, 0xFFFF');
-ins ('32', 'lls', 'left shift', '4 | 5 | 4 | 4 | 5 | 8 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | C | SU');
+ins ('32', 'lls', 'left shift', '4 | 5 | 4 | 4 | 5 | 8 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | C | SU',
+'',' | Will change if C is set | | ');
-ins ('32', 'lrs', 'right shift', '4 | 5 | 4 | 4 | 5 | 7 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | ARITH | C | SU');
+ins ('32', 'lrs', 'right shift', '4 | 5 | 4 | 4 | 5 | 7 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | A | C | SU',
+'',' | Will change if C is set | | ');
-ins ('32', 'branch', 'Branch; jump to pc+imm', '4 | 5 | 16 | 3 | 2 | 1 | 1', 'Conditions | OpCode | Immediate | - | Branch/Call/Ret(i) | +/- | S');
+ins ('32', 'branch', 'Branch; jump to pc+imm', '4 | 5 | 16 | 3 | 2 | 1 | 1', 'Conditions | OpCode | Immediate | - | Type | +/- | S',
+'This instruction should be used with it\'s aliases branch, call, ret and reti. No flags will be affected by this instructions.');
#ins ('32', 'call', 'Call; save pc+4 in stack, jump to pc+imm', '4 | 5 | 16 | 5 | 1 | 1', 'Conditions | OpCode | Immediate | - | +/- | S');
#ins ('32', 'reti', 'reti', '4 | 5 | 23 ', 'Conditions | OpCode | -');
-ins ('32', 'cmp', 'compare (rS1 - rS2)', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register A (Source1) | Register B (Source2) | -');
+ins ('32', 'cmp', 'compare (rS1 - rS2)', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register A (Source1) | Register B (Source2) | -',
+'This instructions compares the two source registers by subtraction of register B from register A and setting the flags accordingly',
+'is set to the MSB of the result|is set if the subtraction has a carry out|is set if an overflow occurred|is set if the result is zero');
+
+ins ('32', 'cmpi', 'compare (rS1 - imm)', '4 | 5 | 4 | 16 | 3', 'Conditions | OpCode | Register A (Source1) | Immediate | -',
+'This instructions compares the the source register with the immediate be subtracting the immediate from register A and setting the flags accordingly',
+'is set to the MSB of the result|is set if the subtraction has a carry out|is set if an overflow occurred|is set if the result is zero');
-ins ('32', 'cmpi', 'compare (rS1 - imm)', '4 | 5 | 4 | 16 | 3', 'Conditions | OpCode | Register A (Source1) | Immediate | -');
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